docs(dn): Ibrahim Hashim 09/29/2025 (#409)

Co-authored-by: Ibrahim <[email protected]>

Author: ihash123

src/design_notebooks/2025fall/irh8156.md

@@ -15,4 +15,23 @@ Project Work:
   * [Program Counter]: Wrote and tested a simple pc16 verilog module for the RiSC-16 CPU:([PC Implementation](https://github.com/1fHu/ProcessorDesign/))
 
 Comments:
-  * My team implemented the Program counter. We saved the module as pc16.v and verified its behavior with simple simulations.
+  * My team implemented the Program counter. We saved the module as pc16.v and verified its behavior with simple simulations.
+
+
+## Week of 22 September 2025
+
+Project Work:
+  * [Testing Program Counter]: Tested the program counter with the test bench and made it compatible with it as well: ([Edited PC Implementation](https://github.com/ihash123/processorDesign))
+  * [ALU Implementation]: Wrote and tested a simple alu verilog module for the RiSC-16 CPU: ([ALU Implementation](https://github.com/ihash123/processorDesign))
+
+Comments:
+  * Worked with my team to test the program counter and implement the ALU as alu.v, and verified the behavior with simple tests.
+
+
+## Week of 29 September 2025
+
+Project Work:
+  * [Register File Implementation]: Wrote and tested a register file module for the RiSC-16 CPU: ([Register Implementation](https://github.com/ihash123/processorDesign))
+
+Comments:
+  * Worked with my team to create and test a register file for the RiSC-16 CPU, and tested it with the given testbench.