docs(dn): Lucy Zheng 10/26/2025 (#419)

Co-authored-by: Lucy Zheng <[email protected]>
Co-authored-by: Noahms12 <[email protected]>

Author: 3 people

src/design_notebooks/2025fall/lz3007.md

@@ -96,4 +96,15 @@ The biggest problem that I encountered while writing the testbench was the veril
 
 [GitHub: Data Memory Testbench](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/data_memory_tb2.v)
 
-**Notes:** Wires cannot be declared inside an intial block.  However, registers and integers can, but only at the top, before any executable statements.
+**Notes:** Wires cannot be declared inside an intial block.  However, registers and integers can, but only at the top, before any executable statements.
+
+## Week 7: 10/20/2025 - 10/26/2025
+
+* Completed Control and Data Memory modules
+* Passed all testcases for the Control module, using the provided testbench
+
+The Control module selects the value of the output signals: WErf, WEdmem, MUXalu1, MUXalu2, MUXrf, MUXtgt, FUNCalu, and MUXpc, based on the opcode input and the EQ signal (only for MUXpc). The first step was to find the corrosponding opcodes to the instructions using the [instruction set](https://user.eng.umd.edu/~blj/risc/RiSC-isa.pdf). The output signals were found by looking at the "Instruction Dataflow" diagrams for each instruction found in the [sequential implementation document](https://user.eng.umd.edu/~blj/risc/RiSC-seq.pdf). Another useful part of the document was the "Putting it all together" section that shows which modules the signals are sent to and describes what the signals are used for in the modules.
+
+[GitHub: Control Module Code](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/control2.v)
+
+**Notes:** There were some modules that were not used for some instructions and I was not sure if I needed to set the value of the signals that corrolate to the unused modules.