docs(dn): Lucy Zheng 10/19/2025 (#415)

* docs(dn): Lucy Zheng 10/19/2025

* docs(dn): Lucy Zheng 10/19/2025

---------

Co-authored-by: Lucy Zheng <[email protected]>

Author: Tyjihn

src/design_notebooks/2025fall/lz3007.md

@@ -23,7 +23,7 @@ We read the documentations on the [instruction set](https://user.eng.umd.edu/~bl
 
 We consulted Noah about the inputs and outputs of the PC. From my interpretation, he explained that there are 3 possible jumps for the output address: incrementing of 1, jumping to register B (JALR instruction), and jumping to the immediate value (BEQ instruction). For all 3 possible jumps, there should be an input with the 16-bit address. A multiplexer, given an input from another module, is used to choose which address would be the one the PC would actually point to.
 
-My partner and I had some differences in our interpretations, so we decided to write our code in separate files and push both versions to the repository ([Mine](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/program_counter_2.v) and [My Partner's](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/program_counter.v)).
+My partner and I had some differences in our interpretations, so we decided to write our code in separate files and push both versions to the repository ([My PC](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/pc2.v) and [My Partner's PC](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/program_counter.v)).
 
 **Remaining Questions/Notes:** We are unable to test our PC implementations, so we are not sure if either of them are correct. Since we are both taking Computer Architecture this semester, we are not yet sure how the ALU, PC, instruction memory, etc. work together.
 
@@ -45,7 +45,7 @@ The outputs, EQ (1-bit) and alu_out (16-bit), are selected based on the followin
 
 EQ is always being set to (src1 == src2) for every operation.
 
-For this week's project, my partner and I worked separately, meeting once to check each other's progress. Therefore, we worked on separate alu files: [Mine](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/alu2.v) and [My Partner's](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/alu.v).
+For this week's project, my partner and I worked separately, meeting once to check each other's progress. Therefore, we worked on separate alu files: [My ALU](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/alu2.v) and [My Partner's ALU](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/alu.v).
 
 **Remaining Question:** When fixing the PC, I was confused on why the reset input is negative and why the immediate value is inputted as 7-bit, not 16-bit.
 When working on the ALU, I had the following questions: When do you decide to make an input/output a register? When do you use a clock and when do you not (depending on if it iterates?).
@@ -70,6 +70,30 @@ There were many syntax and logic errors while testing my code with the testbench
     1) WE_rf bit is on
     2) source register is not register 0
 
-[Link to the Code](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/register2.v)
+[GitHub: Register File Code](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/register_file2.v)
 
-**Notes:** As I am writing this week's design notebook, I realize that it doesn't make sense to update the register using the value of the current instruction's rA. So, I am unsure as to why my current code (which does the above) passes all the test cases.
+**Notes:** As I am writing this week's design notebook, I realize that it doesn't make sense to update the register using the value of the current instruction's rA. So, I am unsure as to why my current code (which does the above) passes all the test cases.
+
+## Week 5: 10/06/2025 - 10/12/2025
+
+* Fixed register file using the updated testbench, passed all tests
+
+#### There was no new assignment for this week. 
+
+The previous testbench was incorrect because the Register File should not take the instruction, only the registers (rA, rB, rC). While fixing my Register File code using the fixed testbench, I realized the following about my code:
+1. The Register File should NOT sign-extend or left shift the immediate value; in fact, the register does not take the immediate value as an input at all.
+2. The opcode should not be an input for any of the modules, only the signals from the Control Unit and the outputs from other modules are inputs.
+
+[GitHub: Register File Code](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/register_file2.v)
+
+## Week 6: 10/13/2025 - 10/19/2025
+
+* Completed testbench for the Data Memory module
+
+At the start, I created different test cases, like the verfication of the initial values in the memory, testing if the reg_out value was written to the address (alu_out) if WE_dmem = 0 (should not write), and overwriting previously modified memory data. One problem I had was that I was checking all 65536 memory locations, which is very inefficient. So, I changed the tests cases to only check the few memory addresses that were being tested. 
+
+The biggest problem that I encountered while writing the testbench was the verilog syntax and logic. Within an initial block, declaring an integer after an executable statements would cause errors and displaying text right after one another would also cause errors. However, all these errors would point to the $finish line at the very end of the code, so it was difficult to know which lines were actually causing errors.
+
+[GitHub: Data Memory Testbench](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/data_memory_tb2.v)
+
+**Notes:** Wires cannot be declared inside an intial block.  However, registers and integers can, but only at the top, before any executable statements.