Adding support for a bit-twiddled 6805 variant

[philpem]

I'd like to add a couple of 6805 variants to Ghidra. These are unusual in that the wiring to the instruction latch has been shuffled -- and in one case, a few bits have been inverted.

It appears that the quick-and-obvious way to implement this is to copy-paste the 6805 SLEIGH definition for each chip and change the opcode byte and field comparisons to account for the bit twiddling.

Is there a way I can tell Ghidra to map the input opcode bytes into standard 6805 opcodes? That is to say, tell it that when it reads on opcode, it needs to shuffle some bits around and XOR the result with another constant?