RISC-V: Support for vendor extensions #5374
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gamelaster
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This is not the way to go about it. Creating a new sinc file with the extension and then including it in the right order. In this case, include it before riscv.custom.sinc is included would be the best generic way. Possibly mix in context register logic and ifdefs. The straight forward way would likely be a new T-Head slaspec file and include all the other sinc and vendor extension sinc files. If the riscv.custom.sinc is entirely unused it could be omitted that from that slaspec. Then add a new entry in the ldefs that is T-Head. |
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Many chips currently use T-Head cores (C906, E907, C910 etc.), whose contains custom RISC-V ISA extensions.
In this particular case, T-Head published it's specs here.
I would like to ask, what is recommended and best way of adding support for those instructions into Ghidra?
@florolf (I hope you don't mind the ping!) made support for some of them via hacky solution, directly modifying
.sinc
files (the changes are here), although I am not sure if this would be possible to get into upstream, without better support of vendor extensions in Ghidra.Thanks
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