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Have you tried to manually set |
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Hello,
I'm using ghidra with an architecture that contains some aliasing between registers. Simply put, it has 8-bit registers that alias with 16-bit registers.
The issue is sometimes this causes computation to happen in 16-bit register with ugly concat pcode, when in reality it was just two 8-bit variables.
Example:
Here uVar5 should have been split into two u8 variables.
Is there anything I can do to fix this?
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