diff --git a/.github/build_examples.py b/.github/build_examples.py new file mode 100644 index 0000000..ef2e6d4 --- /dev/null +++ b/.github/build_examples.py @@ -0,0 +1,26 @@ +import os +import sys + +PASS = True +Fails = [] + +for example in os.listdir("examples"): + print("Use PIO to build %s" % (example)) + pio_cmd = "pio run -d examples/%s" %(example) + print(pio_cmd) + sys.stdout.flush() + ret = os.system(pio_cmd) + if ret != 0: + print("%s build fail!" % (example)) + sys.stdout.flush() + PASS = False + Fails.append(example) + else: + print("%s build successfully!" % (example)) + +if PASS: + print("All examples compiled passed!") + sys.exit(0) +else: + print("These examples failed %s" %(Fails)) + sys.exit(1) diff --git a/.github/gcc.json b/.github/gcc.json new file mode 100644 index 0000000..0351108 --- /dev/null +++ b/.github/gcc.json @@ -0,0 +1,22 @@ +{ + "name": "toolchain-riscv-nuclei", + "version": "1.1.0", + "description": "Nuclei RISC-V toolchain", + "keywords": [ + "build tools", + "compiler", + "assembler", + "linker", + "preprocessor", + "risc-v" + ], + "license": "GPL-2.0-or-later", + "system": [ + "windows_x86", + "windows_amd64" + ], + "repository": { + "type": "git", + "url": "https://github.com/riscv-mcu/riscv-gnu-toolchain" + } +} diff --git a/.github/openocd.json b/.github/openocd.json new file mode 100644 index 0000000..93cb779 --- /dev/null +++ b/.github/openocd.json @@ -0,0 +1,22 @@ +{ + "name": "tool-openocd-nuclei", + "version": "1.1.0", + "description": "Open On-Chip Debugger branch with RISC-V Nuclei support", + "keywords": [ + "tools", + "debugger", + "debug server", + "uploader", + "risc-v" + ], + "homepage": "http://openocd.org", + "license": "GPL-2.0-or-later", + "system": [ + "windows_x86", + "windows_amd64" + ], + "repository": { + "type": "git", + "url": "https://github.com/riscv-mcu/riscv-openocd" + } +} \ No newline at end of file diff --git a/.github/prepare_tools.py b/.github/prepare_tools.py new file mode 100644 index 0000000..da39900 --- /dev/null +++ b/.github/prepare_tools.py @@ -0,0 +1,336 @@ +import os +import sys +import platform +import zipfile +import tarfile +import shutil +import json +import requests +import hashlib + +from urllib.parse import urlparse +import argparse +try: + import wget # Import the wget library + NOWGET = False +except: + NOWGET = True + pass + +PIOJSONLOC = "" +PREBLT_CACHE = "prebuilt_dlcache" +PREBLT_TOOLS = "prebuilt_tools" + +def download_file(url, file_name): + if NOWGET: + # Download the file using stream to avoid loading the entire file into memory + with requests.get(url, stream=True) as response: + with open(file_name, 'wb') as file: + shutil.copyfileobj(response.raw, file) + else: + wget.download(url, file_name) + pass + +def run_cmd(cmd): + print(cmd) + return os.system(cmd) + +def get_file_size(file_path): + return os.path.getsize(file_path) + +def calculate_md5(file_path, buffer_size=8192): + md5_hash = hashlib.md5() + with open(file_path, "rb") as file: + for chunk in iter(lambda: file.read(buffer_size), b""): + md5_hash.update(chunk) + return md5_hash.hexdigest() + +def md5sum_file(file_path): + if os.path.isfile(file_path) == False: + print("{file_path} not existed!") + return False + print(f"{file_path} size %s bytes" % (get_file_size(file_path))) + print(f"{file_path} md5 %s" % (calculate_md5(file_path))) + return True + +def download_with_progress(url, destination_folder, reuse=False): + file_name = os.path.join(destination_folder, os.path.basename(urlparse(url).path)) + if os.path.isdir(destination_folder) == False: + os.makedirs(destination_folder) + + if reuse == False and os.path.isfile(file_name): + os.remove(file_name) + # Download the file with progress bar + if os.path.isfile(file_name) == False: + download_file(url, file_name) + print("%s is downloaded!" % (file_name)) + else: + print("%s already downloaded!" % (file_name)) + md5sum_file(file_name) + + return file_name + +def download_and_extract(url, extract_folder, reuse=False): + print("Downloading %s" % (url)) + file_name = download_with_progress(url, PREBLT_CACHE, reuse) + + if os.path.isdir(extract_folder) == False: + os.makedirs(extract_folder) + + print("Extracting %s to %s" % (file_name, extract_folder)) + # Extract the contents + if file_name.endswith(".zip"): + print(f"Unzip {file_name}") + with zipfile.ZipFile(file_name, "r") as zip_ref: + zip_ref.extractall(extract_folder) + elif file_name.endswith(".tar.gz") or file_name.endswith(".tgz"): + print(f"Untar {file_name}") + with tarfile.open(file_name, "r:gz") as tar_ref: + tar_ref.extractall(extract_folder) + else: + print("Unsupported archive file %s" % (file_name)) + + print("List in this directory %s: %s" %(extract_folder, os.listdir(extract_folder))) + # Remove the temporary file + if reuse == False and os.path.isfile(file_name): + os.remove(file_name) + pass + +def modify_json_file(old_file, file_path, system_value, force=False): + if os.path.isfile(file_path): + print("%s already existed!" % (file_path)) + if force == False: + return + print("Force reinstall this %s file!" % (file_path)) + + # Read the existing JSON file + with open(old_file, "r") as json_file: + data = json.load(json_file) + + # Modify the 'system' key + data["system"] = system_value + + # Write back to the JSON file + with open(file_path, "w") as json_file: + json.dump(data, json_file, indent=4) + + print("%s is ready!" % (file_path)) + pass + +def check_isdir(uri): + try: + return os.path.isdir(uri) + except: + return False + +def setup_nuclei_studio(toolsdir, nuclei_uri, system_value, reuse, force=False): + if check_isdir(nuclei_uri) == False: + # Download and extract NucleiStudio + nuclei_folder = toolsdir + download_and_extract(nuclei_uri, nuclei_folder, reuse) + # Fix nuclei studio path + for item in os.listdir(nuclei_folder): + itemdir = os.path.join(nuclei_folder, item) + if os.path.isdir(itemdir) and item.startswith("NucleiStudio") and item != "NucleiStudio": + nsidepath = os.path.join(nuclei_folder, item) + newpath = os.path.join(nuclei_folder, "NucleiStudio") + if len(os.listdir(nsidepath)) == 1: + nsidepath = os.path.join(nsidepath, "NucleiStudio") + # rename old ide path to new ide path + # such as NucleiStudio_IDE_202310/NucleiStudio -> NucleiStudio + print("Move %s -> %s" % (nsidepath, newpath)) + os.rename(nsidepath, newpath) + break + nsideloc = os.path.join(nuclei_folder, "NucleiStudio") + else: + nsideloc = nuclei_uri + + # Copy and modify nuclei_openocd.json + openocd_json_path = os.path.join(nsideloc, "toolchain", "openocd", "package.json") + modify_json_file(os.path.join(PIOJSONLOC, "openocd.json"), openocd_json_path, system_value, force) + + # Copy and modify nuclei_gcc.json + gcc_json_path = os.path.join(nsideloc, "toolchain", "gcc", "package.json") + modify_json_file(os.path.join(PIOJSONLOC, "gcc.json"), gcc_json_path, system_value, force) + pass + +def setup_gd_openocd(toolsdir, gd_openocd_uri, system_value, nsideloc, reuse, force=False): + if gd_openocd_uri == "" or os.path.isfile(os.path.join(PIOJSONLOC, "gd_openocd.json")) == False: + print("Ignore setup for gd openocd, maybe latest nuclei openocd already merged support for gd openocd!") + return + gd_openocd_folder_name = "gd_openocd" + destination_folder = os.path.join(nsideloc, "toolchain", gd_openocd_folder_name) + temp_folder = None + if check_isdir(gd_openocd_uri) == False: + # Download and extract gd32-openocd to a temporary folder + tools_folder = toolsdir + temp_folder = os.path.join(tools_folder, "temp_gd_openocd") + if temp_folder and os.path.isdir(temp_folder): + shutil.rmtree(temp_folder) + download_and_extract(gd_openocd_uri, temp_folder, reuse) + org_folder = os.path.join(temp_folder, os.listdir(temp_folder)[0]) + else: + org_folder = gd_openocd_uri + if os.path.isdir(os.path.join(org_folder, "scripts")) == False: + print("This %s may not be a valid openocd package!" % (org_folder)) + sys.exit(1) + # Rename the old openocd folder to gd_openocd + if os.path.isdir(destination_folder) == False or force == True: + if force == True and os.path.isdir(destination_folder): + print("Remove existing %s" % (destination_folder)) + shutil.rmtree(destination_folder) + print("Copy %s -> %s" % (org_folder, destination_folder)) + shutil.copytree(org_folder, destination_folder) + else: + print("%s already exist!" % (destination_folder)) + + # Remove the temporary extraction folder + if temp_folder and os.path.isdir(temp_folder): + shutil.rmtree(temp_folder) + + # Copy and modify gd_openocd.json + gd_openocd_json_path = os.path.join(destination_folder, "package.json") + modify_json_file(os.path.join(PIOJSONLOC, "gd_openocd.json"), gd_openocd_json_path, system_value, force) + pass + + +PIOJSONLOC = ".github" +REUSE_ARCHIVE = True + +def is_valid_url(url): + try: + if url and urlparse(url).netloc != "": + return True + except: + pass + return False + +def prepare_tools(prebltloc=PREBLT_TOOLS, nside=None, gdocd=None, force=False): + ostype = platform.system() + print("Setup Tools for %s" % (ostype)) + if platform.architecture()[0] != '64bit': + print("ERROR: Currently only support 64bit OS!") + sys.exit(1) + # if you provide a real installed nuclei studio path + nsideloc = os.path.join(prebltloc, "NucleiStudio") + # you can customize the url to your own url + nuclei_win_url = "https://download.nucleisys.com/upload/files/nucleistudio/NucleiStudio_IDE_202406-win64.zip" + gd_openocd_win_url = "" + nuclei_linux_url = "https://download.nucleisys.com/upload/files/nucleistudio/NucleiStudio_IDE_202406-lin64.tgz" + gd_openocd_linux_url = "" + + nside_uri = None + gdocd_uri = None + supported_oses = [] + if ostype == "Windows": + # Windows Setup + nside_uri = nuclei_win_url + gdocd_uri = gd_openocd_win_url + supported_oses = ["windows_amd64"] + elif ostype == "Linux": + # Linux Setup + nside_uri = nuclei_linux_url + gdocd_uri = gd_openocd_linux_url + supported_oses = ["linux_x86_64"] + else: + print("ERROR: Unsupported OS") + sys.exit(1) + + # if nside or gdocd are specified + if nside and (os.path.isdir(nside) and os.path.isfile(os.path.join(nside, "NucleiStudio.ini"))): + print("INFO: Using already installed Nuclei Studio in %s!" % (nside)) + nside_uri = nside + nsideloc = nside + elif is_valid_url(nside): + print("INFO: Using a different url %s to download Nuclei Studio!" % (nside)) + nside_uri = nside + if gdocd and os.path.isdir(gdocd) and os.path.isdir(os.path.join(gdocd, "scripts")): + print("INFO: Using already installed GD OpenOCD in %s!" % (gdocd)) + gdocd_uri = gdocd + elif is_valid_url(gdocd): + print("INFO: Using a different url %s to download gd32 openocd!" % (gdocd)) + gdocd_uri = nside + + setup_nuclei_studio(prebltloc, nside_uri, supported_oses, REUSE_ARCHIVE, force) + setup_gd_openocd(prebltloc, gdocd_uri, supported_oses, nsideloc, REUSE_ARCHIVE, force) + pass + +def get_nside_loc(prebltloc=PREBLT_TOOLS, nside=None): + if nside and os.path.isdir(nside) and os.path.isfile(os.path.join(nside, "NucleiStudio.ini")): + return nside + return os.path.join(prebltloc, "NucleiStudio") + + +def install_pio_packages(nsideloc=os.path.join(os.getcwd(), PREBLT_TOOLS, "NucleiStudio"), nsdk_url="https://github.com/Nuclei-Software/nuclei-sdk"): + if os.path.isfile("platform.py") == False: + print("Not in platform nuclei folder, exit") + return False + try: + import platformio as pio + except: + print("PlatformIO maybe not installed or not set in PATH, please check!") + return False + if pio.VERSION[0] < 6: + print("PlatformIO %s need to >= 6.x, see https://docs.platformio.org/en/latest/core/history.html#platformio-core-6" % (".".join(pio.VERSION))) + return False + nside_tools_loc = os.path.join(nsideloc, "toolchain") + if os.path.isdir(nside_tools_loc) == False: + print("%s not exist! Please Check!" % (nside_tools_loc)) + sys.exit(1) + print("Install required tool packages located in %s" % (nside_tools_loc)) + sys.stdout.flush() + run_cmd("pio pkg install -g -t symlink://%s" % (os.path.join(nside_tools_loc, "gcc"))) + run_cmd("pio pkg install -g -t symlink://%s" % (os.path.join(nside_tools_loc, "openocd"))) + if os.path.exists(os.path.join(nside_tools_loc, "gd_openocd")) == True: + run_cmd("pio pkg install -g -t symlink://%s" % (os.path.join(nside_tools_loc, "gd_openocd"))) + print("Install framework-nuclei-sdk from %s" % (nsdk_url)) + sys.stdout.flush() + if os.path.isdir(nsdk_url): + run_cmd("pio pkg install -g -t symlink://%s" % (os.path.realpath(nsdk_url))) + else: + run_cmd("pio pkg install -g -t %s" % (nsdk_url)) + print("Install platform-nuclei from current folder!") + run_cmd("pio pkg install -g -p symlink://%s" % (os.getcwd())) + print("List installed pio packages") + sys.stdout.flush() + run_cmd("pio pkg list -g") + return True + +if __name__ == '__main__': + parser = argparse.ArgumentParser(description='Prepare Nuclei Tools and Install PIO Packages.') + parser.add_argument('--install', action='store_true', help="Always install required tools") + parser.add_argument('--into', default=PREBLT_TOOLS, help="Install required tools to desired location") + parser.add_argument('--pio', action='store_true', help="Setup PIO Package") + parser.add_argument('--sdk', "-s", default="https://github.com/Nuclei-Software/nuclei-sdk", help='URL or PATH of Nuclei SDK >= 0.6.0') + parser.add_argument('--ide', help='Nuclei Studio IDE PATH, such as C:\\Software\\NucleiStudio') + parser.add_argument('--gdocd', help='GD OpenOCD PATH, such as C:\\Work\\openocd_v1.2.2\\xpack-openocd-0.11.0-3, if using Nuclei Studio 2024.06, no need to install gd openocd') + parser.add_argument('--force', action='store_true', help='Force reinstall the package.json file if existed!') + + args = parser.parse_args() + + needinstall = True + if os.path.isdir(PREBLT_CACHE): + print("Prebuilt tool download cache directory existed!") + print("Content in this directory: %s" % (os.listdir(PREBLT_CACHE))) + else: + print("No prebuilt tool download cache found!") + + prebuiltloc = args.into + if os.path.isdir(prebuiltloc) and len(os.listdir(prebuiltloc)) >= 1: + needinstall = False + print("%s existed, maybe tools already installed!" % (prebuiltloc)) + if args.install: + if prebuiltloc == PREBLT_TOOLS: + shutil.rmtree(prebuiltloc) + needinstall = True + + if needinstall: + prepare_tools(prebuiltloc, args.ide, args.gdocd, args.force) + + nsideloc = get_nside_loc(prebuiltloc, args.ide) + if args.pio: + print("Install pio required packages") + install_pio_packages(nsideloc, args.sdk) + + print("Setup completed successfully!") + sys.exit(0) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 0000000..e7d6075 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,49 @@ +name: Build Examples + +on: [push, pull_request] + +jobs: + build: + strategy: + fail-fast: false + matrix: + os: [ubuntu-20.04, ubuntu-latest, windows-latest] + runs-on: ${{ matrix.os }} + steps: + - uses: actions/checkout@v4 + with: + submodules: "recursive" + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: "3.9" + + - name: Install dependencies + run: | + pip install -U https://github.com/platformio/platformio/archive/develop.zip + pip install wget requests + + - name: Caching Nuclei Tools + uses: actions/cache@v3 + with: + path: prebuilt_dlcache + key: build + + - name: Install and Setup Nuclei Tools + run: | + python3 -u .github/prepare_tools.py --install + + - name: Upload cached packages + uses: actions/upload-artifact@v3 + with: + name: prebuilt_caching_${{ matrix.os }} + path: | + prebuilt_dlcache + + - name: Setup PIO Packages + run: | + python3 -u .github/prepare_tools.py --pio + + - name: Build examples + run: | + python3 -u .github/build_examples.py \ No newline at end of file diff --git a/.gitignore b/.gitignore index c184a43..f4d0030 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ *.pyc .vscode .pio +prebuilt_* \ No newline at end of file diff --git a/.travis.yml b/.travis.yml deleted file mode 100644 index 0b57746..0000000 --- a/.travis.yml +++ /dev/null @@ -1,27 +0,0 @@ -language: python -python: - - "3.6" - -env: - - PLATFORMIO_PROJECT_DIR=examples/coremark - - PLATFORMIO_PROJECT_DIR=examples/dhrystone - - PLATFORMIO_PROJECT_DIR=examples/whetstone - - PLATFORMIO_PROJECT_DIR=examples/helloworld - - PLATFORMIO_PROJECT_DIR=examples/demo_nice - - PLATFORMIO_PROJECT_DIR=examples/demo_eclic - - PLATFORMIO_PROJECT_DIR=examples/demo_timer - - PLATFORMIO_PROJECT_DIR=examples/demo_dsp - - PLATFORMIO_PROJECT_DIR=examples/freertos_demo - - PLATFORMIO_PROJECT_DIR=examples/ucosii_demo - - PLATFORMIO_PROJECT_DIR=examples/rtthread_demo - - PLATFORMIO_PROJECT_DIR=examples/rtthread_msh - -install: - - pip install -U https://github.com/platformio/platformio/archive/develop.zip - - platformio platform install file://. - -script: - - platformio run -d $PLATFORMIO_PROJECT_DIR - -notifications: - email: false diff --git a/README.md b/README.md index 61dce68..f4f7e33 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,17 @@ # Nuclei: development platform for [PlatformIO](https://platformio.org) -[![Build Status](https://travis-ci.com/Nuclei-Software/platform-nuclei.svg?branch=master)](https://travis-ci.com/Nuclei-Software/platform-nuclei) -[![Build status](https://ci.appveyor.com/api/projects/status/cy7mc2qbd5yalr41?svg=true)](https://ci.appveyor.com/project/fanghuaqi/platform-nuclei) + +[![Build Examples](https://github.com/Nuclei-Software/platform-nuclei/actions/workflows/build.yml/badge.svg?branch=feature%2Fgd32vw55x)](https://github.com/Nuclei-Software/platform-nuclei/actions/workflows/build.yml) + +> [!NOTE] +> +> If you want to use **platform-nuclei** with latest nuclei sdk(>=0.6.0) and toolchain offline, please follow +> the steps list in [.github/workflows/build.yml](.github/workflows/build.yml). +> +> Here is a [sample online doc](https://doc.weixin.qq.com/doc/w3_ASUAMQZqALwutPQJm8OTOOPy1OobX?scode=ABcAKgdSAFcdHdWdviASUAMQZqALw) in chinese to tell you how to use **platform-nuclei** for [GD32VW553H Evaluation Kit](https://www.gigadevice.com/product/mcu/risc-v/gd32vw553kmq7). +> +> And you can also take a try with **Nuclei Studio IDE**, which is built on Eclipse embedded CDT, see https://www.nucleisys.com/download.php#tools +> +> If you want **better online platformio support for you and your customer**, **highly recommended** to use https://registry.platformio.org/ [Nuclei System Technology](https://www.nucleisys.com/) is a professional RISC-V IP product company. It provides various RISC-V IP products which can meet the requirements of the AIoT era. diff --git a/appveyor.yml b/appveyor.yml deleted file mode 100644 index d736ffb..0000000 --- a/appveyor.yml +++ /dev/null @@ -1,25 +0,0 @@ -build: off -environment: - - matrix: - - PLATFORMIO_PROJECT_DIR: "examples/coremark" - - PLATFORMIO_PROJECT_DIR: "examples/dhrystone" - - PLATFORMIO_PROJECT_DIR: "examples/whetstone" - - PLATFORMIO_PROJECT_DIR: "examples/helloworld" - - PLATFORMIO_PROJECT_DIR: "examples/demo_eclic" - - PLATFORMIO_PROJECT_DIR: "examples/demo_nice" - - PLATFORMIO_PROJECT_DIR: "examples/demo_timer" - - PLATFORMIO_PROJECT_DIR: "examples/demo_dsp" - - PLATFORMIO_PROJECT_DIR: "examples/freertos_demo" - - PLATFORMIO_PROJECT_DIR: "examples/ucosii_demo" - - PLATFORMIO_PROJECT_DIR: "examples/rtthread_demo" - - PLATFORMIO_PROJECT_DIR: "examples/rtthread_msh" - -install: -- cmd: git submodule update --init --recursive -- cmd: SET PATH=C:\Python36\Scripts;%PATH% -- cmd: pip install -U https://github.com/platformio/platformio/archive/develop.zip -- cmd: platformio platform install file://. - -test_script: -- cmd: platformio run -d %PLATFORMIO_PROJECT_DIR% diff --git a/boards/gd32vf103c_longan_nano.json b/boards/gd32vf103c_longan_nano.json index 0ca5a43..a29bda8 100644 --- a/boards/gd32vf103c_longan_nano.json +++ b/boards/gd32vf103c_longan_nano.json @@ -31,8 +31,6 @@ "flash_start": "0x08000000", "protocol": "rv-link", "protocols": [ - "altera-usb-blaster", - "gd-link", "jlink", "rv-link" ] diff --git a/boards/gd32vf103c_t_display.json b/boards/gd32vf103c_t_display.json index 4911dec..b34fc43 100644 --- a/boards/gd32vf103c_t_display.json +++ b/boards/gd32vf103c_t_display.json @@ -31,8 +31,6 @@ "flash_start": "0x08000000", "protocol": "rv-link", "protocols": [ - "altera-usb-blaster", - "gd-link", "jlink", "rv-link" ] diff --git a/boards/gd32vf103v_eval.json b/boards/gd32vf103v_eval.json index ae68095..2e3c25f 100644 --- a/boards/gd32vf103v_eval.json +++ b/boards/gd32vf103v_eval.json @@ -29,12 +29,10 @@ "maximum_ram_size": 32768, "maximum_size": 131072, "flash_start": "0x08000000", - "protocol": "rv-link", + "protocol": "gd-link", "protocols": [ - "altera-usb-blaster", - "gd-link", "jlink", - "rv-link" + "gd-link" ] }, "url": "https://www.gigadevice.com/", diff --git a/boards/gd32vf103v_rvstar.json b/boards/gd32vf103v_rvstar.json index 0770724..c032b14 100644 --- a/boards/gd32vf103v_rvstar.json +++ b/boards/gd32vf103v_rvstar.json @@ -35,8 +35,6 @@ "flash_start": "0x08000000", "protocol": "rv-link", "protocols": [ - "altera-usb-blaster", - "gd-link", "jlink", "rv-link" ] diff --git a/boards/gd32vw553h_eval.json b/boards/gd32vw553h_eval.json new file mode 100644 index 0000000..8137873 --- /dev/null +++ b/boards/gd32vw553h_eval.json @@ -0,0 +1,45 @@ +{ + "build": { + "f_cpu": "160000000L", + "hwids": [ + [ + "0x0403", + "0x6010" + ] + ], + "core": "n307fd", + "arch_ext": "_zba_zbb_zbc_zbs_xxldspn1x", + "soc": "gd32vw55x", + "mcu": "gd32vw553h", + "download": "flashxip", + "ldscript": "", + "download_modes": [ + "flashxip", + "sram" + ] + }, + "debug": { + "jlink_device": "GD32VW553HM", + "svd_path": "GD32VW55X.svd", + "onboard_tools": [ + "gd-link" + ] + }, + "frameworks": [ + "nuclei-sdk" + ], + "name": "GD32VW553H-EVAL Board", + "upload": { + "maximum_ram_size": 294912, + "maximum_size": 2097152, + "flash_start": "0x08000000", + "sram_start": "0x20000000", + "protocol": "gd-link", + "protocols": [ + "jlink", + "gd-link" + ] + }, + "url": "https://www.gigadevice.com/product/mcu/risc-v", + "vendor": "GigaDevice" +} diff --git a/boards/hbird_eval.json b/boards/hbird_eval.json deleted file mode 100644 index 419a50c..0000000 --- a/boards/hbird_eval.json +++ /dev/null @@ -1,46 +0,0 @@ -{ - "build": { - "f_cpu": "16000000L", - "hwids": [ - [ - "0x0403", - "0x6010" - ] - ], - "mcmodel": "medany", - "soc": "demosoc", - "mcu": "demosoc", - "core": "n307fd", - "download": "ilm", - "download_modes": [ - "ilm", - "flash", - "flashxip", - "ddr" - ] - }, - "debug": { - "jlink_device": "RISC-V", - "svd_path": "DEMOSOC.svd", - "onboard_tools": [ - "rv-link" - ] - }, - "frameworks": [ - "nuclei-sdk" - ], - "name": "Nuclei FPGA Evaluation Kit(MCU200T/DDR200T)", - "upload": { - "maximum_ram_size": 65536, - "maximum_size": 65536, - "ilm_start": "0x80000000", - "ddr_start": "0xA0000000", - "flash_start": "0x20000000", - "protocol": "rv-link", - "protocols": [ - "rv-link" - ] - }, - "url": "https://nucleisys.com/", - "vendor": "Nuclei" -} diff --git a/boards/nuclei_fpga_eval.json b/boards/nuclei_fpga_eval.json index 419a50c..3444a01 100644 --- a/boards/nuclei_fpga_eval.json +++ b/boards/nuclei_fpga_eval.json @@ -7,21 +7,25 @@ "0x6010" ] ], - "mcmodel": "medany", - "soc": "demosoc", - "mcu": "demosoc", + "soc": "evalsoc", + "mcu": "evalsoc", "core": "n307fd", + "arch_ext": "", "download": "ilm", + "toolchain": "nuclei_gnu", + "stdclib": "newlib_small", + "ldscript": "", "download_modes": [ "ilm", "flash", "flashxip", + "sram", "ddr" ] }, "debug": { "jlink_device": "RISC-V", - "svd_path": "DEMOSOC.svd", + "svd_path": "EVALSOC.svd", "onboard_tools": [ "rv-link" ] @@ -29,16 +33,18 @@ "frameworks": [ "nuclei-sdk" ], - "name": "Nuclei FPGA Evaluation Kit(MCU200T/DDR200T)", + "name": "Nuclei FPGA Evaluation Kit", "upload": { "maximum_ram_size": 65536, "maximum_size": 65536, "ilm_start": "0x80000000", "ddr_start": "0xA0000000", + "sram_start": "0xA0000000", "flash_start": "0x20000000", "protocol": "rv-link", "protocols": [ - "rv-link" + "rv-link", + "jlink" ] }, "url": "https://nucleisys.com/", diff --git a/builder/frameworks/_bare.py b/builder/frameworks/_bare.py index 7192c8f..5b5da6e 100644 --- a/builder/frameworks/_bare.py +++ b/builder/frameworks/_bare.py @@ -26,18 +26,12 @@ "-x", "assembler-with-cpp", ], CCFLAGS=[ - "-Os", - "-Wall", # show warnings "-ffunction-sections", "-fdata-sections", "-fno-common" ], LINKFLAGS=[ - "-Os", - "-ffunction-sections", - "-fdata-sections", - "-fno-common", "-Wl,--gc-sections" ], diff --git a/builder/frameworks/nuclei-sdk.py b/builder/frameworks/nuclei-sdk.py index 5300a32..db0aa0e 100644 --- a/builder/frameworks/nuclei-sdk.py +++ b/builder/frameworks/nuclei-sdk.py @@ -37,29 +37,11 @@ assert isdir(FRAMEWORK_DIR) - def is_valid_soc(soc): return isdir(join(FRAMEWORK_DIR, "SoC", soc)) - -def get_extra_soc_board_incdirs(soc, board): - def _get_inc_dirs(path): - incdirs = [] - if isdir(path): - for dir in listdir(path): - dir_path = join(path, dir) - if isdir(dir_path): - incdirs.append(dir_path) - return incdirs - - soc_inc_dir_root = join(FRAMEWORK_DIR, "SoC", soc, "Common", "Include") - board_inc_dir_root = join(FRAMEWORK_DIR, "SoC", soc, "Board", board, "Include") - - return _get_inc_dirs(soc_inc_dir_root) + _get_inc_dirs(board_inc_dir_root) - - def select_rtos_package(build_rtos): - SUPPORTED_RTOSES = ("FreeRTOS", "UCOSII", "RTThread") + SUPPORTED_RTOSES = ("FreeRTOS", "UCOSII", "RTThread", "ThreadX") selected_rtos = None build_rtos = build_rtos.strip().lower() for rtos in SUPPORTED_RTOSES: @@ -67,239 +49,370 @@ def select_rtos_package(build_rtos): selected_rtos = rtos return selected_rtos - -def parse_nuclei_soc_predefined_cores(core_mk): +def parse_nuclei_predefined_cores(core_mk): if not os.path.isfile(core_mk): return dict() core_arch_abis = dict() - core_arch_abi_re = re.compile(r'^([A-Z]+\d+[A-Z]*)_CORE_ARCH_ABI\s*=\s*(rv\d+\w*)\s+(i*lp\d+\w*)') + core_arch_abi_re = re.compile(r'^([A-Z]+\d+[A-Z]*)_CORE_ARCH_ABI\s*=\s*(rv\d+\w*)\s+(i*lp\d+\w*)\s+(nuclei-\d*-series)') with open(core_mk, "r") as core_mk_file: for line in core_mk_file.readlines(): line = line.strip() matches = core_arch_abi_re.match(line) if matches: core_lower = matches.groups()[0].lower() - core_arch_abis[core_lower] = (matches.groups()[1:3]) + core_arch_abis[core_lower] = (matches.groups()[1:]) return core_arch_abis - -core_arch_abis = parse_nuclei_soc_predefined_cores(FRAMEWORK_NUCLEI_SOC_CORES_MK) - +def find_suitable_download(download, download_modes): + if download_modes and type(download_modes) == list and len(download_modes) > 1: + if download not in download_modes: + print("DOWNLOAD MODE is %s, not supported in %s" % (download, download_modes)) + download = download_modes[0] + print("Change to use DOWNLOAD MODE %s now!!!!!" % (download)) + return download + +def find_suitable_ldscript(socdir, soc, board, download, variant=""): + soc_variant = soc + if board == "gd32vf103c_longan_nano": + soc_variant = "gd32vf103x8" if variant == "lite" else "gd32vf103xb" + + if download: + ld_script = "gcc_%s_%s.ld" % (soc_variant, download) + else: + ld_script = "gcc_%s.ld" % build_soc + + build_ldscript = join(socdir, "Board", build_board, "Source", "GCC", ld_script) + return build_ldscript + +def find_arch_abi_tune_cmodel(core, arch, abi, tune, cmodel, splist): + if not (arch and abi) and core in splist: + if len(splist[core]) == 2: + arch, abi = splist[core] + elif len(splist[core]) == 3: + arch, abi, tune = splist[core] + if not cmodel: + cmodel = "medlow" if "rv32" in arch else "medany" + + return [arch, abi, tune, cmodel] + +def get_arch_flags(arch, abi, tune, cmodel, archext, toolchain): + optlist = ["-g"] + optlist.append("-march=%s%s" % (arch, archext)) if arch else optlist + optlist.append("-mabi=%s" % (abi)) if abi else optlist + optlist.append("-mcmodel=%s" % (cmodel)) if cmodel else optlist + if toolchain == "nuclei_gnu": + optlist.append("-mtune=%s" % (tune)) if tune else optlist + return optlist + +# Get core arch/abi/mtune list +core_arch_abis = parse_nuclei_predefined_cores(FRAMEWORK_NUCLEI_SOC_CORES_MK) + +# get build soc build_soc = board.get("build.soc", "").strip() if not build_soc: - sys.stderr.write( - "build.soc is not defined in board description json file, please check!") + print("Error! build.soc is not defined in board description json file %s.json, please check!" % (build_board)) env.Exit(1) -if build_soc == "hbird": - print("%s SoC is deprecated, please use demosoc instead!" %(build_soc)) - build_soc = "demosoc" +# Check whether soc is supported by this nuclei sdk +if build_soc in ("hbird", "demosoc"): + if not is_valid_soc(build_soc): + print("Warning! %s SoC is deprecated, please use evalsoc instead!" %(build_soc)) + build_soc = "evalsoc" -BUILTIN_ALL_DOWNLOADED_MODES = ("ilm", "flash", "flashxip", "ddr") +FRAMEWORK_SOC_DIR = "" +if not is_valid_soc(build_soc): + print("Warning! Could not find %s SoC support package in framework-nuclei-sdk" % build_soc) + soc_framework_pkg = "framework-nuclei-sdk-%s" % build_soc + try: + # you can add an extra platform_packages see https://docs.platformio.org/en/latest/projectconf/sections/env/options/platform/platform_packages.html + print("Try to find SoC support package from pio package %s, assume it is provided!" % (soc_framework_pkg)) + FRAMEWORK_SOC_DIR = env.PioPlatform().get_package_dir(soc_framework_pkg) + print("Using SoC support package source code from %s" % (soc_framework_pkg)) + except KeyError: + print("Error! If you confirm this pio package %s existed, please install it!" % (soc_framework_pkg)) + env.Exit(1) + +# Set Nuclei SDK Root directory +build_nsdk_dir = FRAMEWORK_DIR +build_nsdk_socdir = os.path.join(FRAMEWORK_DIR, "SoC", build_soc) +if FRAMEWORK_SOC_DIR != "": + build_nsdk_socdir = FRAMEWORK_SOC_DIR build_core = board.get("build.core", "").lower().strip() -build_mabi = board.get("build.mabi", "").lower().strip() +build_arch_ext = board.get("build.arch_ext", "").lower().strip() + build_march = board.get("build.march", "").lower().strip() -build_mcmodel = board.get("build.mcmodel", "medany").lower().strip() +build_mabi = board.get("build.mabi", "").lower().strip() +build_mtune = board.get("build.mtune", "").lower().strip() +build_mcmodel = board.get("build.mcmodel", "").lower().strip() + build_rtos = board.get("build.rtos", "").lower().strip() build_rtthread_msh = board.get("build.rtthread_msh", "").lower().strip() build_variant = board.get("build.variant", "").lower().strip() +build_toolchain = board.get("build.toolchain", "").lower().strip() +build_download = board.get("build.download", "").lower().strip() +build_download_modes = board.get("build.download_modes", []) +build_stdclib = board.get("build.stdclib", "newlib_small").lower().strip() +build_simu = board.get("build.simu", "").lower().strip() +build_ncrtio = board.get("build.ncrtio", "uart").lower().strip() +build_stacksz = board.get("build.stacksz", "").lower().strip() +build_heapsz = board.get("build.heapsz", "").lower().strip() +build_ldscript = board.get("build.ldscript", "").lower().strip() +build_nmsis_lib = board.get("build.nmsis_lib", "").lower().strip() +build_nmsis_lib_arch = board.get("build.nmsis_lib_arch", "").lower().strip() +build_usb_driver = board.get("build.usb_driver", "").lower().strip() +build_smp = board.get("build.smp", "").lower().strip() +build_boot_hartid = board.get("build.boot_hartid", "").lower().strip() +build_hartid_ofs = board.get("build.hartid_ofs", "").lower().strip() +build_sysclk = board.get("build.sysclk", "").lower().strip() +build_clksrc = board.get("build.clksrc", "").lower().strip() +build_hxtal_value = board.get("build.hxtal_value", "").lower().strip() selected_rtos = select_rtos_package(build_rtos) -build_download_mode = board.get("build.download", "").lower().strip() +build_download = find_suitable_download(build_download, build_download_modes) -build_supported_download_modes = board.get("build.download_modes", []) +if not build_ldscript: + build_ldscript = find_suitable_ldscript(build_nsdk_socdir, build_soc, build_board, build_download, build_variant) -# Get supported download modes -build_supported_download_modes = [mode.lower().strip() for mode in build_supported_download_modes] -# intersection of BUILTIN_ALL_DOWNLOADED_MODES, build.download_modes, build.download -mixed_supported_download_modes = list(set(BUILTIN_ALL_DOWNLOADED_MODES).intersection( - build_supported_download_modes)) - -if build_soc == "demosoc": - if build_download_mode not in mixed_supported_download_modes: - # If build.download not defined for Nuclei demosoc SoC, use default "ILM" - chosen_download_mode = "ilm" if len(mixed_supported_download_modes) == 0 else mixed_supported_download_modes[0] - print("Download mode %s is not supported for SOC %s, use default download mode %s" \ - % (build_download_mode, build_soc, chosen_download_mode)) - build_download_mode = chosen_download_mode -else: - if build_download_mode not in mixed_supported_download_modes: - chosen_download_mode = "flashxip" if len(mixed_supported_download_modes) == 0 else mixed_supported_download_modes[0] - print("Download mode %s is not supported for SOC %s, use default download mode %s" \ - % (build_download_mode, build_soc, chosen_download_mode)) - build_download_mode = chosen_download_mode - -print("Supported downloaded modes for board %s are %s, chosen downloaded mode is %s" \ - % (build_board, mixed_supported_download_modes, build_download_mode)) - -if not board.get("build.ldscript", ""): - build_soc_variant = build_soc - if build_board == "gd32vf103c_longan_nano": - if build_variant == "lite": - build_soc_variant = "gd32vf103x8" - else: - build_soc_variant = "gd32vf103xb" - - ld_script = "gcc_%s_%s.ld" % ( - build_soc_variant, build_download_mode) if build_download_mode else "gcc_%s.ld" % build_soc - build_ldscript = join( - FRAMEWORK_DIR, "SoC", build_soc, "Board", build_board, "Source", "GCC", ld_script) - env.Replace(LDSCRIPT_PATH=build_ldscript) -else: - print("Use user defined ldscript %s" % board.get("build.ldscript")) - -# Use correct downloaded modes -DOWNLOAD_MODE = "DOWNLOAD_MODE_%s" % build_download_mode.upper() - -if selected_rtos: - RTOS_MACRO = ("RTOS_%s" % selected_rtos.upper()) -else: - RTOS_MACRO = ("NO_RTOS_SERVICE") - -default_arch_abi = ("rv32imac", "ilp32") - -if not build_mabi and not build_march and build_core in core_arch_abis: - build_march, build_mabi = core_arch_abis[build_core] -else: - if not build_mabi or not build_march: - build_march, build_mabi = default_arch_abi - print("No mabi and march specified in board json file, use default -march=%s -mabi=%s!" % (build_march, build_mabi)) - -if build_rtthread_msh == "1": # RT-Thread MSH compoment selected - rtt_srcfilter = "+<*>" -else: - rtt_srcfilter = "+<*> -" +build_march, build_mabi, build_mtune, build_mcmodel = find_arch_abi_tune_cmodel(build_core, build_march, build_mabi, build_mtune, build_mcmodel, core_arch_abis) env.SConscript("_bare.py", exports="env") +print("Use ldscript %s" % build_ldscript) +env.Replace(LDSCRIPT_PATH=build_ldscript) target_map = join("$BUILD_DIR", "${PROGNAME}.map") -env.Append( - CCFLAGS=[ - "-march=%s" % build_march, - "-mabi=%s" % build_mabi, - "-mcmodel=%s" % build_mcmodel - ], - - ASFLAGS=[ - "-march=%s" % build_march, - "-mabi=%s" % build_mabi, - "-mcmodel=%s" % build_mcmodel - ], - - LINKFLAGS=[ - "-march=%s" % build_march, - "-mabi=%s" % build_mabi, - "-mcmodel=%s" % build_mcmodel, +build_arch_flags = get_arch_flags(build_march, build_mabi, build_mtune, build_mcmodel, build_arch_ext, build_toolchain) + +if not build_nmsis_lib_arch: + build_nmsis_lib_arch = "%s%s" % (build_march, build_arch_ext) + +build_common_flags = build_arch_flags +build_asmflags = [] +build_cflags = [] +build_cxxflags = [] +build_ldflags = [ "-Wl,-Map,%s" % target_map, "-nostartfiles", - "--specs=nano.specs", - "--specs=nosys.specs", + "-nodefaultlibs", "-u", "_isatty", "-u", "_write", "-u", "_sbrk", "-u", "_read", "-u", "_close", "-u", "_fstat", - "-u", "_lseek" - ], - - CPPDEFINES=[ - ("DOWNLOAD_MODE", DOWNLOAD_MODE), - RTOS_MACRO - ], - - CPPPATH=[ - "$PROJECT_SRC_DIR", - "$PROJECT_INCLUDE_DIR", - join(FRAMEWORK_DIR, "NMSIS", "Include"), - join(FRAMEWORK_DIR, "NMSIS", "Core", "Include"), - join(FRAMEWORK_DIR, "NMSIS", "DSP", "Include"), - join(FRAMEWORK_DIR, "NMSIS", "NN", "Include"), - join(FRAMEWORK_DIR, "SoC", build_soc, "Common", "Include"), - join(FRAMEWORK_DIR, "SoC", build_soc, "Board", build_board, "Include"), - ], - - LIBPATH=[ - join(FRAMEWORK_DIR, "NMSIS", "Library", "DSP", "GCC"), - join(FRAMEWORK_DIR, "NMSIS", "Library", "NN", "GCC") - ], - - LIBS=["gcc", "m", "stdc++"] -) + "-u", "_lseek", + "-u", "errno"] + +build_cppdefines = [] +build_cpppaths = [ + "$PROJECT_SRC_DIR", "$PROJECT_INCLUDE_DIR", join(build_nsdk_dir, "NMSIS", "Core", "Include"), + join(build_nsdk_socdir, "Common", "Include"), + join(build_nsdk_socdir, "Board", build_board, "Include")] +build_libpaths = [] +build_libs = [] + +stubname = "newlib" +# process stdclib +if build_stdclib.startswith("libncrt"): + stubname = "libncrt" + ncrtlib = build_stdclib.replace("lib", "") + build_libs = [ncrtlib, "fileops_%s" % (build_ncrtio), "heapops_basic"] + build_common_flags.extend(["-isystem", "/include/libncrt"]) +else: + build_common_flags.extend(["-isystem", "/include/newlib-nano"]) + if build_stdclib == "newlib_full": + build_libs.extend(["c", "gcc", "m", "stdc++"]) + else: + build_libs.extend(["c_nano", "gcc", "m", "stdc++"]) + if build_stdclib == "newlib_fast": + build_ldflags.extend(["-u", "_printf_float", "-u", "_scanf_float"]) + elif build_stdclib == "newlib_small": + build_ldflags.extend(["-u", "_printf_float"]) + if build_toolchain == "nuclei_llvm": + build_ldflags.extend(["-u", "_printf_float", "-u", "__on_exit_args"]) + +if build_toolchain == "nuclei_gnu": + build_ldflags.append("-Wl,--no-warn-rwx-segments") + if "zc" in build_arch_ext: + build_common_flags.extend(["-fomit-frame-pointer", "-fno-shrink-wrap-separate"]) + +if build_download: + build_cppdefines.extend([("DOWNLOAD_MODE", "DOWNLOAD_MODE_%s" % (build_download.upper())), + ("DOWNLOAD_MODE_STRING", "\\\"%s\\\"" % build_download), + "VECTOR_TABLE_REMAPPED" if build_download == "flash" else "VECTOR_TABLE_NOT_REMAPPED"]) + +if selected_rtos: + build_cppdefines.extend(["RTOS_%s" % selected_rtos.upper()]) + +if build_nmsis_lib: + sel_nmsis_libs = build_nmsis_lib.split() + print(sel_nmsis_libs) + for lib in ["dsp", "nn"]: + libname = "nmsis_%s" % (lib) + if libname in sel_nmsis_libs: + build_libs.extend(["%s_%s" % (libname, build_nmsis_lib_arch)]) + build_libpaths.extend([join(build_nsdk_dir, "NMSIS", "Library", lib.upper(), "GCC")]) + build_cpppaths.extend([join(build_nsdk_dir, "NMSIS", lib.upper(), "Include")]) + if lib == "dsp": + build_cpppaths.extend([join(build_nsdk_dir, "NMSIS", lib.upper(), "PrivateInclude")]) + +if build_soc == "gd32vf103" and build_usb_driver != "": + build_cpppaths.extend([join(build_nsdk_socdir, "Common", "Include", "Usb")]) + +if build_simu: + build_cppdefines.extend([("SIMULATION_MODE", "SIMULATION_MODE_%s" % (build_simu.upper()))]) + +if build_heapsz: + build_ldflags.extend(["-Wl,--defsym=__HEAP_SIZE=%s" % (build_heapsz)]) + +if build_stacksz: + build_ldflags.extend(["-Wl,--defsym=__STACK_SIZE=%s" % (build_stacksz)]) + +if build_smp: + build_cppdefines.extend([("SMP_CPU_CNT", build_smp)]) + build_ldflags.extend(["-Wl,--defsym=__SMP_CPU_CNT=%s" % (build_smp)]) + +if build_boot_hartid: + build_cppdefines.extend([("BOOT_HARTID", build_boot_hartid)]) + +if build_hartid_ofs: + build_cppdefines.extend([("__HARTID_OFFSET", build_hartid_ofs)]) + +if build_sysclk: + build_cppdefines.extend([("SYSTEM_CLOCK", build_sysclk)]) + +if build_clksrc: + build_cppdefines.extend(["SYSCLK_USING_%s" % (build_clksrc.upper())]) + +if build_hxtal_value: + build_cppdefines.extend([("HXTAL_VALUE", build_hxtal_value)]) + +# NOTE: Search linker script include directory since nuclei sdk 0.6.0 +build_ldflags.extend(["-L", "%s" % (os.path.dirname(build_ldscript))]) # WORKAROUND: If RT-Thread used, force it to include symbols from finsh # otherwise it will not be included -if build_rtthread_msh == "1": - env.Append(LINKFLAGS=["-u", "finsh_system_init"]) - -extra_incdirs = get_extra_soc_board_incdirs(build_soc, build_board) -if extra_incdirs: - env.Append( - CPPPATH=extra_incdirs +if build_rtthread_msh == "1": # RT-Thread MSH compoment selected + build_ldflags.extend(["-u", "finsh_system_init"]) + rtt_srcfilter = "+<*> -<**/iar/>" +else: + rtt_srcfilter = "+<*> -<**/iar/> -" + +if build_toolchain == "nuclei_llvm": + build_ldflags.extend(["-fuse-ld=lld"]) + env.Replace( + AR="llvm-ar", + AS="riscv64-unknown-elf-clang", + CC="riscv64-unknown-elf-clang", + CXX="riscv64-unknown-elf-clang++", + RANLIB="llvm-ranlib" ) -if not is_valid_soc(build_soc): - sys.stderr.write("Could not find BSP package for SoC %s" % build_soc) - env.Exit(1) +# Append generic options +env.Append( + ASFLAGS = build_common_flags + build_asmflags, + CFLAGS = build_common_flags + build_cflags, + CXXFLAGS = build_common_flags + build_cxxflags, + LINKFLAGS = build_common_flags + build_ldflags, + CPPDEFINES = build_cppdefines, + CPPPATH = build_cpppaths, + LIBPATH = build_libpaths, + LIBS = build_libs + ) # # Target: Build Nuclei SDK Libraries # soclibname = "soc_" + build_soc boardlibname = "board_" + build_board + libs = [ env.BuildLibrary( join("$BUILD_DIR", "SoC", build_soc, soclibname), - join(FRAMEWORK_DIR, "SoC", build_soc, "Common") + join(build_nsdk_socdir, "Common"), + src_filter="+<*> -<**/IAR/> -<**/Stubs/> -<**/Usb/> +<**/%s/>" % (stubname) ), - env.BuildLibrary( join("$BUILD_DIR", "SoC", build_soc, "Board", boardlibname), - join(FRAMEWORK_DIR, "SoC", build_soc, "Board", build_board) + join(build_nsdk_socdir, "Board", build_board), + src_filter="+<*> -<**/IAR/>" ) ] if selected_rtos == "FreeRTOS": libs.append(env.BuildLibrary( join("$BUILD_DIR", "RTOS", "FreeRTOS"), - join(FRAMEWORK_DIR, "OS", "FreeRTOS", "Source"), - src_filter="+<*> - +" + join(build_nsdk_dir, "OS", "FreeRTOS", "Source"), + src_filter="+<*> - - +" )) env.Append( - CPPPATH=[ - join(FRAMEWORK_DIR, "OS", "FreeRTOS", "Source", "include"), - join(FRAMEWORK_DIR, "OS", "FreeRTOS", "Source", "portable", "GCC") + CPPPATH = [ + join(build_nsdk_dir, "OS", "FreeRTOS", "Source", "include"), + join(build_nsdk_dir, "OS", "FreeRTOS", "Source", "portable") ] ) elif selected_rtos == "UCOSII": libs.append(env.BuildLibrary( join("$BUILD_DIR", "RTOS", "UCOSII"), - join(FRAMEWORK_DIR, "OS", "UCOSII") + join(build_nsdk_dir, "OS", "UCOSII"), + src_filter="+<*> -" )) env.Append( - CPPPATH=[ - join(FRAMEWORK_DIR, "OS", "UCOSII", "arch"), - join(FRAMEWORK_DIR, "OS", "UCOSII", "cfg"), - join(FRAMEWORK_DIR, "OS", "UCOSII", "source") + CPPPATH = [ + join(build_nsdk_dir, "OS", "UCOSII", "arch"), + join(build_nsdk_dir, "OS", "UCOSII", "cfg"), + join(build_nsdk_dir, "OS", "UCOSII", "source") ] ) elif selected_rtos == "RTThread": libs.append(env.BuildLibrary( join("$BUILD_DIR", "RTOS", "RTThread"), - join(FRAMEWORK_DIR, "OS", "RTThread"), + join(build_nsdk_dir, "OS", "RTThread"), src_filter=rtt_srcfilter )) env.Append( - CPPPATH=[ - join(FRAMEWORK_DIR, "OS", "RTThread", "libcpu", "risc-v", "nuclei"), - join(FRAMEWORK_DIR, "OS", "RTThread", "include"), - join(FRAMEWORK_DIR, "OS", "RTThread", "include", "libc"), - join(FRAMEWORK_DIR, "OS", "RTThread", "components", "finsh") + CPPPATH = [ + join(build_nsdk_dir, "OS", "RTThread", "libcpu", "risc-v", "nuclei"), + join(build_nsdk_dir, "OS", "RTThread", "include"), + join(build_nsdk_dir, "OS", "RTThread", "include", "libc") + ] + ) + if build_rtthread_msh == "1": + env.Append( + CPPPATH = [ + join(build_nsdk_dir, "OS", "RTThread", "components", "finsh") + ] + ) +elif selected_rtos == "ThreadX": + libs.append(env.BuildLibrary( + join("$BUILD_DIR", "RTOS", "ThreadX"), + join(build_nsdk_dir, "OS", "ThreadX"), + src_filter="+<*> -<**/iar/>" + )) + env.Append( + CPPPATH = [ + join(build_nsdk_dir, "OS", "ThreadX", "common", "inc"), + join(build_nsdk_dir, "OS", "ThreadX", "ports", "nuclei") ] ) +# process usb library +if build_soc == "gd32vf103" and build_usb_driver != "": + usb_srcfilter = "+<*>" + if build_usb_driver == "device": + usb_srcfilter = "+<*> -<*usbh_*.c> -" + elif build_usb_driver == "host": + usb_srcfilter = "+<*> -<*usbd_*.c> -" + else: + usb_srcfilter = "+<*>" + + libs.append(env.BuildLibrary( + join("$BUILD_DIR", "SoC", build_soc, "%s_usb" %(soclibname)), + join(build_nsdk_socdir, "Common", "Source", "Drivers", "Usb"), + src_filter=usb_srcfilter + )) + env.Prepend(LIBS=libs) diff --git a/builder/main.py b/builder/main.py index 852d2ac..cc62f35 100644 --- a/builder/main.py +++ b/builder/main.py @@ -25,16 +25,17 @@ env = DefaultEnvironment() platform = env.PioPlatform() board_config = env.BoardConfig() +build_board = board_config.id env.Replace( - AR="riscv-nuclei-elf-gcc-ar", - AS="riscv-nuclei-elf-as", - CC="riscv-nuclei-elf-gcc", - GDB="riscv-nuclei-elf-gdb", - CXX="riscv-nuclei-elf-g++", - OBJCOPY="riscv-nuclei-elf-objcopy", - RANLIB="riscv-nuclei-elf-gcc-ranlib", - SIZETOOL="riscv-nuclei-elf-size", + AR="riscv64-unknown-elf-gcc-ar", + AS="riscv64-unknown-elf-as", + CC="riscv64-unknown-elf-gcc", + GDB="riscv64-unknown-elf-gdb", + CXX="riscv64-unknown-elf-g++", + OBJCOPY="riscv64-unknown-elf-objcopy", + RANLIB="riscv64-unknown-elf-gcc-ranlib", + SIZETOOL="riscv64-unknown-elf-size", ARFLAGS=["rc"], @@ -148,7 +149,7 @@ def _jlink_cmd_script(env, source): ] openocd_args.extend( debug_tools.get(upload_protocol).get("server").get("arguments", [])) - if download_mode in ("ilm", "ddr"): + if download_mode in ("ilm", "ddr", "sram", "sramxip"): startplace = download_mode + "_start" openocd_args.extend([ "-c", "reset halt; load_image {$SOURCE}; resume %s; shutdown;" % @@ -156,11 +157,15 @@ def _jlink_cmd_script(env, source): ]) else: openocd_args.extend([ - "-c", "reset halt; flash protect 0 0 last off;", - "-c", "program {$SOURCE} verify; reset; shutdown;" + "-c", "reset halt; ", + "-c", "program {$SOURCE} verify; reset halt; resume; shutdown;" ]) + # TODO You must use Nuclei OpenOCD >= 2024.06 + openocd_dir = platform.get_package_dir("tool-openocd-nuclei") + openocd_exe = join(openocd_dir, "bin", "openocd") + env.Replace( - UPLOADER="openocd", + UPLOADER=openocd_exe, UPLOADERFLAGS=openocd_args, UPLOADCMD="$UPLOADER $UPLOADERFLAGS") upload_actions = [env.VerboseAction("$UPLOADCMD", "Uploading $SOURCE")] @@ -170,7 +175,7 @@ def _jlink_cmd_script(env, source): upload_actions = [env.VerboseAction("$UPLOADCMD", "Uploading $SOURCE")] else: - sys.stderr.write("Warning! Unknown upload protocol %s\n" % upload_protocol) + print("Warning! Unknown upload protocol %s\n" % upload_protocol) AlwaysBuild(env.Alias("upload", upload_target, upload_actions)) diff --git a/examples/coremark/README.md b/examples/coremark/README.md index 1dd7b5b..07db7a6 100644 --- a/examples/coremark/README.md +++ b/examples/coremark/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/coremark/platformio.ini b/examples/coremark/platformio.ini index 9b4374e..bbc929f 100644 --- a/examples/coremark/platformio.ini +++ b/examples/coremark/platformio.ini @@ -1,51 +1,92 @@ ; PlatformIO Project Configuration File ; -; Build options: build flags, source filter, extra scripting -; Upload options: custom port, speed and extra flags +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags ; Library options: dependencies, extra library storages +; Advanced options: extra scripting ; ; Please visit documentation for the other options and examples -; http://docs.platformio.org/page/projectconf.html +; https://docs.platformio.org/page/projectconf.html [platformio] -description = - CoreMark benchmark. +description = + CoreMark benchmark. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [common] -compile_flags = -O2 -funroll-all-loops -finline-limit=600 - -ftree-dominator-opts -fno-if-conversion2 - -fselective-scheduling -fno-code-hoisting - -fno-common -funroll-loops -finline-functions - -falign-functions=4 -falign-jumps=4 -falign-loops=4 - -DPERFORMANCE_RUN=1 - -Wl,-u,_printf_float +300_flags = -Ofast -fno-code-hoisting -fno-tree-vectorize -fno-common -finline-functions -falign-functions=4 + -falign-jumps=4 -falign-loops=4 -finline-limit=200 -fno-if-conversion -fno-if-conversion2 -fipa-pta + -fselective-scheduling -fno-tree-loop-distribute-patterns -funroll-loops -funroll-all-loops + -fno-delete-null-pointer-checks -fno-rename-registers -mbranch-cost=1 --param fsm-scale-path-stmts=5 + --param max-average-unrolled-insns=200 --param max-grow-copy-bb-insns=20 --param max-jump-thread-duplication-stmts=25 + --param hot-bb-frequency-fraction=4 --param unroll-jam-min-percent=0 + -DPERFORMANCE_RUN=1 +900_flags = -Ofast -mbranch-cost=1 -mstrict-align -funroll-all-loops -finline-limit=500 + -ftree-dominator-opts -fselective-scheduling -funroll-loops -finline-functions -falign-functions=4 + -falign-jumps=4 -falign-loops=4 -fipa-pta -fno-code-hoisting -fno-common -fno-if-conversion + -fno-if-conversion2 -fno-tree-loop-distribute-patterns -fno-tree-vectorize -fno-tree-loop-ivcanon + -ftree-vrp -fgcse-las --param=max-loop-header-insns=4 --param loop-max-datarefs-for-datadeps=0 + --param=unroll-jam-min-percent=0 --param=max-goto-duplication-insns=0 + --param max-jump-thread-duplication-stmts=19 --param fsm-scale-path-stmts=3 --param max-grow-copy-bb-insns=12 + -DPERFORMANCE_RUN=1 +200_flags = -Ofast -fno-code-hoisting -fno-tree-vectorize -fno-common -finline-functions -falign-functions=4 + -falign-jumps=4 -falign-loops=4 -finline-limit=200 -fno-if-conversion -fno-if-conversion2 -fipa-pta + -fselective-scheduling -fno-tree-loop-distribute-patterns -funroll-loops -funroll-all-loops + -fno-delete-null-pointer-checks -fno-rename-registers -mbranch-cost=1 --param fsm-scale-path-stmts=3 + --param max-average-unrolled-insns=200 --param max-grow-copy-bb-insns=20 --param max-jump-thread-duplication-stmts=25 + --param hot-bb-frequency-fraction=4 --param unroll-jam-min-percent=0 + -DPERFORMANCE_RUN=1 +600_flags = -Ofast -fno-code-hoisting -fno-tree-vectorize -fno-common -finline-functions + -falign-functions=4 -falign-jumps=4 -falign-loops=4 -finline-limit=200 -fno-if-conversion + -fno-if-conversion2 -fipa-pta -fselective-scheduling -fno-tree-loop-distribute-patterns + -funroll-loops -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers + -mbranch-cost=1 --param fsm-scale-path-stmts=5 --param max-average-unrolled-insns=200 + --param max-grow-copy-bb-insns=16 --param max-jump-thread-duplication-stmts=14 + --param hot-bb-frequency-fraction=4 --param unroll-jam-min-percent=0 + -DPERFORMANCE_RUN=1 [env] platform = nuclei framework = nuclei-sdk monitor_speed = 115200 build_unflags = -Os -build_flags = ${common.compile_flags} +build_flags = ${common.300_flags} -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval -# Changed to use ilm download mode board_build.download = ilm -build_flags = ${common.compile_flags} -DITERATIONS=500 +build_flags = ${common.300_flags} -DITERATIONS=500 -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +board_build.download = sram +# you can uncomment below variable and set proper sysclk +#board_build.sysclk = 48000000 +#board_build.clksrc = hxtal +board_build.stdclib = newlib_small +build_flags = ${common.300_flags} -DITERATIONS=4000 + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar -build_flags = ${common.compile_flags} -DITERATIONS=5000 +board_build.sysclk = 96000000 +board_build.clksrc = hxtal +board_build.stdclib = libncrt_small +build_flags = ${common.200_flags} -DITERATIONS=4000 -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -build_flags = ${common.compile_flags} -DITERATIONS=5000 +board_build.sysclk = 108000000 +board_build.clksrc = hxtal +build_flags = ${common.200_flags} -DITERATIONS=4000 -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -build_flags = ${common.compile_flags} -DITERATIONS=5000 +board_build.sysclk = 72000000 +board_build.clksrc = irc8m +build_flags = ${common.200_flags} -DITERATIONS=4000 -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite -build_flags = ${common.compile_flags} -DITERATIONS=5000 \ No newline at end of file +build_flags = ${common.200_flags} -DITERATIONS=4000 \ No newline at end of file diff --git a/examples/coremark/src/core_main.c b/examples/coremark/src/core_main.c index 1bea456..22611ca 100644 --- a/examples/coremark/src/core_main.c +++ b/examples/coremark/src/core_main.c @@ -21,6 +21,21 @@ El Dorado Hills, CA, 95762 */ #include "coremark.h" +/* Only support dec number < 1000 */ +static char *dec2str(uint32_t val) +{ + static char str[4]; + val = val % 1000; + int decnum = 100; + for (int i = 0; i < 3; i ++) { + str[i] = (val / decnum) + '0'; + val = val % decnum; + decnum = decnum / 10; + } + str[3] = '\0'; + return str; +} + /* Function: iterate Run the benchmark for a specified number of iterations. @@ -101,7 +116,7 @@ MAIN_RETURN_TYPE main(int argc, char* argv[]) ee_u16 i, j = 0, num_algorithms = 0; ee_s16 known_id = -1, total_errors = 0; ee_u16 seedcrc = 0; - CORE_TICKS total_time; + CORE_TICKS total_time, total_instret; core_results results[MULTITHREAD]; #if (MEM_METHOD==MEM_STACK) ee_u8 stack_memblock[TOTAL_DATA_SIZE * MULTITHREAD]; @@ -120,14 +135,14 @@ MAIN_RETURN_TYPE main(int argc, char* argv[]) #if CORE_DEBUG results[0].iterations = 1; #endif - // Bob: change the interation times to make it faster #ifdef CFG_SIMULATION - results[0].iterations = 2; // For simulation we make it small + // 2024.1.3: 6 iterations are enough for rtl simulation + results[0].iterations = 6; #else results[0].iterations = ITERATIONS; #endif - ee_printf("Start to run coremark for %d iterations\r\n", results[0].iterations); + ee_printf("Start to run coremark for %u iterations\r\n", (unsigned int)results[0].iterations); results[0].execs = get_seed_32(5); if (results[0].execs == 0) { /* if not supplied, execute all algorithms */ @@ -233,6 +248,7 @@ MAIN_RETURN_TYPE main(int argc, char* argv[]) } /* perform actual benchmark */ start_time(); + start_instret(); #if (MULTITHREAD>1) if (default_num_contexts > MULTITHREAD) { default_num_contexts = MULTITHREAD; @@ -249,7 +265,9 @@ MAIN_RETURN_TYPE main(int argc, char* argv[]) iterate(&results[0]); #endif stop_time(); + stop_instret(); total_time = get_time(); + total_instret = get_instret(); /* get a function of the input to report */ seedcrc = crc16(results[0].seed1, seedcrc); seedcrc = crc16(results[0].seed2, seedcrc); @@ -304,8 +322,8 @@ MAIN_RETURN_TYPE main(int argc, char* argv[]) } total_errors += check_data_types(); /* and report results */ - ee_printf("CoreMark Size : %lu\n", (ee_u32)results[0].size); - ee_printf("Total ticks : %lu\n", (ee_u32)total_time); + ee_printf("CoreMark Size : %u\n", (unsigned int)results[0].size); + ee_printf("Total ticks : %u\n", (unsigned int)total_time); #if HAS_FLOAT ee_printf("Total time (secs): %f\n", time_in_secs(total_time)); if (time_in_secs(total_time) > 0) { @@ -326,7 +344,7 @@ MAIN_RETURN_TYPE main(int argc, char* argv[]) } #endif - ee_printf("Iterations : %lu\n", (ee_u32)default_num_contexts * results[0].iterations); + ee_printf("Iterations : %u\n", (unsigned int)(default_num_contexts * results[0].iterations)); ee_printf("Compiler version : %s\n", COMPILER_VERSION); ee_printf("Compiler flags : %s\n", COMPILER_FLAGS); #if (MULTITHREAD>1) @@ -385,20 +403,35 @@ MAIN_RETURN_TYPE main(int argc, char* argv[]) float coremark_dmips = ((uint64_t)results[0].iterations * 1000000) / (float)total_time; + if ((total_time >> 32) & 0xFFFFFFFF) { + printf("WARNING: Total ticks higher 32bit has value, please take care, higher 32bit 0x%x, lower 32bit 0x%x\n", \ + (unsigned int)(total_time >> 32), (unsigned int)total_time); + } + #if HAS_FLOAT ee_printf("\n"); ee_printf("\n"); ee_printf("Print Personal Added Addtional Info to Easy Visual Analysis\n"); ee_printf("\n"); - ee_printf(" (Iterations is: %u\n", results[0].iterations); - ee_printf(" (total_ticks is: %u\n", (ee_u32)total_time); + ee_printf(" (Iterations is: %u\n", (unsigned int)results[0].iterations); + ee_printf(" (total_ticks is: %u\n", (unsigned int)total_time); ee_printf(" (*) Assume the core running at 1 MHz\n"); - ee_printf(" So the CoreMark/MHz can be caculated by: \n"); + ee_printf(" So the CoreMark/MHz can be calculated by: \n"); ee_printf(" (Iterations*1000000/total_ticks) = %2.6f CoreMark/MHz\n", coremark_dmips); ee_printf("\n"); #endif - return MAIN_RETURN_VAL; -} + uint32_t cmk_dmips = (uint32_t)(coremark_dmips * 1000); + char *pstr = dec2str(cmk_dmips); + ee_printf("\nCSV, Benchmark, Iterations, Cycles, CoreMark/MHz\n"); + ee_printf("CSV, CoreMark, %u, %u, %u.%s\n", \ + (unsigned int)results[0].iterations, (unsigned int)total_time, (unsigned int)(cmk_dmips/1000), pstr); + + float f_ipc = (((float)total_instret / total_time)); + uint32_t i_ipc = (uint32_t)(f_ipc * 1000); + pstr = dec2str(i_ipc); + ee_printf("IPC = Instret/Cycle = %u/%u = %u.%s\n", (unsigned int)total_instret, (unsigned int)total_time, (unsigned int)(i_ipc/1000), pstr); + return MAIN_RETURN_VAL; +} diff --git a/examples/coremark/src/core_matrix.c b/examples/coremark/src/core_matrix.c index 1230fb5..9afee57 100644 --- a/examples/coremark/src/core_matrix.c +++ b/examples/coremark/src/core_matrix.c @@ -17,6 +17,7 @@ EEMBC El Dorado Hills, CA, 95762 */ #include "coremark.h" + /* Topic: Description Matrix manipulation benchmark @@ -44,7 +45,15 @@ void matrix_add_const(ee_u32 N, MATDAT* A, MATDAT val); #define matrix_test_next(x) (x+1) #define matrix_clip(x,y) ((y) ? (x) & 0x0ff : (x) & 0x0ffff) #define matrix_big(x) (0xf000 | (x)) -#define bit_extract(x,from,to) (((x)>>(from)) & (~(0xffffffff << (to)))) + +// TODO: clang not yet provide any xxlcz instruction support +#if (defined(__riscv_xxlczbitop) || (defined(__riscv_xxlcz))) && !defined(__clang__) && !defined(NO_EXTRACTU) +#include "riscv_nuclei_xlcz.h" +#define BIT_EXTRACT(x, from, to) (__xl_extractu(x, from, to)) +#else +#define BIT_EXTRACT(x, from, to) (((x)>>(from)) & (~(0xffffffff << (to)))) +#endif + #if CORE_DEBUG void printmat(MATDAT* A, ee_u32 N, char* name) @@ -313,7 +322,7 @@ void matrix_mul_matrix_bitextract(ee_u32 N, MATRES* C, MATDAT* A, MATDAT* B) C[i * N + j] = 0; for (k = 0; k < N; k++) { MATRES tmp = (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; - C[i * N + j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5, 7); + C[i * N + j] += BIT_EXTRACT(tmp, 2, 4) * BIT_EXTRACT(tmp, 5, 7); } } } diff --git a/examples/coremark/src/core_portme.c b/examples/coremark/src/core_portme.c index 940dde2..2a46a41 100644 --- a/examples/coremark/src/core_portme.c +++ b/examples/coremark/src/core_portme.c @@ -24,9 +24,11 @@ volatile ee_s32 seed4_volatile = ITERATIONS; volatile ee_s32 seed5_volatile = 0; static CORE_TICKS t0, t1; +static CORE_TICKS i0, i1; void start_time(void) { + __set_rv_cycle(0); t0 = __get_rv_cycle(); } @@ -40,6 +42,22 @@ CORE_TICKS get_time(void) return t1 - t0; } +void start_instret(void) +{ + __set_rv_instret(0); + i0 = __get_rv_instret(); +} + +void stop_instret(void) +{ + i1 = __get_rv_instret(); +} + +CORE_TICKS get_instret(void) +{ + return i1 - i0; +} + secs_ret time_in_secs(CORE_TICKS ticks) { // scale timer down to avoid uint64_t -> double conversion in RV32 diff --git a/examples/coremark/src/core_portme.h b/examples/coremark/src/core_portme.h index fdfebf9..bd4054b 100644 --- a/examples/coremark/src/core_portme.h +++ b/examples/coremark/src/core_portme.h @@ -2,11 +2,10 @@ #define CORE_PORTME_H #include "nuclei_sdk_soc.h" -//Bob: put some macro here such that the IDE SDK do not need to specify the macro specially -//#define FLAGS_STR "-O3 -fno-common -funroll-loops -finline-functions -falign-functions=4 -falign-jumps=4 -falign-loops=4 -funswitch-loops -fpeel-loops -fgcse-sm -fgcse-las" -//#define FLAGS_STR "-O2 -fno-common -funroll-loops -finline-functions -falign-functions=4 -falign-jumps=4 -falign-loops=4" + + #ifndef FLAGS_STR -#define FLAGS_STR "-O2 -funroll-all-loops -finline-limit=600 -ftree-dominator-opts -fno-if-conversion2 -fselective-scheduling -fno-code-hoisting -fno-common -funroll-loops -finline-functions -falign-functions=4 -falign-jumps=4 -falign-loops=4" +#define FLAGS_STR "Please check your compiler options!" #endif #ifndef PERFORMANCE_RUN @@ -52,8 +51,10 @@ #ifdef __GNUC__ # define COMPILER_VERSION "GCC"__VERSION__ +#elif defined(__ICCRISCV__) +# define COMPILER_VERSION "IAR "__VERSION__ #else -# error +# define COMPILER_VERSION "Unknown Compiler" #endif #define MEM_METHOD MEM_STACK diff --git a/examples/coremark/src/core_util.c b/examples/coremark/src/core_util.c index 6727672..a65b577 100644 --- a/examples/coremark/src/core_util.c +++ b/examples/coremark/src/core_util.c @@ -170,22 +170,41 @@ ee_u16 crcu8(ee_u8 data, ee_u16 crc) } return crc; } + +#if (defined(__riscv_zicond) && !defined(__clang__)) +#pragma GCC push_options +#pragma GCC optimize("-fcode-hoisting") +#pragma GCC optimize("-ftree-vrp") +#endif ee_u16 crcu16(ee_u16 newval, ee_u16 crc) { crc = crcu8((ee_u8)(newval), crc); crc = crcu8((ee_u8)((newval) >> 8), crc); return crc; } +#if (defined(__riscv_zicond) && !defined(__clang__)) +#pragma GCC pop_options +#endif + ee_u16 crcu32(ee_u32 newval, ee_u16 crc) { crc = crc16((ee_s16) newval, crc); crc = crc16((ee_s16)(newval >> 16), crc); return crc; } + +#if (defined(__riscv_zicond) && !defined(__clang__)) +#pragma GCC push_options +#pragma GCC optimize("-fcode-hoisting") +#pragma GCC optimize("-ftree-vrp") +#endif ee_u16 crc16(ee_s16 newval, ee_u16 crc) { return crcu16((ee_u16)newval, crc); } +#if (defined(__riscv_zicond) && !defined(__clang__)) +#pragma GCC pop_options +#endif ee_u8 check_data_types() { diff --git a/examples/coremark/src/coremark.h b/examples/coremark/src/coremark.h index e8872f7..e47880c 100644 --- a/examples/coremark/src/coremark.h +++ b/examples/coremark/src/coremark.h @@ -71,6 +71,9 @@ typedef ee_u32 secs_ret; void start_time(void); void stop_time(void); CORE_TICKS get_time(void); +void start_instret(void); +void stop_instret(void); +CORE_TICKS get_instret(void); secs_ret time_in_secs(CORE_TICKS ticks); /* Misc useful functions */ diff --git a/examples/cpuinfo/.gitignore b/examples/cpuinfo/.gitignore new file mode 100644 index 0000000..03f4a3c --- /dev/null +++ b/examples/cpuinfo/.gitignore @@ -0,0 +1 @@ +.pio diff --git a/examples/cpuinfo/README.md b/examples/cpuinfo/README.md new file mode 100644 index 0000000..1f8b920 --- /dev/null +++ b/examples/cpuinfo/README.md @@ -0,0 +1,27 @@ +How to build PlatformIO based project +===================================== + +1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +2. Download [development platform with examples](https://github.com/Nuclei-Software/platform-nuclei/archive/develop.zip) +3. Extract ZIP archive +4. Run these commands: + +```shell +# Change directory to example +$ cd platform-nuclei/examples/cpuinfo + +# Build project +$ pio run + +# Upload firmware +$ pio run --target upload + +# Build specific environment +$ pio run -e gd32vf103v_rvstar + +# Upload firmware for the specific environment +$ pio run -e gd32vf103v_rvstar --target upload + +# Clean build files +$ pio run --target clean +``` diff --git a/examples/cpuinfo/include/README b/examples/cpuinfo/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/examples/cpuinfo/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/cpuinfo/lib/README b/examples/cpuinfo/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/examples/cpuinfo/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/cpuinfo/platformio.ini b/examples/cpuinfo/platformio.ini new file mode 100644 index 0000000..7aadab8 --- /dev/null +++ b/examples/cpuinfo/platformio.ini @@ -0,0 +1,53 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter, extra scripting +; Upload options: custom port, speed and extra flags +; Library options: dependencies, extra library storages +; +; Please visit documentation for the other options and examples +; http://docs.platformio.org/page/projectconf.html + +[platformio] +description = + Probe and dump Nuclei RISC-V Processor Info +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval + +[env] +platform = nuclei +framework = nuclei-sdk +monitor_speed = 115200 + +[env:nuclei_fpga_eval] +board = nuclei_fpga_eval +board_build.download = flashxip +board_build.stdclib = libncrt_small + +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = flashxip +board_build.stdclib = libncrt_nano +board_build.clksrc = hxtal + +[env:gd32vf103v_rvstar] +board = gd32vf103v_rvstar +board_build.sysclk = 108000000 +board_build.clksrc = hxtal +board_build.stdclib = libncrt_small + +[env:gd32vf103v_eval] +board = gd32vf103v_eval +board_build.sysclk = 96000000 +board_build.clksrc = hxtal +board_build.stdclib = libncrt_fast + +[env:gd32vf103c_longan_nano] +board = gd32vf103c_longan_nano +board_build.sysclk = 96000000 +board_build.clksrc = hxtal +board_build.stdclib = libncrt_balanced + +[env:gd32vf103c_longan_nano_lite] +board = gd32vf103c_longan_nano +board_build.variant = lite \ No newline at end of file diff --git a/examples/cpuinfo/src/main.c b/examples/cpuinfo/src/main.c new file mode 100644 index 0000000..eacac05 --- /dev/null +++ b/examples/cpuinfo/src/main.c @@ -0,0 +1,342 @@ +#include +#include "nuclei_sdk_soc.h" + +#define KB (1024) +#define MB (KB * 1024) +#define GB (MB * 1024) +#define EXTENSION_NUM (26) +#define POWER_FOR_TWO(n) (1UL << (n)) +#define LINESZ(n) ((n) > 0 ? POWER_FOR_TWO((n)-1) : 0) + +void show_safety_mechanism(unsigned long safetyMode) +{ + switch (safetyMode) { + case 0b00: printf(" No-Safety-Mechanism"); break; + case 0b01: printf(" Lockstep"); break; + case 0b10: printf(" Lockstep+SplitMode"); break; + case 0b11: printf(" ASIL-B"); break; + default: return; + } +} + +void show_vpu_degree(unsigned long degree) +{ + switch (degree) { + case 0b00: printf(" DLEN=VLEN/2"); break; + case 0b01: printf(" DLEN=VLEN"); break; + default: return; + } +} + +void print_size(unsigned long bytes) +{ + if (bytes / GB) { + printf(" %ld GB", bytes / GB); + } else if (bytes / MB) { + printf(" %ld MB", bytes / MB); + } else if (bytes / KB) { + printf(" %ld KB", bytes / KB); + } else { + printf(" %ld Byte", bytes); + } +} + +void show_cache_info(unsigned long set, unsigned long way, unsigned long lsize, unsigned long ecc) +{ + print_size(set * way * lsize); + printf("(set=%ld,", set); + printf("way=%ld,", way); + printf("lsize=%ld,", lsize); + printf("ecc=%ld)\r\n", !!ecc); +} + +void nuclei_cpuinfo(void) +{ + CSR_MCFGINFO_Type mcfg; + CSR_MICFGINFO_Type micfg; + CSR_MDCFGINFO_Type mdcfg; + CSR_MTLBCFGINFO_Type mtlbcfg; + rv_csr_t iregion_base = 0; + rv_csr_t csr_marchid = 0; + rv_csr_t csr_mimpid = 0; + rv_csr_t csr_misa = 0; + rv_csr_t csr_mirgb = 0; + rv_csr_t csr_mfiocfg = 0; + rv_csr_t csr_mppicfg = 0; + + + // CFG_CPU_NAME/CFG_CPU_VERSION/CPU_ISA are macros defined in cpufeature.h auto generated by nuclei_gen + // nuclei_gen is our cpu ip generation tool +#ifdef CFG_CPU_NAME + printf("CPU NAME: %s\n", CFG_CPU_NAME); +#endif +#ifdef CFG_CPU_VERSION + printf("CPU VERSION: %s\n", CFG_CPU_VERSION); +#endif +#ifdef CPU_ISA + printf("CPU ISA: %s\n", CPU_ISA); +#endif + + printf("\r\n-----Nuclei RISC-V CPU Configuration Information-----\r\n"); + + /* ID and version */ + csr_marchid = __RV_CSR_READ(CSR_MARCHID); + csr_mimpid = __RV_CSR_READ(CSR_MIMPID); + printf(" MARCHID: 0x%lx\r\n", csr_marchid); + printf(" MIMPID: 0x%lx\r\n", csr_mimpid); + + /* ISA */ + csr_misa = __RV_CSR_READ(CSR_MISA); + printf(" ISA:"); +#if __RISCV_XLEN == 32 + printf(" RV32"); +#else + printf(" RV64"); +#endif + for (int i = 0; i < EXTENSION_NUM; i++) { + if (csr_misa & BIT(i)) { + if ('X' == ('A' + i)) { + printf(" NICE"); + } else { + printf(" %c", 'A' + i); + } + } + } + mcfg = (CSR_MCFGINFO_Type)__RV_CSR_READ(CSR_MCFG_INFO); + if (mcfg.b.dsp_n1) { + printf(" Xxldspn1x"); + } + if (mcfg.b.dsp_n2) { + printf(" Xxldspn2x"); + } + if (mcfg.b.dsp_n3) { + printf(" Xxldspn3x"); + } + if (mcfg.b.zc_xlcz) { + printf(" Zc Xxlcz"); + } + if (mcfg.b.sec_mode) { + printf(" Smwg"); + } + printf("\r\n"); + + /* Support */ + printf(" MCFG:"); + if (mcfg.b.tee) { + printf(" TEE"); + } + if (mcfg.b.ecc) { + printf(" ECC"); + } + if (mcfg.b.clic) { + printf(" ECLIC"); + } + if (mcfg.b.plic) { + printf(" PLIC"); + } + if (mcfg.b.fio) { + printf(" FIO"); + } + if (mcfg.b.ppi) { + printf(" PPI"); + } + if (mcfg.b.nice) { + printf(" NICE"); + } + if (mcfg.b.ilm) { + printf(" ILM"); + } + if (mcfg.b.dlm) { + printf(" DLM"); + } + if (mcfg.b.icache) { + printf(" ICACHE"); + } + if (mcfg.b.dcache) { + printf(" DCACHE"); + } + if (mcfg.b.smp) { + printf(" SMP"); + } + if (mcfg.b.dsp_n1) { + printf(" DSP_N1"); + } + if (mcfg.b.dsp_n2) { + printf(" DSP_N2"); + } + if (mcfg.b.dsp_n3) { + printf(" DSP_N3"); + } + if (mcfg.b.zc_xlcz) { + printf(" ZC_XLCZ_EXT"); + } + if (mcfg.b.iregion) { + printf(" IREGION"); + } + if (mcfg.b.sec_mode) { + printf(" SEC_MODE"); + } + if (mcfg.b.etrace) { + printf(" ETRACE"); + } + if (mcfg.b.vnice) { + printf(" VNICE"); + } + show_safety_mechanism(mcfg.b.safety_mecha); + show_vpu_degree(mcfg.b.vpu_degree); + printf("\r\n"); + + /* ILM */ + if (mcfg.b.ilm) { + micfg = (CSR_MICFGINFO_Type)__RV_CSR_READ(CSR_MICFG_INFO); + printf(" ILM:"); + print_size(POWER_FOR_TWO(micfg.b.lm_size - 1) * 256); + if (micfg.b.lm_xonly) { + printf(" execute-only"); + } + if (micfg.b.lm_ecc) { + printf(" has-ecc"); + } + printf("\r\n"); + } + + /* DLM */ + if (mcfg.b.dlm) { + mdcfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO); + printf(" DLM:"); + print_size(POWER_FOR_TWO(mdcfg.b.lm_size - 1) * 256); + if (mdcfg.b.lm_ecc) { + printf(" has-ecc"); + } + printf("\r\n"); + } + + /* ICACHE */ + if (mcfg.b.icache) { + micfg = (CSR_MICFGINFO_Type)__RV_CSR_READ(CSR_MICFG_INFO); + printf(" ICACHE:"); + show_cache_info(POWER_FOR_TWO(micfg.b.set + 3), micfg.b.way + 1, POWER_FOR_TWO(micfg.b.lsize + 2), mcfg.b.ecc); + } + + /* DCACHE */ + if (mcfg.b.dcache) { + mdcfg = (CSR_MDCFGINFO_Type)__RV_CSR_READ(CSR_MDCFG_INFO); + printf(" DCACHE:"); + show_cache_info(POWER_FOR_TWO(mdcfg.b.set + 3), mdcfg.b.way + 1, POWER_FOR_TWO(mdcfg.b.lsize + 2), mcfg.b.ecc); + } + + /* TLB only present with MMU, when PLIC present MMU will present */ + if (mcfg.b.plic) { + mtlbcfg = (CSR_MTLBCFGINFO_Type)__RV_CSR_READ(CSR_MTLBCFG_INFO); + printf(" TLB:"); + printf(" MainTLB(set=%lu,way=%lu,entry=%lu,ecc=%lu) ITLB(entry=%lu) DTLB(entry=%lu)\r\n", \ + POWER_FOR_TWO(mtlbcfg.b.set + 3), mtlbcfg.b.way + 1, LINESZ(mtlbcfg.b.lsize), \ + mtlbcfg.b.ecc, LINESZ(mtlbcfg.b.i_size), LINESZ(mtlbcfg.b.d_size)); + } + + + /* IREGION */ + if (mcfg.b.iregion) { + rv_csr_t csr_mirgb = __RV_CSR_READ(CSR_MIRGB_INFO); + printf(" IREGION:"); + iregion_base = csr_mirgb & (~0x3FF); + printf(" %#lx", iregion_base); + print_size(POWER_FOR_TWO(__RV_EXTRACT_FIELD(csr_mirgb, 0x1F << 1) - 1) * KB); + printf("\r\n"); + printf(" Unit Size Address\r\n"); + printf(" INFO 64KB %#lx\r\n", iregion_base + IREGION_IINFO_OFS); + printf(" DEBUG 64KB %#lx\r\n", iregion_base + IREGION_DEBUG_OFS); + if (mcfg.b.clic) { + printf(" ECLIC 64KB %#lx\r\n", iregion_base + IREGION_ECLIC_OFS); + } + printf(" TIMER 64KB %#lx\r\n", iregion_base + IREGION_TIMER_OFS); + if (mcfg.b.smp) { + printf(" SMP 64KB %#lx\r\n", iregion_base + IREGION_SMP_OFS); + } + rv_csr_t smp_cfg = *(rv_csr_t*)(iregion_base + 0x40004); + if (mcfg.b.clic && (__RV_EXTRACT_FIELD(smp_cfg, 0x1F << 1) >= 2)) { + printf(" CIDU 64KB %#lx\r\n", iregion_base + IREGION_IDU_OFS); + } + if (mcfg.b.plic) { + printf(" PLIC 64MB %#lx\r\n", iregion_base + IREGION_PLIC_OFS); + } + /* SMP */ + if (mcfg.b.smp) { + printf(" SMP_CFG:"); + printf(" CC_PRESENT=%ld", __RV_EXTRACT_FIELD(smp_cfg, 0x1)); + printf(" SMP_CORE_NUM=%ld", __RV_EXTRACT_FIELD(smp_cfg, 0x3F << 1)); + printf(" IOCP_NUM=%ld", __RV_EXTRACT_FIELD(smp_cfg, 0x3F << 7)); + printf(" PMON_NUM=%ld", __RV_EXTRACT_FIELD(smp_cfg, 0x3F << 13)); + printf("\r\n"); + } + /* ECLIC */ + if (mcfg.b.clic) { + printf(" ECLIC:"); + printf(" VERSION=0x%x", (unsigned int)ECLIC_GetInfoVer()); + printf(" NUM_INTERRUPT=%u", (unsigned int)ECLIC_GetInfoNum()); + printf(" CLICINTCTLBITS=%u", (unsigned int)ECLIC_GetInfoCtlbits()); + printf(" MTH=%u", (unsigned int)ECLIC_GetMth()); + printf(" NLBITS=%u", (unsigned int)ECLIC_GetCfgNlbits()); + printf("\r\n"); + } + + /* L2CACHE */ + if (smp_cfg & BIT(0)) { + uint32_t cc_cfg = *(uint32_t *)(iregion_base + 0x40008); + printf(" L2CACHE:"); + show_cache_info(POWER_FOR_TWO(__RV_EXTRACT_FIELD(cc_cfg, 0xF)), __RV_EXTRACT_FIELD(cc_cfg, 0xf << 4) + 1, + POWER_FOR_TWO(__RV_EXTRACT_FIELD(cc_cfg, 0x7 << 8) + 2), cc_cfg & BIT(11)); + } + + /* INFO */ + printf(" INFO-Detail:\r\n"); + uint32_t mpasize = *(uint32_t *)(iregion_base); + printf(" mpasize : %u\r\n", mpasize); + uint32_t cmo_info = *(uint32_t*)(iregion_base + 4); + if (cmo_info & BIT(0)) { + printf(" cbozero : %uByte\r\n", (unsigned int)POWER_FOR_TWO(__RV_EXTRACT_FIELD(cmo_info, 0xF << 6) + 2)); + printf(" cmo : %uByte\r\n", (unsigned int)POWER_FOR_TWO(__RV_EXTRACT_FIELD(cmo_info, 0xF << 2) + 2)); + if (cmo_info & BIT(1)) { + printf(" has_prefecth\r\n"); + } + } + uint32_t mcppi_cfg_lo = *(uint32_t *)(iregion_base + 0x80); + uint32_t mcppi_cfg_hi = *(uint32_t *)(iregion_base + 0x84); + if (mcppi_cfg_lo & 0x1) { +#if __RISCV_XLEN == 32 + printf(" cppi : %#lx", mcppi_cfg_lo & (~0x3FF)); +#else + printf(" cppi : %#lx", ((uint64_t)mcppi_cfg_hi << 32) | (mcppi_cfg_lo & (~0x3FF))); +#endif + print_size(POWER_FOR_TWO(__RV_EXTRACT_FIELD(mcppi_cfg_lo, 0x1F << 1) - 1) * KB); + printf("\r\n"); + } + } + + /* FIO */ + if (mcfg.b.fio) { + csr_mfiocfg = __RV_CSR_READ(CSR_MFIOCFG_INFO); + printf(" FIO:"); + printf(" %#lx", csr_mfiocfg & (~0x3FF)); + print_size(POWER_FOR_TWO(__RV_EXTRACT_FIELD(csr_mfiocfg, 0x1F << 1) - 1) * KB); + printf("\r\n"); + } + + /* PPI */ + if (mcfg.b.ppi) { + csr_mppicfg = __RV_CSR_READ(CSR_MPPICFG_INFO); + printf(" PPI:"); + printf(" %#lx", csr_mppicfg & (~0x3FF)); + print_size(POWER_FOR_TWO(__RV_EXTRACT_FIELD(csr_mppicfg, 0x1F << 1) - 1) * KB); + printf("\r\n"); + } + + printf("-----End of Nuclei CPU INFO-----\r\n"); +} + +int main(void) +{ + nuclei_cpuinfo(); + + return 0; +} diff --git a/examples/cpuinfo/test/README b/examples/cpuinfo/test/README new file mode 100644 index 0000000..df5066e --- /dev/null +++ b/examples/cpuinfo/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html diff --git a/examples/demo_dsp/README.md b/examples/demo_dsp/README.md index 5f6ba14..4f495b8 100644 --- a/examples/demo_dsp/README.md +++ b/examples/demo_dsp/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/demo_dsp/platformio.ini b/examples/demo_dsp/platformio.ini index 411cafc..c00587c 100644 --- a/examples/demo_dsp/platformio.ini +++ b/examples/demo_dsp/platformio.ini @@ -10,44 +10,48 @@ [platformio] description = example to show how to use NMSIS DSP Library. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [env] platform = nuclei framework = nuclei-sdk monitor_speed = 115200 +board_build.nmsis_lib = nmsis_dsp -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval board_build.download = ilm board_build.core = n307fd -# If you change the board_build.core to different core -# then you need to change this build_flags to include different library -# If the core didn't support dsp feature, please remove the `p` extension -# e.g. If you change board_build.core to n205, then -# build_flags = -lnmsis_dsp_rv32imac -build_flags = -lnmsis_dsp_rv32imafdcp -D__RISCV_FEATURE_DSP=1 - -[env:nuclei-gd32vf103v_rvstar] +board_build.nmsis_lib_arch = rv32imafdc +build_flags = +board_build.stdclib = libncrt_small + +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = flashxip +# you can change to use different toolchain +board_build.toolchain = nuclei_gnu +board_build.arch_ext = _zba_zbb_zbc_zbs_xxldspn1x +board_build.nmsis_lib_arch = rv32imafdc_zba_zbb_zbc_zbs_xxldspn1x +#board_build.stdclib = libncrt_small +build_flags = + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar -# This SoC core don't support dsp feature, -# So we use NMSIS-DSP library with DSP disabled -build_flags = -lnmsis_dsp_rv32imac +build_flags = +board_build.stdclib = libncrt_fast -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -# This SoC core don't support dsp feature, -# So we use NMSIS-DSP library with DSP disabled -build_flags = -lnmsis_dsp_rv32imac +build_flags = -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -# This SoC core don't support dsp feature, -# So we use NMSIS-DSP library with DSP disabled -build_flags = -lnmsis_dsp_rv32imac +build_flags = -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite -# This SoC core don't support dsp feature, -# So we use NMSIS-DSP library with DSP disabled -build_flags = -lnmsis_dsp_rv32imac \ No newline at end of file +build_flags = \ No newline at end of file diff --git a/examples/demo_dsp/src/main.c b/examples/demo_dsp/src/main.c index aad4c4e..bac1501 100644 --- a/examples/demo_dsp/src/main.c +++ b/examples/demo_dsp/src/main.c @@ -5,50 +5,7 @@ #include "ref_conv.h" #include "riscv_math.h" -#ifndef READ_CYCLE -#define READ_CYCLE __get_rv_cycle -#endif - -static uint64_t enter_cycle; -static uint64_t exit_cycle; -static uint64_t start_cycle; -static uint64_t end_cycle; -static uint64_t cycle; -static uint64_t extra_cost = 0; -static uint32_t bench_ercd; - -#define BENCH_TRST() - -#define BENCH_INIT() \ - printf("Benchmark Initialized\n"); \ - BENCH_TRST(); \ - start_cycle = READ_CYCLE(); \ - end_cycle = READ_CYCLE(); \ - extra_cost = end_cycle - start_cycle; \ - enter_cycle = READ_CYCLE(); - -#define BENCH_START(func) \ - bench_ercd = 0; \ - BENCH_TRST(); \ - start_cycle = READ_CYCLE(); - -#define BENCH_END(func) \ - end_cycle = READ_CYCLE(); \ - cycle = end_cycle - start_cycle - extra_cost; \ - printf("CSV, %s, %lu\n", #func, cycle); - -#define BENCH_ERROR(func) bench_ercd = 1; -#define BENCH_STATUS(func) \ - if (bench_ercd) { \ - printf("ERROR, %s\n", #func); \ - } else { \ - printf("SUCCESS, %s\n", #func); \ - } - -#define BENCH_FINISH() \ - exit_cycle = READ_CYCLE(); \ - cycle = exit_cycle - enter_cycle - extra_cost; \ - printf("CSV, BENCH END, %llu\n", cycle); +#include "nmsis_bench.h" static float32_t test_conv_input_f32_A[300] = { 0.240707035480160, 0.676122303863752, 0.289064571674477, @@ -317,12 +274,22 @@ static int test_flag_error = 0; #define DELTAQ15 (2) #define DELTAQ7 (2) +BENCH_DECLARE_VAR(); + int main(void) { printf("\r\nNuclei RISC-V NMSIS-DSP Library Demonstration\r\n"); -#if defined(__RISCV_FEATURE_DSP) && __RISCV_FEATURE_DSP == 1 - printf("Using Nuclei RISC-V DSP(P-ext) accelerated and optimized NMSIS-DSP library!\r\n"); +#if (defined(__RISCV_FEATURE_DSP) && __RISCV_FEATURE_DSP == 1) || \ + (defined(__RISCV_FEATURE_VECTOR) && __RISCV_FEATURE_VECTOR == 1) + printf("Using Nuclei RISC-V accelerated and optimized NMSIS-DSP library!\r\n"); +#if (defined(__RISCV_FEATURE_DSP) && __RISCV_FEATURE_DSP == 1) printf("Warning: Make sure Nuclei RISC-V DSP(P-ext) is present in your CPU core!\r\n"); +#endif +#if (defined(__RISCV_FEATURE_VECTOR) && __RISCV_FEATURE_VECTOR == 1) + printf("Warning: Make sure Nuclei RISC-V Vector is present in your CPU core!\r\n"); + // Enable Vector Unit + __enable_vector(); +#endif printf(" Otherwise this example will trap to cpu core exception!\r\n\r\n"); #else printf("Using c-only optimized NMSIS-DSP library!\r\n"); @@ -475,9 +442,11 @@ int main(void) BENCH_STATUS(riscv_conv_fast_opt_q15); if (test_flag_error) { printf("test error apprears, please recheck.\n"); + NMSIS_TEST_FAIL(); return 1; } else { printf("all test are passed. Well done!\n"); + NMSIS_TEST_PASS(); } return 0; } diff --git a/examples/demo_dsp/src/ref_common.h b/examples/demo_dsp/src/ref_common.h index 0115402..a22979d 100644 --- a/examples/demo_dsp/src/ref_common.h +++ b/examples/demo_dsp/src/ref_common.h @@ -38,6 +38,7 @@ typedef enum { #define DBL_MIN 2.22507385850720138e-308 #endif +#ifndef SCHAR_MIN #define SCHAR_MIN (-128) /* mimimum value for an object of type signed char */ #define SCHAR_MAX 127 @@ -62,7 +63,7 @@ typedef enum { /* maximum value for an object of type long int */ #define ULONG_MAX 0xffffffffUL /* maximum value for an object of type unsigned long int */ - +#endif /* * Helper Functions diff --git a/examples/demo_eclic/README.md b/examples/demo_eclic/README.md index b5b5a9c..11ae570 100644 --- a/examples/demo_eclic/README.md +++ b/examples/demo_eclic/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/demo_eclic/platformio.ini b/examples/demo_eclic/platformio.ini index 746cb0b..f3d113b 100644 --- a/examples/demo_eclic/platformio.ini +++ b/examples/demo_eclic/platformio.ini @@ -10,6 +10,8 @@ [platformio] description = example to show how to use ECLIC and interrupt. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [env] platform = nuclei @@ -18,19 +20,29 @@ monitor_speed = 115200 #Uncomment below for code size optimization with LTO #build_flags = -Os -flto -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval board_build.download = ilm -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = sram +board_build.sysclk = 48000000 +board_build.clksrc = irc16m +board_build.stdclib = libncrt_small + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar +board_build.stdclib = libncrt_nano -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval +board_build.stdclib = newlib_fast -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite \ No newline at end of file diff --git a/examples/demo_eclic/src/demo_eclic.c b/examples/demo_eclic/src/demo_eclic.c index cf8d435..bef0adf 100644 --- a/examples/demo_eclic/src/demo_eclic.c +++ b/examples/demo_eclic/src/demo_eclic.c @@ -2,6 +2,16 @@ #include #include "nuclei_sdk_soc.h" +#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) +#else +#error "This example require CPU ECLIC feature" +#endif + +#if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) +#else +#error "This example require CPU System Timer feature" +#endif + // If define SWIRQ_INTLEVEL_HIGHER equals 1 the software interrupt will have a higher interrupt level. // the software interrupt will run during timer interrupt. // If define SWIRQ_INTLEVEL_HIGHER equals 0 the software interrupt will have a lower interrupt level. @@ -11,12 +21,15 @@ #define HIGHER_INTLEVEL 2 #define LOWER_INTLEVEL 1 -#define TIMER_TICKS (2 * SOC_TIMER_FREQ) +// 100ms +#define TIMER_TICKS (SOC_TIMER_FREQ / 10) + +static volatile uint32_t int_check_cnt = 0; // setup timer void setup_timer(void) { - printf("Initialize timer and start timer interrupt periodly\n\r"); + printf("Initialize timer and start timer interrupt periodically\n\r"); SysTick_Config(TIMER_TICKS); } @@ -57,10 +70,17 @@ __INTERRUPT void eclic_msip_handler(void) printf("[IN SOFTWARE INTERRUPT]software interrupt hit %d times\r\n", int_sw_cnt++); printf("[IN SOFTWARE INTERRUPT]software interrupt end\r\n"); + int_check_cnt ++; // restore CSR context RESTORE_IRQ_CSR_CONTEXT(); } +#ifdef CFG_SIMULATION +#define RUN_LOOPS 2 +#else +#define RUN_LOOPS 20 +#endif + int main(int argc, char** argv) { uint8_t timer_intlevel, swirq_intlevel; @@ -81,17 +101,19 @@ int main(int argc, char** argv) // initialize software interrupt as vector interrupt returnCode = ECLIC_Register_IRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT, - ECLIC_LEVEL_TRIGGER, swirq_intlevel, 0, eclic_msip_handler); + ECLIC_LEVEL_TRIGGER, swirq_intlevel, 0, (void*)eclic_msip_handler); // inital timer interrupt as non-vector interrupt returnCode = ECLIC_Register_IRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT, - ECLIC_LEVEL_TRIGGER, timer_intlevel, 0, eclic_mtip_handler); + ECLIC_LEVEL_TRIGGER, timer_intlevel, 0, (void*)eclic_mtip_handler); // Enable interrupts in general. __enable_irq(); // Wait for timer interrupt and software interrupt - // triggered periodly - while (1); + // triggered periodically + while (int_check_cnt < RUN_LOOPS); + __disable_irq(); + printf("ECLIC Demo finished sucessfully in %d loops\n", RUN_LOOPS); return 0; } diff --git a/examples/demo_nice/README.md b/examples/demo_nice/README.md index 53ba5bc..9541d3c 100644 --- a/examples/demo_nice/README.md +++ b/examples/demo_nice/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-hbird_eval +$ pio run -e hbird_eval # Upload firmware for the specific environment -$ pio run -e nuclei-hbird_eval --target upload +$ pio run -e hbird_eval --target upload # Clean build files $ pio run --target clean diff --git a/examples/demo_nice/platformio.ini b/examples/demo_nice/platformio.ini index d3072ac..d7c1094 100644 --- a/examples/demo_nice/platformio.ini +++ b/examples/demo_nice/platformio.ini @@ -18,6 +18,7 @@ monitor_speed = 115200 #Uncomment below for code size optimization with LTO #build_flags = -Os -flto -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval -board_build.download = ilm \ No newline at end of file +board_build.download = flash +board_build.stdclib = newlib_fast diff --git a/examples/demo_nice/src/insn.c b/examples/demo_nice/src/insn.c index 1739486..f859da4 100644 --- a/examples/demo_nice/src/insn.c +++ b/examples/demo_nice/src/insn.c @@ -38,15 +38,15 @@ void print_array(unsigned int array[ROW_LEN][COL_LEN]) int i, j; printf("the element of array is :\r\n\t"); for (i = 0; i < ROW_LEN; i++) { - printf("%d\t", array[0][i]); + printf("%u\t", array[0][i]); } printf("\r\n\t"); for (i = 0; i < ROW_LEN; i++) { - printf("%d\t", array[1][i]); + printf("%u\t", array[1][i]); } printf("\r\n\t"); for (i = 0; i < ROW_LEN; i++) { - printf("%d\t", array[2][i]); + printf("%u\t", array[2][i]); } printf("\r\n\r\n"); } @@ -56,12 +56,12 @@ void print_result(unsigned int col_sum[COL_LEN], unsigned int row_sum[ROW_LEN]) int i, j; printf("the sum of each row is :\r\n\t\t"); for (i = 0; i < ROW_LEN; i++) { - printf("%d\t", row_sum[i]); + printf("%u\t", row_sum[i]); } printf("\r\n"); printf("the sum of each col is :\r\n\t\t"); for (j = 0; j < COL_LEN; j++) { - printf("%d\t", col_sum[j]); + printf("%u\t", col_sum[j]); } printf("\r\n"); } @@ -73,7 +73,7 @@ int compare_result(unsigned int ref_cs[COL_LEN], unsigned int ref_rs[ROW_LEN], \ for (i = 0; i < COL_LEN; i ++) { if (ref_cs[i] != nice_cs[i]) { #ifdef _DEBUG_INFO_ - printf("Column %d result not match: %d vs %d\r\n", ref_cs[i], nice_cs[i]); + printf("Column %d result not match: %u vs %u\r\n", i, ref_cs[i], nice_cs[i]); #endif ret = -1; } @@ -81,7 +81,7 @@ int compare_result(unsigned int ref_cs[COL_LEN], unsigned int ref_rs[ROW_LEN], \ for (i = 0; i < ROW_LEN; i ++) { if (ref_rs[i] != nice_rs[i]) { #ifdef _DEBUG_INFO_ - printf("Row %d result not match: %d vs %d\r\n", ref_rs[i], nice_rs[i]); + printf("Row %d result not match: %u vs %u\r\n", i, ref_rs[i], nice_rs[i]); #endif ret = -1; } diff --git a/examples/demo_nice/src/insn.h b/examples/demo_nice/src/insn.h index 0795fc5..02b31b5 100644 --- a/examples/demo_nice/src/insn.h +++ b/examples/demo_nice/src/insn.h @@ -12,7 +12,7 @@ extern "C" { ****************************************************************************************** * NICE Extension Instruction Format: * .insn and r indicates this is a pseudo and R-type instruction. - * 0x7b is the value of the opcode field, which means it is a + * 0x5b is the value of the opcode field, which means it is a * NICE instruction belonging to custom3. * Supported format: only R type here * This NICE Demo implements the following 3 instructions for NICE-Core: @@ -20,13 +20,13 @@ extern "C" { * * CSW or sbuf: Store 12-byte data from row buffer to memory. * * CACC or rowsum: Sums a row of the matrix, and columns are accumulated automatically. * Supported instructions for this nice demo: - * 1. custom3 lbuf: burst 4 load(4 cycles) data in memory to row_buf + * 1. custom2 lbuf: burst 4 load(4 cycles) data in memory to row_buf * lbuf (a1) * .insn r opcode, func3, func7, rd, rs1, rs2 - * 2. custom3 sbuf: burst 4 store(4 cycles) row_buf to memory + * 2. custom2 sbuf: burst 4 store(4 cycles) row_buf to memory * sbuf (a1) * .insn r opcode, func3, func7, rd, rs1, rs2 - * 3. custom3 acc rowsum: load data from memory(@a1), accumulate row data and write back + * 3. custom2 acc rowsum: load data from memory(@a1), accumulate row data and write back * rowsum rd, a1, x0(N cycles) * .insn r opcode, func3, func7, rd, rs1, rs2 ****************************************************************************************** @@ -35,12 +35,16 @@ extern "C" { #define ROW_LEN 3 #define COL_LEN 3 +// TODO: demo nice opcode change according to rtl updates: +// demo nice is just an demo used to prove Nuclei NICE feature, so this opcode might change frequently +// 20231023: 0x5b -> 0xb +// 20220721: 0x7b -> 0x5b + /** custom nice instruction lbuf */ __STATIC_FORCEINLINE void custom_lbuf(unsigned long* addr) { int zero = 0; - - asm volatile(".insn r 0x7b, 2, 1, x0, %1, x0" : "=r"(zero) : "r"(addr)); + asm volatile(".insn r 0xb, 2, 1, x0, %1, x0" : "=r"(zero) : "r"(addr)); } /** custom nice instruction sbuf */ @@ -48,7 +52,7 @@ __STATIC_FORCEINLINE void custom_sbuf(unsigned long* addr) { int zero = 0; - asm volatile(".insn r 0x7b, 2, 2, x0, %1, x0" : "=r"(zero) : "r"(addr)); + asm volatile(".insn r 0xb, 2, 2, x0, %1, x0" : "=r"(zero) : "r"(addr)); } /** custom nice instruction rowsum */ @@ -56,7 +60,7 @@ __STATIC_FORCEINLINE int custom_rowsum(unsigned long* addr) { int rowsum; - asm volatile(".insn r 0x7b, 6, 6, %0, %1, x0" : "=r"(rowsum) : "r"(addr)); + asm volatile(".insn r 0xb, 6, 6, %0, %1, x0" : "=r"(rowsum) : "r"(addr)); return rowsum; } diff --git a/examples/demo_nice/src/main.c b/examples/demo_nice/src/main.c index e6b757d..3a14858 100644 --- a/examples/demo_nice/src/main.c +++ b/examples/demo_nice/src/main.c @@ -4,6 +4,7 @@ int main(void) { + int ret = 0; unsigned int array[ROW_LEN][COL_LEN] = { {10, 30, 90}, {20, 40, 80}, @@ -13,10 +14,10 @@ int main(void) unsigned int row_sum_ref[ROW_LEN] = {0}; unsigned int col_sum_nice[COL_LEN] = {0}; unsigned int row_sum_nice[ROW_LEN] = {0}; - unsigned int begin_instret, end_instret, instret_normal, instret_nice; - unsigned int begin_cycle, end_cycle, cycle_normal, cycle_nice; + unsigned long begin_instret, end_instret, instret_normal, instret_nice; + unsigned long begin_cycle, end_cycle, cycle_normal, cycle_nice; - __RV_CSR_WRITE(CSR_MSTATUS, MSTATUS_XS); + __RV_CSR_SET(CSR_MSTATUS, MSTATUS_XS); __enable_minstret_counter(); __enable_mcycle_counter(); @@ -63,14 +64,15 @@ int main(void) printf("PASS\r\n"); } else { printf("FAIL\r\n"); + ret = 1; } printf("4. Performance summary\r\n"); printf("\t normal: \r\n"); - printf("\t instret: %u, cycle: %u\r\n", instret_normal, cycle_normal); + printf("\t instret: %lu, cycle: %lu\r\n", instret_normal, cycle_normal); printf("\t nice : \r\n"); - printf("\t instret: %u, cycle: %u\r\n", instret_nice, cycle_nice); + printf("\t instret: %lu, cycle: %lu\r\n", instret_nice, cycle_nice); - return 0; + return ret; } diff --git a/examples/demo_timer/README.md b/examples/demo_timer/README.md index b83631f..bb323e9 100644 --- a/examples/demo_timer/README.md +++ b/examples/demo_timer/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/demo_timer/platformio.ini b/examples/demo_timer/platformio.ini index 29376f6..5eab6cc 100644 --- a/examples/demo_timer/platformio.ini +++ b/examples/demo_timer/platformio.ini @@ -16,19 +16,25 @@ platform = nuclei framework = nuclei-sdk monitor_speed = 115200 -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval board_build.download = ilm -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = sram +board_build.stdclib = libncrt_small + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite \ No newline at end of file diff --git a/examples/demo_timer/src/main.c b/examples/demo_timer/src/main.c index 96c3a39..7482553 100644 --- a/examples/demo_timer/src/main.c +++ b/examples/demo_timer/src/main.c @@ -1,35 +1,37 @@ // See LICENSE for license details. #include #include "nuclei_sdk_soc.h" + +#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) +#else +#error "This example require CPU ECLIC feature" +#endif + +#if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) +#else +#error "This example require CPU System Timer feature" +#endif + /* Define the interrupt handler name same as vector table in case download mode is flashxip. */ #define mtimer_irq_handler eclic_mtip_handler #define mtimer_sw_irq_handler eclic_msip_handler -static uint32_t int0_cnt = 0; /* msip timer interrupt test counter */ -static uint32_t int1_cnt = 0; /* mtip timer interrupt test counter */ -unsigned int msip_trig_flag = 1; /* sw trigger mtimer sw interrupt flag */ - -void wait_seconds(size_t n) -{ - uint64_t start_mtime, delta_mtime; +static volatile uint32_t int0_cnt = 0; /* mtip timer interrupt test counter */ +static volatile uint32_t int1_cnt = 0; /* msip timer interrupt test counter */ +volatile unsigned int msip_trig_flag = 1; /* sw trigger mtimer sw interrupt flag */ - uint64_t tmp = SysTimer_GetLoadValue(); - do { - start_mtime = SysTimer_GetLoadValue(); - } while (start_mtime == tmp); - - do { - delta_mtime = SysTimer_GetLoadValue() - start_mtime; - } while (delta_mtime < (n * SOC_TIMER_FREQ)); -} +#ifdef CFG_SIMULATION +#define LOOP_COUNT 2 +#else +#define LOOP_COUNT 5 +#endif void mtimer_irq_handler(void) { int0_cnt++; - wait_seconds(1); printf("MTimer IRQ handler %d\n\r", int0_cnt); uint64_t now = SysTimer_GetLoadValue(); - SysTimer_SetCompareValue(now + 0.5 * SOC_TIMER_FREQ); + SysTimer_SetCompareValue(now + SOC_TIMER_FREQ / 10); } void mtimer_sw_irq_handler(void) @@ -44,7 +46,7 @@ void setup_timer() { printf("init timer and start\n\r"); uint64_t now = SysTimer_GetLoadValue(); - uint64_t then = now + 0.5 * SOC_TIMER_FREQ; + uint64_t then = now + SOC_TIMER_FREQ / 10; SysTimer_SetCompareValue(then); } @@ -54,27 +56,27 @@ int main(void) returnCode = ECLIC_Register_IRQ( SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT, ECLIC_LEVEL_TRIGGER, 1, 0, - mtimer_irq_handler); /* register system timer interrupt */ + (void *)mtimer_irq_handler); /* register system timer interrupt */ __enable_irq(); /* enable global interrupt */ setup_timer(); /* initialize timer */ - while (int0_cnt < 10); + while (int0_cnt < LOOP_COUNT); ECLIC_DisableIRQ(SysTimer_IRQn); /* Disable MTIP iterrupt */ returnCode = ECLIC_Register_IRQ( SysTimerSW_IRQn, ECLIC_NON_VECTOR_INTERRUPT, ECLIC_POSTIVE_EDGE_TRIGGER, 2, 0, - mtimer_sw_irq_handler); /* register system timer SW interrupt */ + (void *)mtimer_sw_irq_handler); /* register system timer SW interrupt */ do { if (msip_trig_flag == 1) { msip_trig_flag = 0; SysTimer_SetSWIRQ(); /* trigger timer sw interrupt */ - wait_seconds(1); + delay_1ms(10); } - } while (int1_cnt < 10); /* check test end condition */ + } while (int1_cnt < LOOP_COUNT); /* check test end condition */ printf("MTimer msip and mtip interrupt test finish and pass\r\n"); @@ -82,7 +84,6 @@ int main(void) return -1; } - while (1); return 0; } diff --git a/examples/dhrystone/README.md b/examples/dhrystone/README.md index f32fcc9..d60729b 100644 --- a/examples/dhrystone/README.md +++ b/examples/dhrystone/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/dhrystone/platformio.ini b/examples/dhrystone/platformio.ini index 48f65c5..571cf5b 100644 --- a/examples/dhrystone/platformio.ini +++ b/examples/dhrystone/platformio.ini @@ -10,6 +10,8 @@ [platformio] description = Dhyrstone benchmark. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [common] compile_flags = -O3 -fno-inline -funroll-loops @@ -26,20 +28,29 @@ monitor_speed = 115200 build_unflags = -Os build_flags = ${common.compile_flags} -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval # Changed to use ilm download mode board_build.download = ilm +board_build.core = n300f +board_build.stdclib = newlib_small -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = sram +board_build.stdclib = newlib_small + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar +board_build.stdclib = libncrt_small -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite diff --git a/examples/dhrystone/src/dhry.h b/examples/dhrystone/src/dhry.h index 50db655..7e19165 100644 --- a/examples/dhrystone/src/dhry.h +++ b/examples/dhrystone/src/dhry.h @@ -344,6 +344,9 @@ * *************************************************************************** */ +#ifndef _DHRY_H_ +#define _DHRY_H_ + //Bob: here we add define TIME and NOENUM #define TIME #define NOENUM @@ -386,8 +389,7 @@ Enumeration; /* General definitions: */ -#include -/* for strcpy, strcmp */ +#include #define Null 0 /* Value of a Null pointer */ @@ -422,4 +424,4 @@ typedef struct record { } variant; } Rec_Type, *Rec_Pointer; - +#endif diff --git a/examples/dhrystone/src/dhry_1.c b/examples/dhrystone/src/dhry_1.c index bdeec4e..cfcfb85 100644 --- a/examples/dhrystone/src/dhry_1.c +++ b/examples/dhrystone/src/dhry_1.c @@ -14,12 +14,13 @@ * **************************************************************************** */ - #include "dhry.h" -#include "string.h" + +#include +#include #include -/* Global Variables: */ +/* Global Variables: */ Rec_Pointer Ptr_Glob, Next_Ptr_Glob; int Int_Glob; @@ -29,10 +30,6 @@ char Ch_1_Glob, int Arr_1_Glob [50]; int Arr_2_Glob [50] [50]; -//extern char *malloc (); -Enumeration Func_1(); -/* forward declaration necessary since Enumeration may not simply be int */ - #ifndef REG Boolean Reg = false; #define REG @@ -52,12 +49,24 @@ extern int times(); /* Measurements should last at least about 2 seconds */ #endif #ifdef TIME -extern long time(); +extern long time(void); /* see library function "time" */ #define Too_Small_Time 2 /* Measurements should last at least 2 seconds */ #endif +extern long csr_cycle(void); +extern long csr_instret(void); +extern void reset_cycle(void); +extern void reset_instret(void); + +extern Enumeration Func_1(Capital_Letter Ch_1_Par_Val, Capital_Letter Ch_2_Par_Val); +extern Boolean Func_2(Str_30 Str_1_Par_Ref, Str_30 Str_2_Par_Ref); +extern Boolean Func_3(Enumeration Enum_Par_Val); +extern void Proc_6(Enumeration Enum_Val_Par, Enumeration* Enum_Ref_Par); +extern void Proc_7(One_Fifty Int_1_Par_Val, One_Fifty Int_2_Par_Val, One_Fifty* Int_Par_Ref); +extern void Proc_8(Arr_1_Dim Arr_1_Par_Ref, Arr_2_Dim Arr_2_Par_Ref, int Int_1_Par_Val, int Int_2_Par_Val); + long Begin_Cycle, End_Cycle, User_Cycle; @@ -73,9 +82,116 @@ float Microseconds, float DMIPS_MHZ; /* end of variables for time measurement */ +/* Only support dec number < 1000 */ +static char *dec2str(uint32_t val) +{ + static char str[4]; + val = val % 1000; + int decnum = 100; + for (int i = 0; i < 3; i ++) { + str[i] = val / decnum + '0'; + val = val % decnum; + decnum = decnum / 10; + } + str[3] = '\0'; + return str; +} + +void Proc_3(Rec_Pointer* Ptr_Ref_Par) +/******************/ +/* executed once */ +/* Ptr_Ref_Par becomes Ptr_Glob */ +{ + if (Ptr_Glob != Null) + /* then, executed */ + { + *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; + } + Proc_7(10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); +} /* Proc_3 */ + +void Proc_1(REG Rec_Pointer Ptr_Val_Par) +/******************/ +/* executed once */ +{ + REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; + /* == Ptr_Glob_Next */ + /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ + /* corresponds to "rename" in Ada, "with" in Pascal */ + structassign(*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); + Ptr_Val_Par->variant.var_1.Int_Comp = 5; + Next_Record->variant.var_1.Int_Comp + = Ptr_Val_Par->variant.var_1.Int_Comp; + Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; + Proc_3(&Next_Record->Ptr_Comp); + /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp + == Ptr_Glob->Ptr_Comp */ + if (Next_Record->Discr == Ident_1) + /* then, executed */ + { + Next_Record->variant.var_1.Int_Comp = 6; + Proc_6(Ptr_Val_Par->variant.var_1.Enum_Comp, + &Next_Record->variant.var_1.Enum_Comp); + Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; + Proc_7(Next_Record->variant.var_1.Int_Comp, 10, + &Next_Record->variant.var_1.Int_Comp); + } else { /* not executed */ + structassign(*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); + } +} /* Proc_1 */ -main() +void Proc_2(One_Fifty* Int_Par_Ref) +/******************/ +/* executed once */ +/* *Int_Par_Ref == 1, becomes 4 */ +{ + One_Fifty Int_Loc; + Enumeration Enum_Loc; + + Int_Loc = *Int_Par_Ref + 10; + do /* executed once */ + if (Ch_1_Glob == 'A') + /* then, executed */ + { + Int_Loc -= 1; + *Int_Par_Ref = Int_Loc - Int_Glob; + Enum_Loc = Ident_1; + } /* if */ + while (Enum_Loc != Ident_1); /* true */ +} /* Proc_2 */ + +void Proc_4(void) /* without parameters */ +/*******/ +/* executed once */ +{ + Boolean Bool_Loc; + + Bool_Loc = Ch_1_Glob == 'A'; + Bool_Glob = Bool_Loc | Bool_Glob; + Ch_2_Glob = 'B'; +} /* Proc_4 */ + +void Proc_5(void) /* without parameters */ +/*******/ +/* executed once */ +{ + Ch_1_Glob = 'A'; + Bool_Glob = false; +} /* Proc_5 */ + +/* Procedure for the assignment of structures, */ +/* if the C compiler doesn't support this feature */ +#ifdef NOSTRUCTASSIGN +void memcpy(register char* d, register char* s, register int l) +{ + while (l--) { + *d++ = *s++; + } +} +#endif + +int main(void) /*****/ /* main program, corresponds to procedures */ @@ -120,18 +236,15 @@ main() printf("Program compiled without 'register' attribute\n"); printf("\n"); } - printf("Please give the number of runs through the benchmark: "); + printf("Please give the number of runs through the benchmark: \n"); { - int n; - //Bob: We dont use scanf #ifdef CFG_SIMULATION //Bob: for simulation we make it small - Number_Of_Runs = 5; + Number_Of_Runs = 200; #else Number_Of_Runs = 500000; #endif } - printf("\n"); printf("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); @@ -145,10 +258,16 @@ main() Begin_Time = (long) time_info.tms_utime; #endif #ifdef TIME - Begin_Time = time((long*) 0); + Begin_Time = time(); #endif - Begin_Instret = csr_instret((long*) 0); - Begin_Cycle = csr_cycle((long*) 0); + + // Reset cycle and instret to zero + reset_cycle(); + reset_instret(); + + // Start sample + Begin_Cycle = csr_cycle(); + Begin_Instret = csr_instret(); for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index) { @@ -197,16 +316,16 @@ main() /**************/ /* Stop timer */ /**************/ - End_Cycle = csr_cycle((long*) 0); + End_Cycle = csr_cycle(); + End_Instret = csr_instret(); #ifdef TIMES times(&time_info); End_Time = (long) time_info.tms_utime; #endif #ifdef TIME - End_Time = time((long*) 0); + End_Time = time(); #endif - End_Instret = csr_instret((long*) 0); printf("Execution ends\n"); printf("\n"); @@ -225,7 +344,7 @@ main() printf("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); printf(" should be: Number_Of_Runs + 10\n"); printf("Ptr_Glob->\n"); - printf(" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); + printf(" Ptr_Comp: %ld\n", (long) Ptr_Glob->Ptr_Comp); printf(" should be: (implementation-dependent)\n"); printf(" Discr: %d\n", Ptr_Glob->Discr); printf(" should be: %d\n", 0); @@ -236,7 +355,7 @@ main() printf(" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); printf(" should be: DHRYSTONE PROGRAM, SOME STRING\n"); printf("Next_Ptr_Glob->\n"); - printf(" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); + printf(" Ptr_Comp: %ld\n", (long) Next_Ptr_Glob->Ptr_Comp); printf(" should be: (implementation-dependent), same as above\n"); printf(" Discr: %d\n", Next_Ptr_Glob->Discr); printf(" should be: %d\n", 0); @@ -265,147 +384,39 @@ main() User_Instret = End_Instret - Begin_Instret; User_Cycle = End_Cycle - Begin_Cycle; -#ifdef CFG_SIMULATION - if (0) -#else - if (User_Time < Too_Small_Time) -#endif - { - printf("Measured time too small to obtain meaningful results\n"); - printf("Please increase number of runs\n"); - printf("\n"); - } else { + #ifdef TIME - Microseconds = (float) User_Time * Mic_secs_Per_Second - / (float) Number_Of_Runs; - Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; + Microseconds = (float) User_Time * Mic_secs_Per_Second / (float) Number_Of_Runs; + Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; #else - Microseconds = (float) User_Time * Mic_secs_Per_Second - / ((float) HZ * ((float) Number_Of_Runs)); - Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) - / (float) User_Time; + Microseconds = (float) User_Time * Mic_secs_Per_Second + / ((float) HZ * ((float) Number_Of_Runs)); + Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) + / (float) User_Time; #endif - Instret = User_Instret / Number_Of_Runs; - - DMIPS_MHZ = (1000000 / ((float)User_Cycle / (float)Number_Of_Runs)) / 1757; - - printf(" (*) User_Cycle for total run through Dhrystone with loops %d: \n", Number_Of_Runs); - printf("%ld \n", User_Cycle); - printf(" So the DMIPS/MHz can be caculated by: \n"); - printf(" 1000000/(User_Cycle/Number_Of_Runs)/1757 = %2.6f DMIPS/MHz\n", DMIPS_MHZ); - printf("\n"); - } - -} - - -Proc_1(Ptr_Val_Par) -/******************/ - -REG Rec_Pointer Ptr_Val_Par; -/* executed once */ -{ - REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; - /* == Ptr_Glob_Next */ - /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ - /* corresponds to "rename" in Ada, "with" in Pascal */ - - structassign(*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); - Ptr_Val_Par->variant.var_1.Int_Comp = 5; - Next_Record->variant.var_1.Int_Comp - = Ptr_Val_Par->variant.var_1.Int_Comp; - Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; - Proc_3(&Next_Record->Ptr_Comp); - /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp - == Ptr_Glob->Ptr_Comp */ - if (Next_Record->Discr == Ident_1) - /* then, executed */ - { - Next_Record->variant.var_1.Int_Comp = 6; - Proc_6(Ptr_Val_Par->variant.var_1.Enum_Comp, - &Next_Record->variant.var_1.Enum_Comp); - Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; - Proc_7(Next_Record->variant.var_1.Int_Comp, 10, - &Next_Record->variant.var_1.Int_Comp); - } else { /* not executed */ - structassign(*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); - } -} /* Proc_1 */ - - -Proc_2(Int_Par_Ref) -/******************/ -/* executed once */ -/* *Int_Par_Ref == 1, becomes 4 */ - -One_Fifty* Int_Par_Ref; -{ - One_Fifty Int_Loc; - Enumeration Enum_Loc; + Instret = User_Instret / Number_Of_Runs; - Int_Loc = *Int_Par_Ref + 10; - do /* executed once */ - if (Ch_1_Glob == 'A') - /* then, executed */ - { - Int_Loc -= 1; - *Int_Par_Ref = Int_Loc - Int_Glob; - Enum_Loc = Ident_1; - } /* if */ - while (Enum_Loc != Ident_1); /* true */ -} /* Proc_2 */ - - -Proc_3(Ptr_Ref_Par) -/******************/ -/* executed once */ -/* Ptr_Ref_Par becomes Ptr_Glob */ - -Rec_Pointer* Ptr_Ref_Par; - -{ - if (Ptr_Glob != Null) - /* then, executed */ - { - *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; - } - Proc_7(10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); -} /* Proc_3 */ + DMIPS_MHZ = (1000000 / ((float)User_Cycle / (float)Number_Of_Runs)) / 1757; + printf(" (*) User_Cycle for total run through Dhrystone with loops %d: \n", Number_Of_Runs); + printf("%ld \n", User_Cycle); + printf(" So the DMIPS/MHz can be calculated by: \n"); + printf(" 1000000/(User_Cycle/Number_Of_Runs)/1757 = %2.6f DMIPS/MHz\n", DMIPS_MHZ); + printf("\n"); -Proc_4() /* without parameters */ -/*******/ -/* executed once */ -{ - Boolean Bool_Loc; + uint32_t dhry_dmips = (uint32_t)(DMIPS_MHZ * 1000); + char *pstr = dec2str(dhry_dmips); + printf("\nCSV, Benchmark, Iterations, Cycles, DMIPS/MHz\n"); + printf("CSV, Dhrystone, %u, %u, %u.%s\n", \ + (unsigned int)Number_Of_Runs, (unsigned int)User_Cycle, (unsigned int)(dhry_dmips/1000), pstr); - Bool_Loc = Ch_1_Glob == 'A'; - Bool_Glob = Bool_Loc | Bool_Glob; - Ch_2_Glob = 'B'; -} /* Proc_4 */ + float f_ipc = (((float)User_Instret / User_Cycle)); + uint32_t i_ipc = (uint32_t)(f_ipc * 1000); + pstr = dec2str(i_ipc); + printf("IPC = Instret/Cycle = %u/%u = %u.%s\n", (unsigned int)User_Instret, (unsigned int)User_Cycle, (unsigned int)(i_ipc/1000), pstr); -Proc_5() /* without parameters */ -/*******/ -/* executed once */ -{ - Ch_1_Glob = 'A'; - Bool_Glob = false; -} /* Proc_5 */ - - -/* Procedure for the assignment of structures, */ -/* if the C compiler doesn't support this feature */ -#ifdef NOSTRUCTASSIGN -memcpy(d, s, l) -register char* d; -register char* s; -register int l; -{ - while (l--) { - *d++ = *s++; - } + return 0; } -#endif diff --git a/examples/dhrystone/src/dhry_2.c b/examples/dhrystone/src/dhry_2.c index 748a475..2023141 100644 --- a/examples/dhrystone/src/dhry_2.c +++ b/examples/dhrystone/src/dhry_2.c @@ -26,14 +26,36 @@ extern int Int_Glob; extern char Ch_1_Glob; +// TODO: clang not yet provide any xxlcz instruction support +#if defined(__riscv_xxlcz) && !defined(__clang__) +extern int strcmp_xlcz(const char* str1, const char* str2); +#define STRCMP(str1, str2) strcmp_xlcz(str1, str2) +#else +#define STRCMP(str1, str2) strcmp(str1, str2) +#endif + + +Boolean Func_3(Enumeration Enum_Par_Val) +/***************************/ +/* executed once */ +/* Enum_Par_Val == Ident_3 */ +{ + Enumeration Enum_Loc; -Proc_6(Enum_Val_Par, Enum_Ref_Par) + Enum_Loc = Enum_Par_Val; + if (Enum_Loc == Ident_3) + /* then, executed */ + { + return (true); + } else { /* not executed */ + return (false); + } +} /* Func_3 */ + +void Proc_6(Enumeration Enum_Val_Par, Enumeration* Enum_Ref_Par) /*********************************/ /* executed once */ /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ - -Enumeration Enum_Val_Par; -Enumeration* Enum_Ref_Par; { *Enum_Ref_Par = Enum_Val_Par; if (! Func_3(Enum_Val_Par)) @@ -66,7 +88,7 @@ Enumeration* Enum_Ref_Par; } /* Proc_6 */ -Proc_7(Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) +void Proc_7(One_Fifty Int_1_Par_Val, One_Fifty Int_2_Par_Val, One_Fifty* Int_Par_Ref) /**********************************************/ /* executed three times */ /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ @@ -75,9 +97,6 @@ Proc_7(Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) /* Int_Par_Ref becomes 17 */ /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ /* Int_Par_Ref becomes 18 */ -One_Fifty Int_1_Par_Val; -One_Fifty Int_2_Par_Val; -One_Fifty* Int_Par_Ref; { One_Fifty Int_Loc; @@ -86,15 +105,11 @@ One_Fifty* Int_Par_Ref; } /* Proc_7 */ -Proc_8(Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) +void Proc_8(Arr_1_Dim Arr_1_Par_Ref, Arr_2_Dim Arr_2_Par_Ref, int Int_1_Par_Val, int Int_2_Par_Val) /*********************************************************************/ /* executed once */ /* Int_Par_Val_1 == 3 */ /* Int_Par_Val_2 == 7 */ -Arr_1_Dim Arr_1_Par_Ref; -Arr_2_Dim Arr_2_Par_Ref; -int Int_1_Par_Val; -int Int_2_Par_Val; { REG One_Fifty Int_Index; REG One_Fifty Int_Loc; @@ -112,15 +127,12 @@ int Int_2_Par_Val; } /* Proc_8 */ -Enumeration Func_1(Ch_1_Par_Val, Ch_2_Par_Val) +Enumeration Func_1(Capital_Letter Ch_1_Par_Val, Capital_Letter Ch_2_Par_Val) /*************************************************/ /* executed three times */ /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ - -Capital_Letter Ch_1_Par_Val; -Capital_Letter Ch_2_Par_Val; { Capital_Letter Ch_1_Loc; Capital_Letter Ch_2_Loc; @@ -138,14 +150,12 @@ Capital_Letter Ch_2_Par_Val; } /* Func_1 */ -Boolean Func_2(Str_1_Par_Ref, Str_2_Par_Ref) +Boolean Func_2(Str_30 Str_1_Par_Ref, Str_30 Str_2_Par_Ref) /*************************************************/ /* executed once */ /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ -Str_30 Str_1_Par_Ref; -Str_30 Str_2_Par_Ref; { REG One_Thirty Int_Loc; Capital_Letter Ch_Loc; @@ -169,7 +179,7 @@ Str_30 Str_2_Par_Ref; { return (true); } else { /* executed */ - if (strcmp(Str_1_Par_Ref, Str_2_Par_Ref) > 0) + if (STRCMP(Str_1_Par_Ref, Str_2_Par_Ref) > 0) /* then, not executed */ { Int_Loc += 7; @@ -181,22 +191,4 @@ Str_30 Str_2_Par_Ref; } /* if Ch_Loc */ } /* Func_2 */ - -Boolean Func_3(Enum_Par_Val) -/***************************/ -/* executed once */ -/* Enum_Par_Val == Ident_3 */ -Enumeration Enum_Par_Val; -{ - Enumeration Enum_Loc; - - Enum_Loc = Enum_Par_Val; - if (Enum_Loc == Ident_3) - /* then, executed */ - { - return (true); - } else { /* not executed */ - return (false); - } -} /* Func_3 */ - +#undef STRCMP \ No newline at end of file diff --git a/examples/dhrystone/src/dhry_stubs.c b/examples/dhrystone/src/dhry_stubs.c index aac6b5d..fb2b3ee 100644 --- a/examples/dhrystone/src/dhry_stubs.c +++ b/examples/dhrystone/src/dhry_stubs.c @@ -1,7 +1,14 @@ #include "nuclei_sdk_soc.h" -/* The functions in this file are only meant to support Dhrystone on an - * embedded RV32 system and are obviously incorrect in general. */ +void reset_cycle(void) +{ + __set_rv_cycle(0); +} + +void reset_instret(void) +{ + __set_rv_instret(0); +} long csr_cycle(void) { @@ -15,6 +22,10 @@ long csr_instret(void) long time(void) { +#if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) return SysTimer_GetLoadValue() / SOC_TIMER_FREQ; +#else +#error "This example require CPU System Timer feature" +#endif } diff --git a/examples/dhrystone/src/strcmp_xlcz.S b/examples/dhrystone/src/strcmp_xlcz.S new file mode 100644 index 0000000..2de8eb7 --- /dev/null +++ b/examples/dhrystone/src/strcmp_xlcz.S @@ -0,0 +1,56 @@ +// TODO: clang not yet provide any xxlcz instruction support +#if defined(__riscv_xxlcz) && !defined(__clang__) +.global strcmp_xlcz +strcmp_xlcz: + xl.addrchk a0, a1, unalgns +loop: + xl.lw a2, 4(a0) + xl.lw a3, 4(a1) + + xl.lw a4, 4(a0) + xl.lw a5, 4(a1) + + xl.lw a6, 4(a0) + xl.lw a7, 4(a1) + + xl.lw t0, 4(a0) + xl.lw t1, 4(a1) + + xl.bezm a2, a3, Lcomp1 + xl.bezm a4, a5, Lcomp2 + xl.bezm a6, a7, Lcomp3 + xl.bezm t0, t1, Lcomp4 + + j loop + +Lcomp1: + xl.nzmsk a5, a2 + j ffnz + +Lcomp2: + xl.nzmsk a5, a4 + j ffnz + +Lcomp3: + xl.nzmsk a5, a6 + j ffnz + +Lcomp4: + xl.nzmsk a5, t0 + +ffnz: + and a5, a5, t6 + xl.ffnz a0, a5 + ret + +unalgns: + xl.lbu a2, 1(a0) + xl.lbu a3, 1(a1) + bne a2, a3, get_res; + bnez a2, unalgns + +get_res: + sub a0, a2, a3 + ret + +#endif diff --git a/examples/freertos_demo/README.md b/examples/freertos_demo/README.md index 6927572..a59173a 100644 --- a/examples/freertos_demo/README.md +++ b/examples/freertos_demo/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/freertos_demo/platformio.ini b/examples/freertos_demo/platformio.ini index 69dcfb2..33a8a45 100644 --- a/examples/freertos_demo/platformio.ini +++ b/examples/freertos_demo/platformio.ini @@ -11,6 +11,8 @@ [platformio] description = A simple FreeRTOS demo to demonstrate FreeRTOS usage and build environment. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [env] platform = nuclei @@ -18,19 +20,26 @@ framework = nuclei-sdk monitor_speed = 115200 board_build.rtos = freertos -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval board_build.download = ilm +board_build.core = n300 +board_build.arch_ext = _zba_zbb_zbc_zbs -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = sram + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite diff --git a/examples/freertos_demo/src/main.c b/examples/freertos_demo/src/main.c index 6306541..d2ac335 100644 --- a/examples/freertos_demo/src/main.c +++ b/examples/freertos_demo/src/main.c @@ -76,13 +76,13 @@ #include #include -#include #include "nuclei_sdk_soc.h" /* The period of the example software timer, specified in milliseconds, and converted to ticks using the pdMS_TO_TICKS() macro. */ -#define mainSOFTWARE_TIMER_PERIOD_MS pdMS_TO_TICKS(1000) +#define mainSOFTWARE_TIMER_PERIOD_MS pdMS_TO_TICKS(500) +#define TASKDLYMS pdMS_TO_TICKS(100) #define mainQUEUE_LENGTH (1) static void prvSetupHardware(void); @@ -148,7 +148,7 @@ void start_task1(void* pvParameters) printf("Enter to task_1\r\n"); while (1) { printf("task1 is running %d.....\r\n", cnt++); - vTaskDelay(200); + vTaskDelay(TASKDLYMS); } } @@ -158,7 +158,7 @@ void start_task2(void* pvParameters) printf("Enter to task_2\r\n"); while (1) { printf("task2 is running %d.....\r\n", cnt++); - vTaskDelay(200); + vTaskDelay(TASKDLYMS); } } @@ -169,6 +169,12 @@ static void vExampleTimerCallback(TimerHandle_t xTimer) execute periodically. */ static int cnt = 0; printf("timers Callback %d\r\n", cnt++); +#ifdef CFG_SIMULATION + if (cnt > 2) { + // directly exit if in nuclei internally simulation + SIMULATION_EXIT(0); + } +#endif } void vApplicationTickHook(void) diff --git a/examples/helloworld/README.md b/examples/helloworld/README.md index d3dc73b..7b701c2 100644 --- a/examples/helloworld/README.md +++ b/examples/helloworld/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/helloworld/platformio.ini b/examples/helloworld/platformio.ini index 8bdfadb..adef636 100644 --- a/examples/helloworld/platformio.ini +++ b/examples/helloworld/platformio.ini @@ -10,25 +10,29 @@ [platformio] description = A simple "Hello, World!" example to demonstrate printf and build environment. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [env] platform = nuclei framework = nuclei-sdk monitor_speed = 115200 -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval -board_build.download = ilm +board_build.download = flashxip +board_build.stdclib = newlib_nano -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar +board_build.stdclib = newlib_small -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite \ No newline at end of file diff --git a/examples/helloworld/src/main.c b/examples/helloworld/src/main.c index a28f7fa..1834514 100644 --- a/examples/helloworld/src/main.c +++ b/examples/helloworld/src/main.c @@ -83,17 +83,34 @@ void print_misa(void) printf("MISA: RV%s\r\n", misa_chars); } +#ifndef CFG_SIMULATION +#define RUN_LOOPS 20 +#else +#define RUN_LOOPS 5 +#endif + int main(void) { - srand(__get_rv_cycle() | __get_rv_instret() | __RV_CSR_READ(CSR_MCYCLE)); - uint32_t rval = rand(); - rv_csr_t misa = __RV_CSR_READ(CSR_MISA); + uint32_t rval, seed; + unsigned long hartid, clusterid; + rv_csr_t misa; + + // get hart id of current cluster + hartid = __get_hart_id(); + clusterid = __get_cluster_id(); + misa = __RV_CSR_READ(CSR_MISA); - printf("MISA: 0x%lx\r\n", misa); + printf("Cluster %lu, Hart %lu, MISA: 0x%lx\r\n", clusterid, hartid, misa); print_misa(); - for (int i = 0; i < 20; i ++) { - printf("%d: Hello World From Nuclei RISC-V Processor!\r\n", i); + // Generate random value with seed + seed = (uint32_t)(__get_rv_cycle() | __get_rv_instret() | __RV_CSR_READ(CSR_MCYCLE)); + srand(seed); + rval = rand(); + printf("Got rand integer %d using seed %d.\r\n", seed, rval); + + for (unsigned long i = 0; i < RUN_LOOPS; i ++) { + printf("%lu: Hello World From Nuclei RISC-V Processor!\r\n", i); } return 0; diff --git a/examples/rtthread_demo/README.md b/examples/rtthread_demo/README.md index cb594c2..229b70e 100644 --- a/examples/rtthread_demo/README.md +++ b/examples/rtthread_demo/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/rtthread_demo/platformio.ini b/examples/rtthread_demo/platformio.ini index eede5a4..dd79448 100644 --- a/examples/rtthread_demo/platformio.ini +++ b/examples/rtthread_demo/platformio.ini @@ -11,6 +11,8 @@ [platformio] description = A simple RT-Thread demo to demonstrate RT-Thread usage and build environment. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [env] platform = nuclei @@ -21,20 +23,28 @@ build_unflags = -Os build_flags = -O3 debug_build_flags = -O3 -g -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval board_build.download = ilm -board_build.core = n305 +board_build.core = n307 +board_build.stdclib = newlib_small -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = sram +board_build.sysclk = 48000000 +board_build.clksrc = irc16m + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite \ No newline at end of file diff --git a/examples/rtthread_msh/README.md b/examples/rtthread_msh/README.md index cb8d415..d05e159 100644 --- a/examples/rtthread_msh/README.md +++ b/examples/rtthread_msh/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/rtthread_msh/platformio.ini b/examples/rtthread_msh/platformio.ini index 21050a9..22da7c5 100644 --- a/examples/rtthread_msh/platformio.ini +++ b/examples/rtthread_msh/platformio.ini @@ -21,20 +21,25 @@ board_build.rtthread_msh = 1 build_unflags = -Os build_flags = -O3 -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval board_build.download = ilm -board_build.core = n305 +board_build.core = n900fd -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = sram + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite diff --git a/examples/smphello/.gitignore b/examples/smphello/.gitignore new file mode 100644 index 0000000..03f4a3c --- /dev/null +++ b/examples/smphello/.gitignore @@ -0,0 +1 @@ +.pio diff --git a/examples/smphello/README.md b/examples/smphello/README.md new file mode 100644 index 0000000..de50c15 --- /dev/null +++ b/examples/smphello/README.md @@ -0,0 +1,28 @@ +How to build PlatformIO based project +===================================== + +1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +2. Download [development platform with examples](https://github.com/Nuclei-Software/platform-nuclei/archive/develop.zip) +3. Extract ZIP archive +4. Run these commands: + +```shell +# Change directory to example +$ cd platform-nuclei/examples/smphello + +# Build project +$ pio run + +# required ux900fd 4c version +# Upload firmware +$ pio run --target upload + +# Build specific environment +$ pio run -e nuclei_fpga_eval + +# Upload firmware for the specific environment +$ pio run -e nuclei_fpga_eval --target upload + +# Clean build files +$ pio run --target clean +``` diff --git a/examples/smphello/include/README b/examples/smphello/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/examples/smphello/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/smphello/lib/README b/examples/smphello/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/examples/smphello/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/smphello/platformio.ini b/examples/smphello/platformio.ini new file mode 100644 index 0000000..6ee1871 --- /dev/null +++ b/examples/smphello/platformio.ini @@ -0,0 +1,27 @@ +; PlatformIO Project Configuration File +; +; Build options: build flags, source filter, extra scripting +; Upload options: custom port, speed and extra flags +; Library options: dependencies, extra library storages +; +; Please visit documentation for the other options and examples +; http://docs.platformio.org/page/projectconf.html + +[platformio] +description = + A simple smp helloworld to demonstrate smp feature of Nuclei Processors. + +[env] +platform = nuclei +framework = nuclei-sdk +monitor_speed = 115200 + +[env:nuclei_fpga_eval] +board = nuclei_fpga_eval +board_build.core = nx900f +board_build.download = sram +board_build.smp = 4 +board_build.stacksz = 4k +board_build.heapsz = 2k +board_build.boot_hartid = 1 + diff --git a/examples/smphello/src/main.c b/examples/smphello/src/main.c new file mode 100644 index 0000000..60f2a25 --- /dev/null +++ b/examples/smphello/src/main.c @@ -0,0 +1,123 @@ +#include +#include "nuclei_sdk_soc.h" + +#if !defined(__riscv_atomic) +#error "RVA(atomic) extension is required for SMP" +#endif + +#if !defined(SMP_CPU_CNT) +#error "SMP_CPU_CNT macro is not defined, please set SMP_CPU_CNT to integer value > 1" +#endif + +typedef struct { + uint32_t state; +} spinlock; + +spinlock lock; +volatile uint32_t lock_ready = 0; +volatile uint32_t cpu_count = 0; +volatile uint32_t finished = 0; + +// comment SPINLOCK_CAS to use AMOSWAP as spinlock +#define SPINLOCK_CAS + +__STATIC_FORCEINLINE void spinlock_init(spinlock *lock) +{ + lock->state = 0; +} + +__STATIC_FORCEINLINE void spinlock_lock(spinlock *lock) +{ + uint32_t old; + uint32_t backoff = 10; + do { +#ifndef SPINLOCK_CAS + // Use amoswap as spinlock + old = __AMOSWAP_W((&(lock->state)), 1); +#else + // use lr.w & sc.w to do CAS as spinlock + old = __CAS_W((&(lock->state)), 0, 1); +#endif + if (old == 0) { + break; + } + for (volatile int i = 0; i < backoff; i ++) { + __NOP(); + } + backoff += 10; + } while (1); +} + +__STATIC_FORCEINLINE void spinlock_unlock(spinlock *lock) +{ + lock->state = 0; +} + +int boot_hart_main(unsigned long hartid); +int other_harts_main(unsigned long hartid); +int main(void); + +/* Reimplementation of smp_main for multi-harts */ +int smp_main(void) +{ + return main(); +} + +int main(void) +{ + int ret; + // get hart id in current cluster + unsigned long hartid = __get_hart_id(); + if (hartid == BOOT_HARTID) { // boot hart + spinlock_init(&lock); + lock_ready = 1; + finished = 0; + __SMP_RWMB(); + ret = boot_hart_main(hartid); + } else { // other harts + // wait for lock initialized + while (lock_ready == 0); + ret = other_harts_main(hartid); + } + return ret; +} + +int boot_hart_main(unsigned long hartid) +{ + volatile unsigned long waitcnt = 0; + spinlock_lock(&lock); + printf("Hello world from hart %lu\n", hartid); + cpu_count += 1; + spinlock_unlock(&lock); + // wait for all harts boot and print hello + while (cpu_count < SMP_CPU_CNT) { + waitcnt ++; + __NOP(); + // The waitcnt compare value need to be adjust according + // to cpu frequency + if (waitcnt >= SystemCoreClock) { + break; + } + } + if (cpu_count == SMP_CPU_CNT) { + printf("All harts boot successfully!\n"); + finished = 1; + return 0; + } else { + printf("Some harts boot failed, only %d/%d booted!\n", cpu_count, SMP_CPU_CNT); + return -1; + } +} + +int other_harts_main(unsigned long hartid) +{ + spinlock_lock(&lock); + printf("Hello world from hart %lu\n", hartid); + cpu_count += 1; + spinlock_unlock(&lock); + // wait for all harts boot and print hello + while (cpu_count < SMP_CPU_CNT); + // wait for boot hart to set finished flag + while (finished == 0); + return 0; +} diff --git a/examples/smphello/test/README b/examples/smphello/test/README new file mode 100644 index 0000000..df5066e --- /dev/null +++ b/examples/smphello/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html diff --git a/examples/threadx_demo/.gitignore b/examples/threadx_demo/.gitignore new file mode 100644 index 0000000..03f4a3c --- /dev/null +++ b/examples/threadx_demo/.gitignore @@ -0,0 +1 @@ +.pio diff --git a/examples/threadx_demo/README.md b/examples/threadx_demo/README.md new file mode 100644 index 0000000..5510856 --- /dev/null +++ b/examples/threadx_demo/README.md @@ -0,0 +1,27 @@ +How to build PlatformIO based project +===================================== + +1. [Install PlatformIO Core](http://docs.platformio.org/page/core.html) +2. Download [development platform with examples](https://github.com/Nuclei-Software/platform-nuclei/archive/develop.zip) +3. Extract ZIP archive +4. Run these commands: + +```shell +# Change directory to example +$ cd platform-nuclei/examples/threadx_demo + +# Build project +$ pio run + +# Upload firmware +$ pio run --target upload + +# Build specific environment +$ pio run -e gd32vf103v_rvstar + +# Upload firmware for the specific environment +$ pio run -e gd32vf103v_rvstar --target upload + +# Clean build files +$ pio run --target clean +``` diff --git a/examples/threadx_demo/include/README b/examples/threadx_demo/include/README new file mode 100644 index 0000000..194dcd4 --- /dev/null +++ b/examples/threadx_demo/include/README @@ -0,0 +1,39 @@ + +This directory is intended for project header files. + +A header file is a file containing C declarations and macro definitions +to be shared between several project source files. You request the use of a +header file in your project source file (C, C++, etc) located in `src` folder +by including it, with the C preprocessing directive `#include'. + +```src/main.c + +#include "header.h" + +int main (void) +{ + ... +} +``` + +Including a header file produces the same results as copying the header file +into each source file that needs it. Such copying would be time-consuming +and error-prone. With a header file, the related declarations appear +in only one place. If they need to be changed, they can be changed in one +place, and programs that include the header file will automatically use the +new version when next recompiled. The header file eliminates the labor of +finding and changing all the copies as well as the risk that a failure to +find one copy will result in inconsistencies within a program. + +In C, the usual convention is to give header files names that end with `.h'. +It is most portable to use only letters, digits, dashes, and underscores in +header file names, and at most one dot. + +Read more about using header files in official GCC documentation: + +* Include Syntax +* Include Operation +* Once-Only Headers +* Computed Includes + +https://gcc.gnu.org/onlinedocs/cpp/Header-Files.html diff --git a/examples/threadx_demo/lib/README b/examples/threadx_demo/lib/README new file mode 100644 index 0000000..6debab1 --- /dev/null +++ b/examples/threadx_demo/lib/README @@ -0,0 +1,46 @@ + +This directory is intended for project specific (private) libraries. +PlatformIO will compile them to static libraries and link into executable file. + +The source code of each library should be placed in a an own separate directory +("lib/your_library_name/[here are source files]"). + +For example, see a structure of the following two libraries `Foo` and `Bar`: + +|--lib +| | +| |--Bar +| | |--docs +| | |--examples +| | |--src +| | |- Bar.c +| | |- Bar.h +| | |- library.json (optional, custom build options, etc) https://docs.platformio.org/page/librarymanager/config.html +| | +| |--Foo +| | |- Foo.c +| | |- Foo.h +| | +| |- README --> THIS FILE +| +|- platformio.ini +|--src + |- main.c + +and a contents of `src/main.c`: +``` +#include +#include + +int main (void) +{ + ... +} + +``` + +PlatformIO Library Dependency Finder will find automatically dependent +libraries scanning project source files. + +More information about PlatformIO Library Dependency Finder +- https://docs.platformio.org/page/librarymanager/ldf.html diff --git a/examples/threadx_demo/platformio.ini b/examples/threadx_demo/platformio.ini new file mode 100644 index 0000000..a16a6ea --- /dev/null +++ b/examples/threadx_demo/platformio.ini @@ -0,0 +1,47 @@ +;PlatformIO Project Configuration File +; +; Build options: build flags, source filter +; Upload options: custom upload port, speed and extra flags +; Library options: dependencies, extra library storages +; Advanced options: extra scripting +; +; Please visit documentation for the other options and examples +; https://docs.platformio.org/page/projectconf.html + +[platformio] +description = + A simple ThreadX demo to demonstrate ThreadX usage and build environment. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval + +[env] +platform = nuclei +framework = nuclei-sdk +monitor_speed = 115200 +board_build.rtos = threadx +build_unflags = -Os +build_flags = -O2 -DTX_INCLUDE_USER_DEFINE_FILE + +[env:nuclei_fpga_eval] +board = nuclei_fpga_eval +board_build.download = ilm +board_build.core = n300 +board_build.arch_ext = _zba_zbb_zbc_zbs + +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = sram + +[env:gd32vf103v_rvstar] +board = gd32vf103v_rvstar + +[env:gd32vf103v_eval] +board = gd32vf103v_eval + +[env:gd32vf103c_longan_nano] +board = gd32vf103c_longan_nano + +[env:gd32vf103c_longan_nano_lite] +board = gd32vf103c_longan_nano +board_build.variant = lite diff --git a/examples/threadx_demo/src/main.c b/examples/threadx_demo/src/main.c new file mode 100644 index 0000000..db91490 --- /dev/null +++ b/examples/threadx_demo/src/main.c @@ -0,0 +1,410 @@ +/* This is a small demo of the high-performance ThreadX kernel. It includes examples of eight + threads of different priorities, using a message queue, semaphore, mutex, event flags group, + byte pool, and block pool. */ +#include "tx_api.h" +#include + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 10240 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + +// NOTE don't turn on all the debug, it really cost time +// just turn on one and keep others close to see whether thread is running + +//#define DEBUG_THREAD_0 +//#define DEBUG_THREAD_1 +//#define DEBUG_THREAD_2 +//#define DEBUG_THREAD_3_4 +//#define DEBUG_THREAD_5 + +#define DEBUG_THREAD_6_7 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD thread_0; +TX_THREAD thread_1; +TX_THREAD thread_2; +TX_THREAD thread_3; +TX_THREAD thread_4; +TX_THREAD thread_5; +TX_THREAD thread_6; +TX_THREAD thread_7; +TX_QUEUE queue_0; +TX_SEMAPHORE semaphore_0; +TX_MUTEX mutex_0; +TX_EVENT_FLAGS_GROUP event_flags_0; +TX_BYTE_POOL byte_pool_0; +TX_BLOCK_POOL block_pool_0; +// This is an memory area used by ThreadX to allocate for task stacks and etc +UCHAR memory_area[DEMO_BYTE_POOL_SIZE]; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; + + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ +// NOTE: TODO: first_unused_memory is not used here, since our port don't create a memory for you, you need +// to prepare it by yourself like memory_area here +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = TX_NULL; + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(&thread_0, "thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(&thread_1, "thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_2, "thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(&thread_3, "thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_4, "thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(&thread_5, "thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(&thread_6, "thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(&thread_7, "thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(&queue_0, "queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(&semaphore_0, "semaphore 0", 1); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(&event_flags_0, "event flags 0"); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(&mutex_0, "mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(&block_pool_0, "block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(&block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(&event_flags_0, 0x1, TX_OR); + +#ifdef DEBUG_THREAD_0 + printf("thread 0 is running %lu\n", thread_0_counter); +#endif + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(&queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; +#ifdef DEBUG_THREAD_1 + printf("thread 1 is running %lu, msg sent %lu\n", thread_1_counter, thread_1_messages_sent); +#endif + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(&queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + +#ifdef DEBUG_THREAD_2 + printf("thread 2 is running %lu, msg recv %lu\n", thread_2_counter, thread_2_messages_received); +#endif + + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(&semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(&semaphore_0); + +#ifdef DEBUG_THREAD_3_4 + printf("thread 3_4 is running, current is %lu, thread 3 counter %lu, thread 4 counter %lu\n", thread_input, thread_3_counter, thread_4_counter); +#endif + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(&event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + +#ifdef DEBUG_THREAD_5 + printf("thread 5 is running %lu\n", thread_5_counter); +#endif + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(&mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(&mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(&mutex_0); + +#ifdef DEBUG_THREAD_6_7 + printf("thread 6_7 is running, current is %lu, thread 6 counter %lu, thread 7 counter %lu\n", thread_input, thread_6_counter, thread_7_counter); +#endif + /* Check status. */ + if (status != TX_SUCCESS) + break; + +#ifdef CFG_SIMULATION + if (thread_7_counter > 2) { + // directly exit if in nuclei internally simulation + SIMULATION_EXIT(0); + } +#endif + } +} diff --git a/examples/threadx_demo/src/tx_user.h b/examples/threadx_demo/src/tx_user.h new file mode 100644 index 0000000..b071752 --- /dev/null +++ b/examples/threadx_demo/src/tx_user.h @@ -0,0 +1,325 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_user.h PORTABLE C */ +/* 6.3.0 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring ThreadX in specific */ +/* ways. This file will have an effect only if the application and */ +/* ThreadX library are built with TX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building ThreadX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 Yuxin Zhou Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 Scott Larson Modified comment(s), */ +/* added option to remove */ +/* FileX pointer, */ +/* resulting in version 6.1.5 */ +/* 06-02-2021 Scott Larson Added options for multiple */ +/* block pool search & delay, */ +/* resulting in version 6.1.7 */ +/* 10-15-2021 Yuxin Zhou Modified comment(s), added */ +/* user-configurable symbol */ +/* TX_TIMER_TICKS_PER_SECOND */ +/* resulting in version 6.1.9 */ +/* 04-25-2022 Wenhui Xie Modified comment(s), */ +/* optimized the definition of */ +/* TX_TIMER_TICKS_PER_SECOND, */ +/* resulting in version 6.1.11 */ +/* 10-31-2023 Xiuwen Cai Modified comment(s), */ +/* added option for random */ +/* number stack filling, */ +/* resulting in version 6.3.0 */ +/* */ +/**************************************************************************/ + +#ifndef TX_USER_H +#define TX_USER_H + + +/* Define various build options for the ThreadX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. + + For maximum speed, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + TX_REACTIVATE_INLINE + TX_DISABLE_STACK_FILLING + TX_INLINE_THREAD_RESUME_SUSPEND + + For minimum size, the following should be defined: + + TX_MAX_PRIORITIES 32 + TX_DISABLE_PREEMPTION_THRESHOLD + TX_DISABLE_REDUNDANT_CLEARING + TX_DISABLE_NOTIFY_CALLBACKS + TX_NO_FILEX_POINTER + TX_NOT_INTERRUPTABLE + TX_TIMER_PROCESS_IN_ISR + + Of course, many of these defines reduce functionality and/or change the behavior of the + system in ways that may not be worth the trade-off. For example, the TX_TIMER_PROCESS_IN_ISR + results in faster and smaller code, however, it increases the amount of processing in the ISR. + In addition, some services that are available in timers are not available from ISRs and will + therefore return an error if this option is used. This may or may not be desirable for a + given application. */ + + +/* Override various options with default values already assigned in tx_port.h. Please also refer + to tx_port.h for descriptions on each of these options. */ + +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK 512 +/* +#define TX_MAX_PRIORITIES 32 +#define TX_MINIMUM_STACK ???? +// Added by Nuclei used to allocated a memory in bytes for ThreadX +#define TX_HEAP_SIZE ???? +#define TX_THREAD_USER_EXTENSION ???? +#define TX_TIMER_THREAD_STACK_SIZE ???? +#define TX_TIMER_THREAD_PRIORITY ???? +*/ + +/* Define the common timer tick reference for use by other middleware components. The default + value is 10ms (i.e. 100 ticks, defined in tx_api.h), but may be replaced by a port-specific + version in tx_port.h or here. + Note: the actual hardware timer value may need to be changed (usually in tx_initialize_low_level). */ + +#define TX_TIMER_TICKS_PER_SECOND (100UL) +/* +#define TX_TIMER_TICKS_PER_SECOND (100UL) +*/ + +/* Determine if there is a FileX pointer in the thread control block. + By default, the pointer is there for legacy/backwards compatibility. + The pointer must also be there for applications using FileX. + Define this to save space in the thread control block. +*/ + +/* +#define TX_NO_FILEX_POINTER +*/ + +/* Determine if timer expirations (application timers, timeouts, and tx_thread_sleep calls + should be processed within the a system timer thread or directly in the timer ISR. + By default, the timer thread is used. When the following is defined, the timer expiration + processing is done directly from the timer ISR, thereby eliminating the timer thread control + block, stack, and context switching to activate it. */ + +/* +#define TX_TIMER_PROCESS_IN_ISR +*/ + +/* Determine if in-line timer reactivation should be used within the timer expiration processing. + By default, this is disabled and a function call is used. When the following is defined, + reactivating is performed in-line resulting in faster timer processing but slightly larger + code size. */ + +//#define TX_REACTIVATE_INLINE +/* +#define TX_REACTIVATE_INLINE +*/ + +/* Determine is stack filling is enabled. By default, ThreadX stack filling is enabled, + which places an 0xEF pattern in each byte of each thread's stack. This is used by + debuggers with ThreadX-awareness and by the ThreadX run-time stack checking feature. */ + +//#define TX_DISABLE_STACK_FILLING +/* +#define TX_DISABLE_STACK_FILLING +*/ + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +/* +#define TX_ENABLE_STACK_CHECKING +*/ + +/* Determine if random number is used for stack filling. By default, ThreadX uses a fixed + pattern for stack filling. When the following is defined, ThreadX uses a random number + for stack filling. This is effective only when TX_ENABLE_STACK_CHECKING is defined. */ + +/* +#define TX_ENABLE_RANDOM_NUMBER_STACK_FILLING +*/ + +/* Determine if preemption-threshold should be disabled. By default, preemption-threshold is + enabled. If the application does not use preemption-threshold, it may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_PREEMPTION_THRESHOLD +*/ + +/* Determine if global ThreadX variables should be cleared. If the compiler startup code clears + the .bss section prior to ThreadX running, the define can be used to eliminate unnecessary + clearing of ThreadX global variables. */ + +/* +#define TX_DISABLE_REDUNDANT_CLEARING +*/ + +/* Determine if no timer processing is required. This option will help eliminate the timer + processing when not needed. The user will also have to comment out the call to + tx_timer_interrupt, which is typically made from assembly language in + tx_initialize_low_level. Note: if TX_NO_TIMER is used, the define TX_TIMER_PROCESS_IN_ISR + must also be used and tx_timer_initialize must be removed from ThreadX library. */ + +/* +#define TX_NO_TIMER +#ifndef TX_TIMER_PROCESS_IN_ISR +#define TX_TIMER_PROCESS_IN_ISR +#endif +*/ + +/* Determine if the notify callback option should be disabled. By default, notify callbacks are + enabled. If the application does not use notify callbacks, they may be disabled to reduce + code size and improve performance. */ + +/* +#define TX_DISABLE_NOTIFY_CALLBACKS +*/ + + +/* Determine if the tx_thread_resume and tx_thread_suspend services should have their internal + code in-line. This results in a larger image, but improves the performance of the thread + resume and suspend services. */ + +/* +#define TX_INLINE_THREAD_RESUME_SUSPEND +*/ + + +/* Determine if the internal ThreadX code is non-interruptable. This results in smaller code + size and less processing overhead, but increases the interrupt lockout time. */ + +/* +#define TX_NOT_INTERRUPTABLE +*/ + + +/* Determine if the trace event logging code should be enabled. This causes slight increases in + code size and overhead, but provides the ability to generate system trace information which + is available for viewing in TraceX. */ + +/* +#define TX_ENABLE_EVENT_TRACE +*/ + + +/* Determine if block pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various block pool performance information. */ + +/* +#define TX_BLOCK_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if byte pool performance gathering is required by the application. When the following is + defined, ThreadX gathers various byte pool performance information. */ + +/* +#define TX_BYTE_POOL_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if event flags performance gathering is required by the application. When the following is + defined, ThreadX gathers various event flags performance information. */ + +/* +#define TX_EVENT_FLAGS_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if mutex performance gathering is required by the application. When the following is + defined, ThreadX gathers various mutex performance information. */ + +/* +#define TX_MUTEX_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if queue performance gathering is required by the application. When the following is + defined, ThreadX gathers various queue performance information. */ + +/* +#define TX_QUEUE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if semaphore performance gathering is required by the application. When the following is + defined, ThreadX gathers various semaphore performance information. */ + +/* +#define TX_SEMAPHORE_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if thread performance gathering is required by the application. When the following is + defined, ThreadX gathers various thread performance information. */ + +/* +#define TX_THREAD_ENABLE_PERFORMANCE_INFO +*/ + +/* Determine if timer performance gathering is required by the application. When the following is + defined, ThreadX gathers various timer performance information. */ + +/* +#define TX_TIMER_ENABLE_PERFORMANCE_INFO +*/ + +/* Override options for byte pool searches of multiple blocks. */ + +/* +#define TX_BYTE_POOL_MULTIPLE_BLOCK_SEARCH 20 +*/ + +/* Override options for byte pool search delay to avoid thrashing. */ + +/* +#define TX_BYTE_POOL_DELAY_VALUE 3 +*/ + +#endif + diff --git a/examples/threadx_demo/test/README b/examples/threadx_demo/test/README new file mode 100644 index 0000000..df5066e --- /dev/null +++ b/examples/threadx_demo/test/README @@ -0,0 +1,11 @@ + +This directory is intended for PIO Unit Testing and project tests. + +Unit Testing is a software testing method by which individual units of +source code, sets of one or more MCU program modules together with associated +control data, usage procedures, and operating procedures, are tested to +determine whether they are fit for use. Unit testing finds problems early +in the development cycle. + +More information about PIO Unit Testing: +- https://docs.platformio.org/page/plus/unit-testing.html diff --git a/examples/ucosii_demo/README.md b/examples/ucosii_demo/README.md index 01c5b71..a8a4556 100644 --- a/examples/ucosii_demo/README.md +++ b/examples/ucosii_demo/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/ucosii_demo/platformio.ini b/examples/ucosii_demo/platformio.ini index 45e6649..539eca5 100644 --- a/examples/ucosii_demo/platformio.ini +++ b/examples/ucosii_demo/platformio.ini @@ -11,6 +11,8 @@ [platformio] description = A simple UCOSII demo to demonstrate UCOSII usage and build environment. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [env] platform = nuclei @@ -18,18 +20,27 @@ framework = nuclei-sdk monitor_speed = 115200 board_build.rtos = ucosii -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval +board_build.download = ilm +board_build.core = n200 -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.core = n300f +board_build.arch_ext = +board_build.download = sram + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite diff --git a/examples/ucosii_demo/src/main.c b/examples/ucosii_demo/src/main.c index 41aa140..b3a55f4 100644 --- a/examples/ucosii_demo/src/main.c +++ b/examples/ucosii_demo/src/main.c @@ -29,7 +29,7 @@ void task1(void* args) for (;;) { cnt++; printf("task1 is running... %d\r\n", cnt); - OSTimeDlyHMSM(0, 0, 2, 0); + OSTimeDlyHMSM(0, 0, 0, 500); } } @@ -39,7 +39,7 @@ void task2(void* args) for (;;) { cnt++; printf("task2 is running... %d\r\n", cnt); - OSTimeDlyHMSM(0, 0, 1, 0); + OSTimeDlyHMSM(0, 0, 0, 250); } } @@ -49,7 +49,13 @@ void task3(void* args) for (;;) { cnt++; printf("task3 is running... %d\r\n", cnt); - OSTimeDlyHMSM(0, 0, 1, 0); + OSTimeDlyHMSM(0, 0, 0, 250); +#ifdef CFG_SIMULATION + if (cnt > 2) { + // directly exit if in nuclei internally simulation + SIMULATION_EXIT(0); + } +#endif } } @@ -68,7 +74,7 @@ int main(void) prvSetupHardware(); OSInit(); OSTaskCreate(start_task, NULL, &start_stk[STK_LEN - 1], TASK_START_PRIO); - printf("create start task success \r\n"); + printf("create start task success\r\n"); OSStart(); while (1) { } diff --git a/examples/whetstone/README.md b/examples/whetstone/README.md index 866f1d7..fc7ce0a 100644 --- a/examples/whetstone/README.md +++ b/examples/whetstone/README.md @@ -17,10 +17,10 @@ $ pio run $ pio run --target upload # Build specific environment -$ pio run -e nuclei-gd32vf103v_rvstar +$ pio run -e gd32vf103v_rvstar # Upload firmware for the specific environment -$ pio run -e nuclei-gd32vf103v_rvstar --target upload +$ pio run -e gd32vf103v_rvstar --target upload # Clean build files $ pio run --target clean diff --git a/examples/whetstone/platformio.ini b/examples/whetstone/platformio.ini index 857373e..0ec4a05 100644 --- a/examples/whetstone/platformio.ini +++ b/examples/whetstone/platformio.ini @@ -10,6 +10,8 @@ [platformio] description = Whestone benchmark. +# uncomment below and select default environment +; default_envs = nuclei_fpga_eval [common] compile_flags = -O3 -funroll-loops -fsingle-precision-constant @@ -22,20 +24,26 @@ monitor_speed = 115200 build_unflags = -Os build_flags = ${common.compile_flags} -[env:nuclei-nuclei_fpga_eval] +[env:nuclei_fpga_eval] board = nuclei_fpga_eval # Changed to use ilm download mode board_build.download = ilm +board_build.core = n300f -[env:nuclei-gd32vf103v_rvstar] +[env:gd32vw553h_eval] +board = gd32vw553h_eval +# Changed to use sram download mode +board_build.download = sram + +[env:gd32vf103v_rvstar] board = gd32vf103v_rvstar -[env:nuclei-gd32vf103v_eval] +[env:gd32vf103v_eval] board = gd32vf103v_eval -[env:nuclei-gd32vf103c_longan_nano] +[env:gd32vf103c_longan_nano] board = gd32vf103c_longan_nano -[env:nuclei-gd32vf103c_longan_nano_lite] +[env:gd32vf103c_longan_nano_lite] board = gd32vf103c_longan_nano board_build.variant = lite \ No newline at end of file diff --git a/examples/whetstone/src/config.h b/examples/whetstone/src/config.h index f5f2709..619274e 100644 --- a/examples/whetstone/src/config.h +++ b/examples/whetstone/src/config.h @@ -2,16 +2,11 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ - - -#define CFG_SIMU 0 - /* Predefined macro __riscv_flen is equal to: * 64: if D toolchain is used * 32: if F toolchain is used */ - -#if __riscv_flen == 64 +#if defined(__riscv_flen) && __riscv_flen == 64 #define SPDP double #define Precision "Double" #else //__riscv_flen == 32 @@ -26,5 +21,4 @@ #define log logf #endif - #endif diff --git a/examples/whetstone/src/cpuidc.c b/examples/whetstone/src/cpuidc.c index 92fdae0..4369c8c 100644 --- a/examples/whetstone/src/cpuidc.c +++ b/examples/whetstone/src/cpuidc.c @@ -1,7 +1,7 @@ #include +#include "nuclei_sdk_soc.h" #include "cpuidh.h" #include "config.h" -#include "nuclei_sdk_soc.h" volatile SPDP theseSecs = 0.0; volatile SPDP startSecs = 0.0; @@ -9,7 +9,11 @@ volatile SPDP secs; SPDP time() { +#if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) return (SPDP) SysTimer_GetLoadValue() / SOC_TIMER_FREQ; +#else +#error "This example require CPU System Timer feature" +#endif } void getSecs() diff --git a/examples/whetstone/src/whets.c b/examples/whetstone/src/whets.c index 45de2d0..4ff4752 100644 --- a/examples/whetstone/src/whets.c +++ b/examples/whetstone/src/whets.c @@ -178,11 +178,12 @@ #include #include #include -#include "stdatomic.h" +// zcc report error stdatomic.h:201:17: error: unknown type name 'int_least8_t'; did you mean '__int_least8_t'? +//#include "stdatomic.h" +#include "nuclei_sdk_soc.h" #include "config.h" #include "cpuidh.h" -#include "nuclei_sdk_soc.h" /*PRECISION PRECISION PRECISION PRECISION PRECISION PRECISION PRECISION*/ @@ -192,18 +193,37 @@ void whetstones(long xtra, long x100, int calibrate); void pa(SPDP e[4], SPDP t, SPDP t2); void po(SPDP e1[4], long j, long k, long l); void p3(SPDP* x, SPDP* y, SPDP* z, SPDP t, SPDP t1, SPDP t2); -void pout(char title[22], float ops, int type, SPDP checknum, SPDP time, +void pout(char *title, float ops, int type, SPDP checknum, SPDP time, int calibrate, int section); static SPDP loop_time[9]; static SPDP loop_mops[9]; static SPDP loop_mflops[9]; static SPDP TimeUsed; -static SPDP mwips; -static char headings[9][18]; +static SPDP mwips, mwips_mhz; +static char headings[9][22]; static SPDP Check; static SPDP results[9]; -int main() + +static uint64_t start_cycle, end_cycle, used_cycle; +static uint64_t start_instret, end_instret, used_instret; + +/* Only support dec number < 1000 */ +static char *dec2str(uint32_t val) +{ + static char str[4]; + val = val % 1000; + int decnum = 100; + for (int i = 0; i < 3; i ++) { + str[i] = val / decnum + '0'; + val = val % decnum; + decnum = decnum / 10; + } + str[3] = '\0'; + return str; +} + +int main(void) { int count = 10, calibrate = 1; long xtra = 1; @@ -212,7 +232,7 @@ int main() #if CFG_SIMULATION int duration = 1; #else - int duration = 10; + int duration = 3; #endif printf("\n"); @@ -229,10 +249,10 @@ int main() calibrate++; count--; -#if CFG_SIMU +#if CFG_SIMULATION if (TimeUsed > 0.02) #else - if (TimeUsed > 2.0) + if (TimeUsed > 0.2) #endif { count = 0; @@ -250,7 +270,7 @@ int main() calibrate = 0; - printf("\nUse %d passes (x 100)\n", xtra); + printf("\nUse %u passes (x 100)\n", (uint32_t)xtra); printf("\n %s Precision C/C++ Whetstone Benchmark", Precision); #ifdef PRECOMP @@ -263,9 +283,20 @@ int main() printf("\nLoop content Result MFLOPS " " MOPS Seconds\n\n"); + // reset instret and cycle + __set_rv_cycle(0); + __set_rv_instret(0); + start_cycle = __get_rv_cycle(); + start_instret = __get_rv_instret(); + TimeUsed = 0; whetstones(xtra, x100, calibrate); + end_cycle = __get_rv_cycle(); + end_instret = __get_rv_instret(); + used_cycle = end_cycle - start_cycle; + used_instret = end_instret - start_instret; + printf("\nMWIPS "); if (TimeUsed > 0) { mwips = (float)(xtra) * (float)(x100) / (10 * TimeUsed); @@ -277,9 +308,23 @@ int main() printf("\nMWIPS/MHz "); - printf("%39.3f%19.3f\n\n", mwips / SystemCoreClock * 1000000, TimeUsed); + mwips_mhz = mwips / SystemCoreClock * 1000000; + printf("%39.3f%19.3f\n\n", mwips_mhz, TimeUsed); + + uint32_t whet_mwips = (uint32_t)(mwips_mhz * 1000); + char *pstr = dec2str(whet_mwips); + printf("\nCSV, Benchmark, MWIPS/MHz\n"); + printf("CSV, Whetstone, %u.%s\n", (unsigned int)(whet_mwips/1000), pstr); + + float f_ipc = (((float)used_instret / used_cycle)); + uint32_t i_ipc = (uint32_t)(f_ipc * 1000); + pstr = dec2str(i_ipc); + + printf("IPC = Instret/Cycle = %u/%u = %u.%s\n", (unsigned int)used_instret, (unsigned int)used_cycle, (unsigned int)(i_ipc/1000), pstr); + if (Check == 0) { - printf("Wrong answer "); + printf("Wrong answer \n"); + return -1; } return 0; @@ -506,7 +551,7 @@ void p3(SPDP* x, SPDP* y, SPDP* z, SPDP t, SPDP t1, SPDP t2) return; } -void pout(char title[18], float ops, int type, SPDP checknum, SPDP time, +void pout(char *title, float ops, int type, SPDP checknum, SPDP time, int calibrate, int section) { SPDP mops, mflops; diff --git a/misc/svd/EVALSOC.svd b/misc/svd/EVALSOC.svd new file mode 100644 index 0000000..fb65e89 --- /dev/null +++ b/misc/svd/EVALSOC.svd @@ -0,0 +1,7154 @@ + + + Nuclei + Nuclei + evalsoc + Nuclei Evaluation SoC + + Nuclei Evaluation SoC using Nuclei N/NX Core + + + 8 + 32 + 32 + 0x00000000 + 0xFFFFFFFF + + + Evalsoc + little + + + + + + ECLIC + Enhanced Core Local Interrupt Controller + ECLIC + 0x18020000 + + 0x0 + 0xFFFF + registers + + + + CLICCFG + CLICCFG + cliccfg Register + 0x0 + 0x08 + read-write + 0x00 + + + NLBITS + NLBITS + 1 + 4 + + + + + CLICINFO + CLICINFO + clicinfo Register + 0x04 + 0x20 + read-only + 0x00000000 + + + NUM_INTERRUPT + NUM_INTERRUPT + 0 + 13 + + + VERSION + VERSION + 13 + 8 + + + CLICINTCTLBITS + CLICINTCTLBITS + 21 + 4 + + + + + MTH + MTH + MTH Register + 0x0b + 0x08 + read-write + 0x00 + + + MTH + MTH + 0 + 8 + + + + + CLICINTIP_0 + CLICINTIP_0 + clicintip Register + 0x1000 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_1 + CLICINTIP_1 + clicintip Register + 0x1004 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_2 + CLICINTIP_2 + clicintip Register + 0x1008 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_3 + CLICINTIP_3 + clicintip Register + 0x100C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_4 + CLICINTIP_4 + clicintip Register + 0x1010 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_5 + CLICINTIP_5 + clicintip Register + 0x1014 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_6 + CLICINTIP_6 + clicintip Register + 0x1018 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_7 + CLICINTIP_7 + clicintip Register + 0x101C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_8 + CLICINTIP_8 + clicintip Register + 0x1020 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_9 + CLICINTIP_9 + clicintip Register + 0x1024 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_10 + CLICINTIP_10 + clicintip Register + 0x1028 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_11 + CLICINTIP_11 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0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_74 + CLICINTIE_74 + clicintattr Register + 0x112A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_75 + CLICINTIE_75 + clicintattr Register + 0x112E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_76 + CLICINTIE_76 + clicintattr Register + 0x1132 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_77 + CLICINTIE_77 + clicintattr Register + 0x1136 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_78 + CLICINTIE_78 + clicintattr Register + 0x113A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_79 + CLICINTIE_79 + clicintattr Register + 0x113E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_80 + CLICINTIE_80 + clicintattr Register + 0x1142 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_81 + CLICINTIE_81 + clicintattr Register + 0x1146 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_82 + CLICINTIE_82 + clicintattr Register + 0x114A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_83 + CLICINTIE_83 + clicintattr Register + 0x114E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_84 + CLICINTIE_84 + clicintattr Register + 0x1152 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_85 + CLICINTIE_85 + clicintattr Register + 0x1156 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_86 + CLICINTIE_86 + clicintattr Register + 0x115A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + + CLICINTCTL_0 + CLICINTCTL_0 + clicintctl Register + 0x1003 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_1 + CLICINTCTL_1 + clicintctl Register + 0x1007 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_2 + CLICINTCTL_2 + clicintctl Register + 0x100B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_3 + CLICINTCTL_3 + clicintctl Register + 0x100F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_4 + CLICINTCTL_4 + clicintctl Register + 0x1013 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_5 + CLICINTCTL_5 + clicintctl Register + 0x1017 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_6 + CLICINTCTL_6 + clicintctl Register + 0x101B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_7 + CLICINTCTL_7 + clicintctl Register + 0x101F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_8 + CLICINTCTL_8 + clicintctl Register + 0x1023 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_9 + CLICINTCTL_9 + clicintctl Register + 0x1027 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_10 + CLICINTCTL_10 + clicintctl Register + 0x102B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_11 + CLICINTCTL_11 + clicintctl Register + 0x102F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_12 + CLICINTCTL_12 + clicintctl Register + 0x1033 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_13 + CLICINTCTL_13 + clicintctl Register + 0x1037 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_14 + CLICINTCTL_14 + clicintctl Register + 0x103B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_15 + CLICINTCTL_15 + clicintctl Register + 0x103F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_16 + CLICINTCTL_16 + clicintctl Register + 0x1043 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_17 + CLICINTCTL_17 + clicintctl Register + 0x1047 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_18 + CLICINTCTL_18 + clicintctl Register + 0x104B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_19 + CLICINTCTL_19 + clicintctl Register + 0x104F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_20 + CLICINTCTL_20 + clicintctl Register + 0x1053 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_21 + CLICINTCTL_21 + clicintctl Register + 0x1057 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_22 + CLICINTCTL_22 + clicintctl Register + 0x105B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_23 + CLICINTCTL_23 + clicintctl Register + 0x105F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_24 + CLICINTCTL_24 + clicintctl Register + 0x1063 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_25 + CLICINTCTL_25 + clicintctl Register + 0x1067 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_26 + CLICINTCTL_26 + clicintctl Register + 0x106B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_27 + CLICINTCTL_27 + clicintctl Register + 0x106F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_28 + CLICINTCTL_28 + clicintctl Register + 0x1073 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_29 + CLICINTCTL_29 + clicintctl Register + 0x1077 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_30 + CLICINTCTL_30 + clicintctl Register + 0x107B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_31 + CLICINTCTL_31 + clicintctl Register + 0x107F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_32 + CLICINTCTL_32 + clicintctl Register + 0x1083 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_33 + CLICINTCTL_33 + clicintctl Register + 0x1087 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_34 + CLICINTCTL_34 + clicintctl Register + 0x108B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_35 + CLICINTCTL_35 + clicintctl Register + 0x108F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_36 + CLICINTCTL_36 + clicintctl Register + 0x1093 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_37 + CLICINTCTL_37 + clicintctl Register + 0x1097 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_38 + CLICINTCTL_38 + clicintctl Register + 0x109B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_39 + CLICINTCTL_39 + clicintctl Register + 0x109F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_40 + CLICINTCTL_40 + clicintctl Register + 0x10A3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_41 + CLICINTCTL_41 + clicintctl Register + 0x10A7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_42 + CLICINTCTL_42 + clicintctl Register + 0x10AB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_43 + CLICINTCTL_43 + clicintctl Register + 0x10AF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_44 + CLICINTCTL_44 + clicintctl Register + 0x10B3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_45 + CLICINTCTL_45 + clicintctl Register + 0x10B7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_46 + CLICINTCTL_46 + clicintctl Register + 0x10BB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_47 + CLICINTCTL_47 + clicintctl Register + 0x10BF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_48 + CLICINTCTL_48 + clicintctl Register + 0x10C3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_49 + CLICINTCTL_49 + clicintctl Register + 0x10C7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_50 + CLICINTCTL_50 + clicintctl Register + 0x10CB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_51 + CLICINTCTL_51 + clicintctl Register + 0x10CF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_52 + CLICINTCTL_52 + clicintctl Register + 0x10D3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_53 + CLICINTCTL_53 + clicintctl Register + 0x10D7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_54 + CLICINTCTL_54 + clicintctl Register + 0x10DB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_55 + CLICINTCTL_55 + clicintctl Register + 0x10DF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_56 + CLICINTCTL_56 + clicintctl Register + 0x10E3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_57 + CLICINTCTL_57 + clicintctl Register + 0x10E7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_58 + CLICINTCTL_58 + clicintctl Register + 0x10EB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_59 + CLICINTCTL_59 + clicintctl Register + 0x10EF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_60 + CLICINTCTL_60 + clicintctl Register + 0x10F3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_61 + CLICINTCTL_61 + clicintctl Register + 0x10F7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_62 + CLICINTCTL_62 + clicintctl Register + 0x10FB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_63 + CLICINTCTL_63 + clicintctl Register + 0x10FF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_64 + CLICINTCTL_64 + clicintctl Register + 0x1103 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_65 + CLICINTCTL_65 + clicintctl Register + 0x1107 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_66 + CLICINTCTL_66 + clicintctl Register + 0x110B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_67 + CLICINTCTL_67 + clicintctl Register + 0x110F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_68 + CLICINTCTL_68 + clicintctl Register + 0x1113 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_69 + CLICINTCTL_69 + clicintctl Register + 0x1117 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_70 + CLICINTCTL_70 + clicintctl Register + 0x111B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_71 + CLICINTCTL_71 + clicintctl Register + 0x111F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_72 + CLICINTCTL_72 + clicintctl Register + 0x1123 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_73 + CLICINTCTL_73 + clicintctl Register + 0x1127 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_74 + CLICINTCTL_74 + clicintctl Register + 0x112B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_75 + CLICINTCTL_75 + clicintctl Register + 0x112F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_76 + CLICINTCTL_76 + clicintctl Register + 0x1133 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_77 + CLICINTCTL_77 + clicintctl Register + 0x1137 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_78 + CLICINTCTL_78 + clicintctl Register + 0x113B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_79 + CLICINTCTL_79 + clicintctl Register + 0x113F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_80 + CLICINTCTL_80 + clicintctl Register + 0x1143 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_81 + CLICINTCTL_81 + clicintctl Register + 0x1147 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_82 + CLICINTCTL_82 + clicintctl Register + 0x114B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_83 + CLICINTCTL_83 + clicintctl Register + 0x114F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_84 + CLICINTCTL_84 + clicintctl Register + 0x1153 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_85 + CLICINTCTL_85 + clicintctl Register + 0x1157 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_86 + CLICINTCTL_86 + clicintctl Register + 0x115B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + + + + MTIMER + System Timer. + 0x18030000 + TIMER + 32 + read-write + + + 0 + 0x10000 + registers + + + + + + MTIME_LO + Machine Timer Register Low. + 0x0 + + MTIME_HI + Machine Timer Register High. + 0x4 + + + + MTIMECMP_LO + Machine Timer Compare Register Low. + 0x8 + + + + MTIMECMP_HI + Machine Timer Compare Register High. + 0xC + + MSFTRST + Machine Timer Software Core Reset Register. + 0xFF0 + + MIMECTL + Machine Timer Control Register. + 0xFF8 + + MSIP + Machine Software Interrupt Pending Register. + 0xFFC + + + + + + GPIO0 + General purpose input/output controller. + 0x10012000 + GPIO + 32 + read-write + + + 0 + 0x1000 + registers + + + GPIO_0_IRQ8 + GPIO_1_IRQ9 + GPIO_2_IRQ10 + GPIO_3_IRQ11 + GPIO_4_IRQ12 + GPIO_5_IRQ13 + GPIO_6_IRQ14 + GPIO_7_IRQ15 + GPIO_8_IRQ16 + GPIO_9_IRQ17 + GPIO_10_IRQ18 + GPIO_11_IRQ19 + GPIO_12_IRQ20 + GPIO_12_IRQ21 + GPIO_14_IRQ22 + GPIO_14_IRQ23 + GPIO_16_IRQ24 + GPIO_17_IRQ25 + GPIO_18_IRQ26 + GPIO_19_IRQ27 + GPIO_20_IRQ28 + GPIO_21_IRQ29 + GPIO_22_IRQ30 + GPIO_23_IRQ31 + GPIO_24_IRQ32 + GPIO_25_IRQ33 + GPIO_26_IRQ34 + GPIO_27_IRQ35 + GPIO_28_IRQ36 + GPIO_28_IRQ37 + GPIO_30_IRQ38 + GPIO_31_IRQ39 + + + + VALUE + Pin value. + 0x000 + + PIN000 + PIN111 + PIN222 + PIN333 + PIN444 + PIN555 + PIN666 + PIN777 + PIN888 + PIN999 + PIN101010 + PIN111111 + PIN121212 + PIN131313 + PIN141414 + PIN151515 + PIN161616 + PIN171717 + PIN181818 + PIN191919 + PIN202020 + PIN212121 + PIN222222 + PIN232323 + PIN242424 + PIN252525 + PIN262626 + PIN272727 + PIN282828 + PIN292929 + PIN303030 + PIN313131 + + + + INPUT_EN + Pin input enable. + 0x004 + + + OUTPUT_EN + Pin output enable. + 0x008 + + + PORT + Output port value. + 0x00C + + + PULLUP + Internal Pull-Up enable. + 0x010 + + + DRIVE + Drive Strength. + 0x014 + + + RISE_INT_EN + Rise interrupt enable. + 0x018 + + + RISE_INT_PEMD + Rise interrupt pending. + 0x01C + + + FALL_INT_EN + Fall interrupt enable. + 0x020 + + + FALL_INT_PEND + Fall interrupt pending. + 0x024 + + + HIGH_INT_EN + High interrupt enable. + 0x028 + + + HIGH_INT_PEND + High interrupt pending. + 0x02C + + + LOW_INT_EN + Low interrupt enable. + 0x030 + + + LOW_INT_PEND + Low interrupt pending. + 0x034 + + + IO_FUNC_EN + HW I/O function enable. + 0x038 + + + IO_FUNC_SEL + HW I/O function select. + 0x03C + + + OUT_XOR + Output XOR (invert). + 0x040 + + + + + + QSPI0 + Serial Peripheral Interface. + 0x10014000 + SPI + 32 + read-write + + + 0 + 0x1000 + registers + + + QSPI0_IRQ5 + + + + + SCKDIV + Serial Clock Divisor Register. + 0x000 + + SCALE011 + + + + + SCKMODE + Serial Clock Mode Register. + 0x004 + + + PHA00 + Serial Clock Phase + + CPHA + + 0 + + Data is sampled on the leading edge of SCK and shifted on the trailing edge of SCK. + + 0 + + + 1 + + Data is shifted on the leading edge of SCK and sampled on the trailing edge of SCK. + + 1 + + + + + POL11 + Serial Clock Polarity + + CPOL + + 0 + Inactive state of SCK is logical 0. + 0 + + + 1 + Inactive state of SCK is logical 1. + 1 + + + + + + + + CSID + Chip Select ID Register. + 0x010 + + + + CSDEF + Chip Select Default Register. + 0x014 + + + + CSMODE + Chip Select Mode Register. + 0x018 + + + MODE01 + + Chip_Select_Modes + + AUTO + Assert/de-assert CS at the beginning/end of each frame. + 0 + + + HOLD + Keep CS continuously asserted after the initial frame. + 2 + + + OFF + Disable hardware control of the CS pin. + 3 + + + + + + + + DELAY0 + Delay Control Register 0. + 0x028 + + CSSCK07 + SCKCS1623 + + + + + DELAY1 + Delay Control Register 1. + 0x02C + + INTERCS07 + INTERXFR1623 + + + + + FMT + Frame Format Register. + 0x040 + + + PROTO01 + + SPI_Protocol + + Single + Data Pins: DQ0 (MOSI), DQ1 (MISO). + 0 + + + Dual + Data Pins: DQ0, DQ1. + 1 + + + Quad + Data Pins: DQ0, DQ1, DQ2, DQ3. + 2 + + + + + ENDIAN22 + + SPI_Endianness + + MSB_First + Tansmit most-significant bit first. + 0 + + + LSB_First + Transmit least-significant bit first. + 1 + + + + + DIR33 + + SPI_IO_Direction + + RX + + For dual and quad protocols, the DQ pins are tri-stated. + For the single protocol, the DQ0 pin is driven with the transmit data as normal. + + 0 + + + TX + The receive FIFO is not populated. + 1 + + + + + LEN1619 + + + + + + TXDATA + Transmit Data Register. + 0x048 + + DATA07 + FULL3131 + + + + + RXDATA + Receive Data Register. + 0x04C + + DATA07 + EMPTY3131 + + + + + TXMARK + Transmit Watermark Register. + 0x050 + + TXMARK02 + + + + + RXMARK + Receive Watermark Register. + 0x054 + + RXMARK02 + + + + + IE + SPI Interrupt Enable Register. + 0x070 + + TXWM00 + RXWM11 + + + + + IP + SPI Interrupt Pending Register. + 0x074 + + TXWM00 + RXWM11 + + + + + FCTRL + SPI Flash Interface Control Register. + 0x060 + + ENABLE00 + + + + + FFMT + SPI Flash Instruction Format Register. + 0x064 + + CMD_EN00 + ADDR_LEN13 + PAD_CNT47 + CMD_PROTO89 + ADDR_PROTO1011 + DATA_PROTO1213 + CMD_CODE1623 + PAD_CODE2431 + + + + + + + + + QSPI1 + Serial Peripheral Interface. + 0x10024000 + SPI + QSPI1_IRQ6 + + + + QSPI2 + Serial Peripheral Interface. + 0x10034000 + SPI + QSPI2_IRQ7 + + + + UART0 + Universal Asynchronous Receiver/Transmitter. + 0x10013000 + UART + 32 + read-write + + + 0 + 0x1000 + registers + + + UART0_IRQ3 + + + + TXDATA + Transmit Data Register. + 0x000 + + DATA07 + FULL3131 + + + + RXDATA + Receive Data Register. + 0x004 + + DATA07 + EMPTY3131 + + + + TXCTRL + Transmit Control Register. + 0x008 + + ENABLE00 + NSTOP11 + TXCNT1618 + + + + RXCTRL + Receive Control Register. + 0x00C + + ENABLE00 + RXCNT1618 + + + + IP + Interrupt Pending Register. + 0x0010 + + TXWM00 + RXWM11 + + + + IE + Interrupt Enable Register. + 0x0014 + + + DIV + Baud Rate Divisor Register (BAUD = Fin / (DIV + 1)). + + 0x0018 + + DIV015 + + + + + + UART1 + Universal Asynchronous Receiver/Transmitter. + 0x10023000 + UART + UART1_IRQ4 + + + diff --git a/misc/svd/GD32VW55x.svd b/misc/svd/GD32VW55x.svd new file mode 100644 index 0000000..7bc8e73 --- /dev/null +++ b/misc/svd/GD32VW55x.svd @@ -0,0 +1,38093 @@ + + + + + GD32VF103 + 1.0 + GD32VF103 RISC-V Microcontroller based device + + + GD32VF103 + r1p0 + little + 1 + 0 + 0 + + + 8 + 32 + 32 + 0x0 + 0xFFFFFFFF + + + + ADC0 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC0_1 + 37 + + + + STAT + STAT + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRC + Start flag of regular channel group + 4 + 1 + + + STIC + Start flag of inserted channel group + 3 + 1 + + + EOIC + End of inserted group conversion flag + 2 + 1 + + + EOC + End of group conversion flag + 1 + 1 + + + WDE + Analog watchdog event flag + 0 + 1 + + + + + CTL0 + CTL0 + control register 0 + 0x04 + 0x20 + read-write + 0x00000000 + + + RWDEN + Regular channel analog watchdog enable + 23 + 1 + + + IWDEN + Inserted channel analog watchdog + enable + 22 + 1 + + + SYNCM + sync mode selection + 16 + 4 + + + DISNUM + Number of conversions in + discontinuous mode + 13 + 3 + + + DISIC + Discontinuous mode on + inserted channels + 12 + 1 + + + DISRC + Discontinuous mode on regular + channels + 11 + 1 + + + ICA + Inserted channel group convert + automatically + 10 + 1 + + + WDSC + When in scan mode, analog watchdog + is effective on a single channel + 9 + 1 + + + SM + Scan mode + 8 + 1 + + + EOICIE + Interrupt enable for EOIC + 7 + 1 + + + WDEIE + Interrupt enable for WDE + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + WDCHSEL + Analog watchdog channel select + 0 + 5 + + + + + CTL1 + CTL1 + control register 1 + 0x08 + 0x20 + read-write + 0x00000000 + + + TSVREN + Channel 16 and 17 enable of ADC0 + 23 + 1 + + + SWRCST + Start on regular channel + 22 + 1 + + + SWICST + Start on inserted channel + 21 + 1 + + + ETERC + External trigger enable for regular channel + 20 + 1 + + + ETSRC + External trigger select for regular channel + 17 + 3 + + + ETEIC + External trigger select for inserted channel + 15 + 1 + + + ETSIC + External trigger select for inserted channel + 12 + 3 + + + DAL + Data alignment + 11 + 1 + + + DMA + DMA request enable + 8 + 1 + + + RSTCLB + Reset calibration + 3 + 1 + + + CLB + ADC calibration + 2 + 1 + + + CTN + Continuous mode + 1 + 1 + + + ADCON + ADC on + 0 + 1 + + + + + SAMPT0 + SAMPT0 + Sample time register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + SPT10 + Channel 10 sample time + selection + 0 + 3 + + + SPT11 + Channel 11 sample time + selection + 3 + 3 + + + SPT12 + Channel 12 sample time + selection + 6 + 3 + + + SPT13 + Channel 13 sample time + selection + 9 + 3 + + + SPT14 + Channel 14 sample time + selection + 12 + 3 + + + SPT15 + Channel 15 sample time + selection + 15 + 3 + + + SPT16 + Channel 16 sample time + selection + 18 + 3 + + + SPT17 + Channel 17 sample time + selection + 21 + 3 + + + + + SAMPT1 + SAMPT1 + Sample time register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + SPT0 + Channel 0 sample time + selection + 0 + 3 + + + SPT1 + Channel 1 sample time + selection + 3 + 3 + + + SPT2 + Channel 2 sample time + selection + 6 + 3 + + + SPT3 + Channel 3 sample time + selection + 9 + 3 + + + SPT4 + Channel 4 sample time + selection + 12 + 3 + + + SPT5 + Channel 5 sample time + selection + 15 + 3 + + + SPT6 + Channel 6 sample time + selection + 18 + 3 + + + SPT7 + Channel 7 sample time + selection + 21 + 3 + + + SPT8 + Channel 8 sample time + selection + 24 + 3 + + + SPT9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFF0 + IOFF0 + Inserted channel data offset register + 0 + 0x14 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 0 + 0 + 12 + + + + + IOFF1 + IOFF1 + Inserted channel data offset register + 1 + 0x18 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 1 + 0 + 12 + + + + + IOFF2 + IOFF2 + Inserted channel data offset register + 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 2 + 0 + 12 + + + + + IOFF3 + IOFF3 + Inserted channel data offset register + 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 3 + 0 + 12 + + + + + WDHT + WDHT + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + WDHT + Analog watchdog higher + threshold + 0 + 12 + + + + + WDLT + WDLT + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + WDLT + Analog watchdog lower + threshold + 0 + 12 + + + + + RSQ0 + RSQ0 + regular sequence register 0 + 0x2C + 0x20 + read-write + 0x00000000 + + + RL + Regular channel group + length + 20 + 4 + + + RSQ15 + 16th conversion in regular + sequence + 15 + 5 + + + RSQ14 + 15th conversion in regular + sequence + 10 + 5 + + + RSQ13 + 14th conversion in regular + sequence + 5 + 5 + + + RSQ12 + 13th conversion in regular + sequence + 0 + 5 + + + + + RSQ1 + RSQ1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + RSQ11 + 12th conversion in regular + sequence + 25 + 5 + + + RSQ10 + 11th conversion in regular + sequence + 20 + 5 + + + RSQ9 + 10th conversion in regular + sequence + 15 + 5 + + + RSQ8 + 9th conversion in regular + sequence + 10 + 5 + + + RSQ7 + 8th conversion in regular + sequence + 5 + 5 + + + RSQ6 + 7th conversion in regular + sequence + 0 + 5 + + + + + RSQ2 + RSQ2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + RSQ5 + 6th conversion in regular + sequence + 25 + 5 + + + RSQ4 + 5th conversion in regular + sequence + 20 + 5 + + + RSQ3 + 4th conversion in regular + sequence + 15 + 5 + + + RSQ2 + 3rd conversion in regular + sequence + 10 + 5 + + + RSQ1 + 2nd conversion in regular + sequence + 5 + 5 + + + RSQ0 + 1st conversion in regular + sequence + 0 + 5 + + + + + ISQ + ISQ + Inserted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + IL + Inserted channel group length + 20 + 2 + + + ISQ3 + 4th conversion in inserted + sequence + 15 + 5 + + + ISQ2 + 3rd conversion in inserted + sequence + 10 + 5 + + + ISQ1 + 2nd conversion in inserted + sequence + 5 + 5 + + + ISQ0 + 1st conversion in inserted + sequence + 0 + 5 + + + + + IDATA0 + IDATA0 + Inserted data register 0 + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA1 + IDATA1 + Inserted data register 1 + 0x40 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA2 + IDATA2 + Inserted data register 2 + 0x44 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA3 + IDATA3 + Inserted data register 3 + 0x48 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + RDATA + RDATA + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ADC1RDTR + ADC regular channel data + 16 + 16 + + + RDATA + Regular channel data + 0 + 16 + + + + + OVSAMPCTL + OVSAMPCTL + Oversample control register + 0x80 + 0x20 + read-write + 0x00000000 + + + DRES + ADC resolution + 12 + 2 + + + TOVS + Triggered Oversampling + 9 + 1 + + + OVSS + Oversampling shift + 5 + 4 + + + OVSR + Oversampling ratio + 2 + 3 + + + OVSEN + Oversampler Enable + 0 + 1 + + + + + + + ADC1 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + ADC0_1 + 37 + + + + STAT + STAT + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRC + Start flag of regular channel group + 4 + 1 + + + STIC + Start flag of inserted channel group + 3 + 1 + + + EOIC + End of inserted group conversion flag + 2 + 1 + + + EOC + End of group conversion flag + 1 + 1 + + + WDE + Analog watchdog event flag + 0 + 1 + + + + + CTL0 + CTL0 + control register 0 + 0x4 + 0x20 + read-write + 0x00000000 + + + RWDEN + Regular channel analog watchdog + enable + 23 + 1 + + + IWDEN + Inserted channel analog watchdog + enable + 22 + 1 + + + DISNUM + Number of conversions in + discontinuous mode + 13 + 3 + + + DISIC + Discontinuous mode on + inserted channels + 12 + 1 + + + DISRC + Discontinuous mode on regular + channels + 11 + 1 + + + ICA + Inserted channel group convert + automatically + 10 + 1 + + + WDSC + When in scan mode, analog watchdog + is effective on a single channel + 9 + 1 + + + SM + Scan mode + 8 + 1 + + + EOICIE + Interrupt enable for EOIC + 7 + 1 + + + WDEIE + Interrupt enable for WDE + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + WDCHSEL + Analog watchdog channel select + 0 + 5 + + + + + CTL1 + CTL1 + control register 1 + 0x08 + 0x20 + read-write + 0x00000000 + + + SWRCST + Start on regular channel + 22 + 1 + + + SWICST + Start on inserted channel + 21 + 1 + + + ETERC + External trigger enable for regular channel + 20 + 1 + + + ETSRC + External trigger select for regular channel + 17 + 3 + + + ETEIC + External trigger enable for inserted channel + 15 + 1 + + + ETSIC + External trigger select for inserted channel + 12 + 3 + + + DAL + Data alignment + 11 + 1 + + + DMA + DMA request enable + 8 + 1 + + + RSTCLB + Reset calibration + 3 + 1 + + + CLB + ADC calibration + 2 + 1 + + + CTN + Continuous mode + 1 + 1 + + + ADCON + ADC on + 0 + 1 + + + + + SAMPT0 + SAMPT0 + Sample time register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + SPT10 + Channel 10 sample time + selection + 0 + 3 + + + SPT11 + Channel 11 sample time + selection + 3 + 3 + + + SPT12 + Channel 12 sample time + selection + 6 + 3 + + + SPT13 + Channel 13 sample time + selection + 9 + 3 + + + SPT14 + Channel 14 sample time + selection + 12 + 3 + + + SPT15 + Channel 15 sample time + selection + 15 + 3 + + + SPT16 + Channel 16 sample time + selection + 18 + 3 + + + SPT17 + Channel 17 sample time + selection + 21 + 3 + + + + + SAMPT1 + SAMPT1 + Sample time register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + SPT0 + Channel 0 sample time + selection + 0 + 3 + + + SPT1 + Channel 1 sample time + selection + 3 + 3 + + + SPT2 + Channel 2 sample time + selection + 6 + 3 + + + SPT3 + Channel 3 sample time + selection + 9 + 3 + + + SPT4 + Channel 4 sample time + selection + 12 + 3 + + + SPT5 + Channel 5 sample time + selection + 15 + 3 + + + SPT6 + Channel 6 sample time + selection + 18 + 3 + + + SPT7 + Channel 7 sample time + selection + 21 + 3 + + + SPT8 + Channel 8 sample time + selection + 24 + 3 + + + SPT9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFF0 + IOFF0 + Inserted channel data offset register + 0 + 0x14 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 0 + 0 + 12 + + + + + IOFF1 + IOFF1 + Inserted channel data offset register + 1 + 0x18 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 1 + 0 + 12 + + + + + IOFF2 + IOFF2 + Inserted channel data offset register + 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 2 + 0 + 12 + + + + + IOFF3 + IOFF3 + Inserted channel data offset register + 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for inserted channel + 3 + 0 + 12 + + + + + WDHT + WDHT + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + WDHT + Analog watchdog higher + threshold + 0 + 12 + + + + + WDLT + WDLT + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + WDLT + Analog watchdog lower + threshold + 0 + 12 + + + + + RSQ0 + RSQ0 + regular sequence register 0 + 0x2C + 0x20 + read-write + 0x00000000 + + + RL + Regular channel group + length + 20 + 4 + + + RSQ15 + 16th conversion in regular + sequence + 15 + 5 + + + RSQ14 + 15th conversion in regular + sequence + 10 + 5 + + + RSQ13 + 14th conversion in regular + sequence + 5 + 5 + + + RSQ12 + 13th conversion in regular + sequence + 0 + 5 + + + + + RSQ1 + RSQ1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + RSQ11 + 12th conversion in regular + sequence + 25 + 5 + + + RSQ10 + 11th conversion in regular + sequence + 20 + 5 + + + RSQ9 + 10th conversion in regular + sequence + 15 + 5 + + + RSQ8 + 9th conversion in regular + sequence + 10 + 5 + + + RSQ7 + 8th conversion in regular + sequence + 5 + 5 + + + RSQ6 + 7th conversion in regular + sequence + 0 + 5 + + + + + RSQ2 + RSQ2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + RSQ5 + 6th conversion in regular + sequence + 25 + 5 + + + RSQ4 + 5th conversion in regular + sequence + 20 + 5 + + + RSQ3 + 4th conversion in regular + sequence + 15 + 5 + + + RSQ2 + 3rd conversion in regular + sequence + 10 + 5 + + + RSQ1 + 2nd conversion in regular + sequence + 5 + 5 + + + RSQ0 + 1st conversion in regular + sequence + 0 + 5 + + + + + ISQ + ISQ + Inserted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + IL + Inserted channel group length + 20 + 2 + + + ISQ3 + 4th conversion in inserted + sequence + 15 + 5 + + + ISQ2 + 3rd conversion in inserted + sequence + 10 + 5 + + + ISQ1 + 2nd conversion in inserted + sequence + 5 + 5 + + + ISQ0 + 1st conversion in inserted + sequence + 0 + 5 + + + + + IDATA0 + IDATA0 + Inserted data register 0 + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA1 + IDATA1 + Inserted data register 1 + 0x40 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA2 + IDATA2 + Inserted data register 2 + 0x44 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + IDATA3 + IDATA3 + Inserted data register 3 + 0x48 + 0x20 + read-only + 0x00000000 + + + IDATAn + Inserted number n conversion data + 0 + 16 + + + + + RDATA + RDATA + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular channel data + 0 + 16 + + + + + + + AFIO + Alternate-function I/Os + AFIO + 0x40010000 + + 0x0 + 0x400 + registers + + + + EC + EC + Event control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EOE + Event output enable + 7 + 1 + + + PORT + Event output port selection + 4 + 3 + + + PIN + Event output pin selection + 0 + 4 + + + + + PCF0 + PCF0 + AFIO port configuration register 0 + 0x04 + 0x20 + read-write + 0x00000000 + + + TIMER1ITI1_REMAP + TIMER1 internal trigger 1 remapping + 29 + 1 + + + SPI2_REMAP + SPI2/I2S2 remapping + 28 + 1 + + + SWJ_CFG + Serial wire JTAG configuration + 24 + 3 + + + CAN1_REMAP + CAN1 I/O remapping + 22 + 1 + + + TIMER4CH3_IREMAP + TIMER4 channel3 internal remapping + 16 + 1 + + + PD01_REMAP + Port D0/Port D1 mapping on OSC_IN/OSC_OUT + 15 + 1 + + + CAN0_REMAP + CAN0 alternate interface remapping + 13 + 2 + + + TIMER3_REMAP + TIMER3 remapping + 12 + 1 + + + TIMER2_REMAP + TIMER2 remapping + 10 + 2 + + + TIMER1_REMAP + TIMER1 remapping + 8 + 2 + + + TIMER0_REMAP + TIMER0 remapping + 6 + 2 + + + USART2_REMAP + USART2 remapping + 4 + 2 + + + USART1_REMAP + USART1 remapping + 3 + 1 + + + USART0_REMAP + USART0 remapping + 2 + 1 + + + I2C0_REMAP + I2C0 remapping + 1 + 1 + + + SPI0_REMAP + SPI0 remapping + 0 + 1 + + + + + EXTISS0 + EXTISS0 + EXTI sources selection register 0 + 0x08 + 0x20 + read-write + 0x00000000 + + + EXTI3_SS + EXTI 3 sources selection + 12 + 4 + + + EXTI2_SS + EXTI 2 sources selection + 8 + 4 + + + EXTI1_SS + EXTI 1 sources selection + 4 + 4 + + + EXTI0_SS + EXTI 0 sources selection + 0 + 4 + + + + + EXTISS1 + EXTISS1 + EXTI sources selection register 1 + 0x0C + 0x20 + read-write + 0x00000000 + + + EXTI7_SS + EXTI 7 sources selection + 12 + 4 + + + EXTI6_SS + EXTI 6 sources selection + 8 + 4 + + + EXTI5_SS + EXTI 5 sources selection + 4 + 4 + + + EXTI4_SS + EXTI 4 sources selection + 0 + 4 + + + + + EXTISS2 + EXTISS2 + EXTI sources selection register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI11_SS + EXTI 11 sources selection + 12 + 4 + + + EXTI10_SS + EXTI 10 sources selection + 8 + 4 + + + EXTI9_SS + EXTI 9 sources selection + 4 + 4 + + + EXTI8_SS + EXTI 8 sources selection + 0 + 4 + + + + + EXTISS3 + EXTISS3 + EXTI sources selection register 3 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI15_SS + EXTI 15 sources selection + 12 + 4 + + + EXTI14_SS + EXTI 14 sources selection + 8 + 4 + + + EXTI13_SS + EXTI 13 sources selection + 4 + 4 + + + EXTI12_SS + EXTI 12 sources selection + 0 + 4 + + + + + PCF1 + PCF1 + AFIO port configuration register 1 + 0x1C + 0x20 + read-write + 0x00000000 + + + EXMC_NADV + EXMC_NADV connect/disconnect + 10 + 1 + + + + + + + BKP + Backup registers + BKP + 0x40006C00 + + 0x0 + 0x400 + registers + + + Tamper + 21 + + + + DATA0 + DATA0 + Backup data register 0 + 0x4 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA1 + DATA1 + Backup data register 1 + 0x8 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA2 + DATA2 + Backup data register 2 + 0xC + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA3 + DATA3 + Backup data register 3 + 0x10 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA4 + DATA4 + Backup data register 4 + 0x14 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA5 + DATA5 + Backup data register 5 + 0x18 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA6 + DATA6 + Backup data register 6 + 0x1C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA7 + DATA7 + Backup data register 7 + 0x20 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA8 + DATA8 + Backup data register 8 + 0x24 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA9 + DATA9 + Backup data register 9 + 0x28 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA10 + DATA10 + Backup data register 10 + 0x40 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA11 + DATA11 + Backup data register 11 + 0x44 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA12 + DATA12 + Backup data register 12 + 0x48 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA13 + DATA13 + Backup data register 13 + 0x4C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA14 + DATA14 + Backup data register 14 + 0x50 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA15 + DATA15 + Backup data register 15 + 0x54 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA16 + DATA16 + Backup data register 16 + 0x58 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA17 + DATA17 + Backup data register 17 + 0x5C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA18 + DATA18 + Backup data register 18 + 0x60 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA19 + DATA19 + Backup data register 19 + 0x64 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA20 + DATA20 + Backup data register 20 + 0x68 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA21 + DATA21 + Backup data register 21 + 0x6C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA22 + DATA22 + Backup data register 22 + 0x70 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA23 + DATA23 + Backup data register 23 + 0x74 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA24 + DATA24 + Backup data register 24 + 0x78 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA25 + DATA25 + Backup data register 25 + 0x7C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA26 + DATA26 + Backup data register 26 + 0x80 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA27 + DATA27 + Backup data register 27 + 0x84 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA28 + DATA28 + Backup data register 28 + 0x88 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA29 + DATA29 + Backup data register 29 + 0x8C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA30 + DATA30 + Backup data register 30 + 0x90 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA31 + DATA31 + Backup data register 31 + 0x94 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA32 + DATA32 + Backup data register 32 + 0x98 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA33 + DATA33 + Backup data register 33 + 0x9C + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA34 + DATA34 + Backup data register 34 + 0xA0 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA35 + DATA35 + Backup data register 35 + 0xA4 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA36 + DATA36 + Backup data register 36 + 0xA8 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA37 + DATA37 + Backup data register 37 + 0xAC + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA38 + DATA38 + Backup data register 38 + 0xB0 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA39 + DATA39 + Backup data register 39 + 0xB4 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA40 + DATA40 + Backup data register 40 + 0xB8 + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + DATA41 + DATA41 + Backup data register 41 + 0xBC + 0x10 + read-write + 0x0000 + + + DATA + Backup data + 0 + 16 + + + + + OCTL + OCTL + RTC signal output control register + 0x2C + 0x10 + read-write + 0x0000 + + + ROSEL + RTC output selection + 9 + 1 + + + ASOEN + RTC alarm or second signal output enable + 8 + 1 + + + COEN + RTC clock calibration output enable + 7 + 1 + + + RCCV + RTC clock calibration value + 0 + 7 + + + + + TPCTL + TPCTL + Tamper pin control register + 0x30 + 0x10 + read-write + 0x0000 + + + TPAL + TAMPER pin active level + 1 + 1 + + + TPEN + TAMPER detection enable + 0 + 1 + + + + + TPCS + TPCS + Tamper control and status register + 0x34 + 0x10 + read-write + 0x0000 + + + TIF + Tamper interrupt flag + 9 + 1 + + + TEF + Tamper event flag + 8 + 1 + + + TPIE + Tamper interrupt enable + 2 + 1 + + + TIR + Tamper interrupt reset + 1 + 1 + + + TER + Tamper event reset + 0 + 1 + + + + + + + CAN0 + Controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN0_TX + 38 + + + CAN0_RX0 + 39 + + + CAN0_RX1 + 40 + + + CAN0_EWMC + 41 + + + + CTL + CTL + Control register + 0x0 + 0x20 + read-write + 0x00010002 + + + DFZ + Debug freeze + 16 + 1 + + + SWRST + Software reset + 15 + 1 + + + TTC + Time-triggered communication + 7 + 1 + + + ABOR + Automatic bus-off recovery + 6 + 1 + + + AWU + Automatic wakeup + 5 + 1 + + + ARD + Automatic retransmission disable + 4 + 1 + + + RFOD + Receive FIFO overwrite disable + 3 + 1 + + + TFO + Transmit FIFO order + 2 + 1 + + + SLPWMOD + Sleep working mode + 1 + 1 + + + IWMOD + Initial working mode + 0 + 1 + + + + + STAT + STAT + Status register + 0x04 + 0x20 + 0x00000C02 + + + RXL + RX level + 11 + 1 + read-only + + + LASTRX + Last sample value of RX pin + 10 + 1 + read-only + + + RS + Receiving state + 9 + 1 + read-only + + + TS + Transmitting state + 8 + 1 + read-only + + + SLPIF + Status change interrupt flag of sleep + working mode entering + 4 + 1 + read-write + + + WUIF + Status change interrupt flag of wakeup + from sleep working mode + 3 + 1 + read-write + + + ERRIF + Error interrupt flag + 2 + 1 + read-write + + + SLPWS + Sleep working state + 1 + 1 + read-only + + + IWS + Initial working state + 0 + 1 + read-only + + + + + TSTAT + TSTAT + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TMLS2 + Transmit mailbox 2 last sending + in transmit FIFO + 31 + 1 + read-only + + + TMLS1 + Transmit mailbox 1 last sending + in transmit FIFO + 30 + 1 + read-only + + + TMLS0 + Transmit mailbox 0 last sending + in transmit FIFO + 29 + 1 + read-only + + + TME2 + Transmit mailbox 2 empty + 28 + 1 + read-only + + + TME1 + Transmit mailbox 1 empty + 27 + 1 + read-only + + + TME0 + Transmit mailbox 0 empty + 26 + 1 + read-only + + + NUM + number of the transmit FIFO mailbox in + which the frame will be transmitted if at least one mailbox is empty + 24 + 2 + read-only + + + MST2 + Mailbox 2 stop transmitting + 23 + 1 + read-write + + + MTE2 + Mailbox 2 transmit error + 19 + 1 + read-write + + + MAL2 + Mailbox 2 arbitration lost + 18 + 1 + read-write + + + MTFNERR2 + Mailbox 2 transmit finished and no error + 17 + 1 + read-write + + + MTF2 + Mailbox 2 transmit finished + 16 + 1 + read-write + + + MST1 + Mailbox 1 stop transmitting + 15 + 1 + read-write + + + MTE1 + Mailbox 1 transmit error + 11 + 1 + read-write + + + MAL1 + Mailbox 1 arbitration lost + 10 + 1 + read-write + + + MTFNERR1 + Mailbox 1 transmit finished and no error + 9 + 1 + read-write + + + MTF1 + Mailbox 1 transmit finished + 8 + 1 + read-write + + + MST0 + Mailbox 0 stop transmitting + 7 + 1 + read-write + + + MTE0 + Mailbox 0 transmit error + 3 + 1 + read-write + + + MAL0 + Mailbox 0 arbitration lost + 2 + 1 + read-write + + + MTFNERR0 + Mailbox 0 transmit finished and no error + 1 + 1 + read-write + + + MTF0 + Mailbox 0 transmit finished + 0 + 1 + read-write + + + + + RFIFO0 + RFIFO0 + Receive message FIFO0 register + 0x0C + 0x20 + 0x00000000 + + + RFD0 + Receive FIFO0 dequeue + 5 + 1 + read-write + + + RFO0 + Receive FIFO0 overfull + 4 + 1 + read-write + + + RFF0 + Receive FIFO0 full + 3 + 1 + read-write + + + RFL0 + Receive FIFO0 length + 0 + 2 + read-only + + + + + RFIFO1 + RFIFO1 + Receive message FIFO1 register + 0x10 + 0x20 + 0x00000000 + + + RFD1 + Receive FIFO1 dequeue + 5 + 1 + read-write + + + RFO1 + Receive FIFO1 overfull + 4 + 1 + read-write + + + RFF1 + Receive FIFO1 full + 3 + 1 + read-write + + + RFL1 + Receive FIFO1 length + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + SLPWIE + Sleep working interrupt enable + 17 + 1 + + + WIE + Wakeup interrupt enable + 16 + 1 + + + ERRIE + Error interrupt enable + 15 + 1 + + + ERRNIE + Error number interrupt enable + 11 + 1 + + + BOIE + Bus-off interrupt enable + 10 + 1 + + + PERRIE + Passive error interrupt enable + 9 + 1 + + + WERRIE + Warning error interrupt enable + 8 + 1 + + + RFOIE1 + Receive FIFO1 overfull interrupt enable + 6 + 1 + + + RFFIE1 + Receive FIFO1 full interrupt enable + 5 + 1 + + + RFNEIE1 + Receive FIFO1 not empty interrupt enable + 4 + 1 + + + RFOIE0 + Receive FIFO0 overfull interrupt enable + 3 + 1 + + + RFFIE0 + Receive FIFO0 full interrupt enable + 2 + 1 + + + RFNEIE0 + Receive FIFO0 not empty interrupt enable + 1 + 1 + + + TMEIE + Transmit mailbox empty interrupt enable + 0 + 1 + + + + + ERR + ERR + Error register + 0x18 + 0x20 + 0x00000000 + + + RECNT + Receive Error Count defined + by the CAN standard + 24 + 8 + read-only + + + TECNT + Transmit Error Count defined + by the CAN standard + 16 + 8 + read-only + + + ERRN + Error number + 4 + 3 + read-write + + + BOERR + Bus-off error + 2 + 1 + read-only + + + PERR + Passive error + 1 + 1 + read-only + + + WERR + Warning error + 0 + 1 + read-only + + + + + BT + BT + Bit timing register + 0x1C + 0x20 + read-write + 0x01230000 + + + SCMOD + Silent communication mode + 31 + 1 + + + LCMOD + Loopback communication mode + 30 + 1 + + + SJW + Resynchronization jump width + 24 + 2 + + + BS2 + Bit segment 2 + 20 + 3 + + + BS1 + Bit segment 1 + 16 + 4 + + + BAUDPSC + Baud rate prescaler + 0 + 10 + + + + + TMI0 + TMI0 + Transmit mailbox identifier register 0 + 0x180 + 0x20 + read-write + 0x00000000 + + + SFID_EFID + The frame identifier + 21 + 11 + + + EFID + The frame identifier + 3 + 18 + + + FF + Frame format + 2 + 1 + + + FT + Frame type + 1 + 1 + + + TEN + Transmit enable + 0 + 1 + + + + + TMP0 + TMP0 + Transmit mailbox property register 0 + 0x184 + 0x20 + read-write + 0x00000000 + + + TS + Time stamp + 16 + 16 + + + TSEN + Time stamp enable + 8 + 1 + + + DLENC + Data length code + 0 + 4 + + + + + TMDATA00 + TMDATA00 + Transmit mailbox data0 register + 0x188 + 0x20 + read-write + 0x00000000 + + + DB3 + Data byte 3 + 24 + 8 + + + DB2 + Data byte 2 + 16 + 8 + + + DB1 + Data byte 1 + 8 + 8 + + + DB0 + Data byte 0 + 0 + 8 + + + + + TMDATA10 + TMDATA10 + Transmit mailbox data1 register + 0x18C + 0x20 + read-write + 0x00000000 + + + DB7 + Data byte 7 + 24 + 8 + + + DB6 + Data byte 6 + 16 + 8 + + + DB5 + Data byte 5 + 8 + 8 + + + DB4 + Data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox identifier register 1 + 0x190 + 0x20 + read-write + 0x00000000 + + + SFID_EFID + The frame identifier + 21 + 11 + + + EFID + The frame identifier + 3 + 18 + + + FF + Frame format + 2 + 1 + + + FT + Frame type + 1 + 1 + + + TEN + Transmit enable + 0 + 1 + + + + + TMP1 + TMP1 + Transmit mailbox property register 1 + 0x194 + 0x20 + read-write + 0x00000000 + + + TS + Time stamp + 16 + 16 + + + TSEN + Time stamp enable + 8 + 1 + + + DLENC + Data length code + 0 + 4 + + + + + TMDATA01 + TMDATA01 + Transmit mailbox data0 register + 0x198 + 0x20 + read-write + 0x00000000 + + + DB3 + Data byte 3 + 24 + 8 + + + DB2 + Data byte 2 + 16 + 8 + + + DB1 + Data byte 1 + 8 + 8 + + + DB0 + Data byte 0 + 0 + 8 + + + + + TMDATA11 + TMDATA11 + Transmit mailbox data1 register + 0x19C + 0x20 + read-write + 0x00000000 + + + DB7 + Data byte 7 + 24 + 8 + + + DB6 + Data byte 6 + 16 + 8 + + + DB5 + Data byte 5 + 8 + 8 + + + DB4 + Data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox identifier register 2 + 0x1A0 + 0x20 + read-write + 0x00000000 + + + SFID_EFID + The frame identifier + 21 + 11 + + + EFID + The frame identifier + 3 + 18 + + + FF + Frame format + 2 + 1 + + + FT + Frame type + 1 + 1 + + + TEN + Transmit enable + 0 + 1 + + + + + TMP2 + TMP2 + Transmit mailbox property register 2 + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TS + Time stamp + 16 + 16 + + + TSEN + Time stamp enable + 8 + 1 + + + DLENC + Data length code + 0 + 4 + + + + + TMDATA02 + TMDATA02 + Transmit mailbox data0 register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + DB3 + Data byte 3 + 24 + 8 + + + DB2 + Data byte 2 + 16 + 8 + + + DB1 + Data byte 1 + 8 + 8 + + + DB0 + Data byte 0 + 0 + 8 + + + + + TMDATA12 + TMDATA12 + Transmit mailbox data1 register + 0x1AC + 0x20 + read-write + 0x00000000 + + + DB7 + Data byte 7 + 24 + 8 + + + DB6 + Data byte 6 + 16 + 8 + + + DB5 + Data byte 5 + 8 + 8 + + + DB4 + Data byte 4 + 0 + 8 + + + + + RFIFOMI0 + RFIFOMI0 + Receive FIFO mailbox identifier register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + SFID_EFID + The frame identifier + 21 + 11 + + + EFID + The frame identifier + 3 + 18 + + + FF + Frame format + 2 + 1 + + + FT + Frame type + 1 + 1 + + + + + RFIFOMP0 + RFIFOMP0 + Receive FIFO0 mailbox property register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + TS + Time stamp + 16 + 16 + + + FI + Filtering index + 8 + 8 + + + DLENC + Data length code + 0 + 4 + + + + + RFIFOMDATA00 + RFIFOMDATA00 + Receive FIFO0 mailbox data0 register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + DB3 + Data byte 3 + 24 + 8 + + + DB2 + Data byte 2 + 16 + 8 + + + DB1 + Data byte 1 + 8 + 8 + + + DB0 + Data byte 0 + 0 + 8 + + + + + RFIFOMDATA10 + RFIFOMDATA10 + Receive FIFO0 mailbox data1 register + 0x1BC + 0x20 + read-only + 0x00000000 + + + DB7 + Data byte 7 + 24 + 8 + + + DB6 + Data byte 6 + 16 + 8 + + + DB5 + Data byte 5 + 8 + 8 + + + DB4 + Data byte 4 + 0 + 8 + + + + + RFIFOMI1 + RFIFOMI1 + Receive FIFO1 mailbox identifier register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + SFID_EFID + The frame identifier + 21 + 11 + + + EFID + The frame identifier + 3 + 18 + + + FF + Frame format + 2 + 1 + + + FT + Frame type + 1 + 1 + + + + + RFIFOMP1 + RFIFOMP1 + Receive FIFO1 mailbox property register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + TS + Time stamp + 16 + 16 + + + FI + Filtering index + 8 + 8 + + + DLENC + Data length code + 0 + 4 + + + + + RFIFOMDATA01 + RFIFOMDATA01 + Receive FIFO1 mailbox data0 register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + DB3 + Data byte 3 + 24 + 8 + + + DB2 + Data byte 2 + 16 + 8 + + + DB1 + Data byte 1 + 8 + 8 + + + DB0 + Data byte 0 + 0 + 8 + + + + + RFIFOMDATA11 + RFIFOMDATA11 + Receive FIFO1 mailbox data1 register + 0x1CC + 0x20 + read-only + 0x00000000 + + + DB7 + Data byte 7 + 24 + 8 + + + DB6 + Data byte 6 + 16 + 8 + + + DB5 + Data byte 5 + 8 + 8 + + + DB4 + Data byte 4 + 0 + 8 + + + + + FCTL + FCTL + Filter control register + 0x200 + 0x20 + read-write + 0x2A1C0E01 + + + HBC1F + Header bank of CAN1 filter + 8 + 6 + + + FLD + Filter lock disable + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode configuration register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMOD27 + Filter mode + 27 + 1 + + + FMOD26 + Filter mode + 26 + 1 + + + FMOD25 + Filter mode + 25 + 1 + + + FMOD24 + Filter mode + 24 + 1 + + + FMOD23 + Filter mode + 23 + 1 + + + FMOD22 + Filter mode + 22 + 1 + + + FMOD21 + Filter mode + 21 + 1 + + + FMOD20 + Filter mode + 20 + 1 + + + FMOD19 + Filter mode + 19 + 1 + + + FMOD18 + Filter mode + 18 + 1 + + + FMOD17 + Filter mode + 17 + 1 + + + FMOD16 + Filter mode + 16 + 1 + + + FMOD15 + Filter mode + 15 + 1 + + + FMOD14 + Filter mode + 14 + 1 + + + FMOD13 + Filter mode + 13 + 1 + + + FMOD12 + Filter mode + 12 + 1 + + + FMOD11 + Filter mode + 11 + 1 + + + FMOD10 + Filter mode + 10 + 1 + + + FMOD9 + Filter mode + 9 + 1 + + + FMOD8 + Filter mode + 8 + 1 + + + FMOD7 + Filter mode + 7 + 1 + + + FMOD6 + Filter mode + 6 + 1 + + + FMOD5 + Filter mode + 5 + 1 + + + FMOD4 + Filter mode + 4 + 1 + + + FMOD3 + Filter mode + 3 + 1 + + + FMOD2 + Filter mode + 2 + 1 + + + FMOD1 + Filter mode + 1 + 1 + + + FMOD0 + Filter mode + 0 + 1 + + + + + FSCFG + FSCFG + Filter scale configuration register + 0x20C + 0x20 + read-write + 0x00000000 + + + FS0 + Filter scale configuration + 0 + 1 + + + FS1 + Filter scale configuration + 1 + 1 + + + FS2 + Filter scale configuration + 2 + 1 + + + FS3 + Filter scale configuration + 3 + 1 + + + FS4 + Filter scale configuration + 4 + 1 + + + FS5 + Filter scale configuration + 5 + 1 + + + FS6 + Filter scale configuration + 6 + 1 + + + FS7 + Filter scale configuration + 7 + 1 + + + FS8 + Filter scale configuration + 8 + 1 + + + FS9 + Filter scale configuration + 9 + 1 + + + FS10 + Filter scale configuration + 10 + 1 + + + FS11 + Filter scale configuration + 11 + 1 + + + FS12 + Filter scale configuration + 12 + 1 + + + FS13 + Filter scale configuration + 13 + 1 + + + FS14 + Filter scale configuration + 14 + 1 + + + FS15 + Filter scale configuration + 15 + 1 + + + FS16 + Filter scale configuration + 16 + 1 + + + FS17 + Filter scale configuration + 17 + 1 + + + FS18 + Filter scale configuration + 18 + 1 + + + FS19 + Filter scale configuration + 19 + 1 + + + FS20 + Filter scale configuration + 20 + 1 + + + FS21 + Filter scale configuration + 21 + 1 + + + FS22 + Filter scale configuration + 22 + 1 + + + FS23 + Filter scale configuration + 23 + 1 + + + FS24 + Filter scale configuration + 24 + 1 + + + FS25 + Filter scale configuration + 25 + 1 + + + FS26 + Filter scale configuration + 26 + 1 + + + FS27 + Filter scale configuration + 27 + 1 + + + + + FAFIFO + FAFIFO + Filter associated FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FAF0 + Filter 0 associated with FIFO + 0 + 1 + + + FAF1 + Filter 1 associated with FIFO + 1 + 1 + + + FAF2 + Filter 2 associated with FIFO + 2 + 1 + + + FAF3 + Filter 3 associated with FIFO + 3 + 1 + + + FAF4 + Filter 4 associated with FIFO + 4 + 1 + + + FAF5 + Filter 5 associated with FIFO + 5 + 1 + + + FAF6 + Filter 6 associated with FIFO + 6 + 1 + + + FAF7 + Filter 7 associated with FIFO + 7 + 1 + + + FAF8 + Filter 8 associated with FIFO + 8 + 1 + + + FAF9 + Filter 9 associated with FIFO + 9 + 1 + + + FAF10 + Filter 10 associated with FIFO + 10 + 1 + + + FAF11 + Filter 11 associated with FIFO + 11 + 1 + + + FAF12 + Filter 12 associated with FIFO + 12 + 1 + + + FAF13 + Filter 13 associated with FIFO + 13 + 1 + + + FAF14 + Filter 14 associated with FIFO + 14 + 1 + + + FAF15 + Filter 15 associated with FIFO + 15 + 1 + + + FAF16 + Filter 16 associated with FIFO + 16 + 1 + + + FAF17 + Filter 17 associated with FIFO + 17 + 1 + + + FAF18 + Filter 18 associated with FIFO + 18 + 1 + + + FAF19 + Filter 19 associated with FIFO + 19 + 1 + + + FAF20 + Filter 20 associated with FIFO + 20 + 1 + + + FAF21 + Filter 21 associated with FIFO + 21 + 1 + + + FAF22 + Filter 22 associated with FIFO + 22 + 1 + + + FAF23 + Filter 23 associated with FIFO + 23 + 1 + + + FAF24 + Filter 24 associated with FIFO + 24 + 1 + + + FAF25 + Filter 25 associated with FIFO + 25 + 1 + + + FAF26 + Filter 26 associated with FIFO + 26 + 1 + + + FAF27 + Filter 27 associated with FIFO + 27 + 1 + + + + + FW + FW + Filter working register + 0x21C + 0x20 + read-write + 0x00000000 + + + FW0 + Filter working + 0 + 1 + + + FW1 + Filter working + 1 + 1 + + + FW2 + Filter working + 2 + 1 + + + FW3 + Filter working + 3 + 1 + + + FW4 + Filter working + 4 + 1 + + + FW5 + Filter working + 5 + 1 + + + FW6 + Filter working + 6 + 1 + + + FW7 + Filter working + 7 + 1 + + + FW8 + Filter working + 8 + 1 + + + FW9 + Filter working + 9 + 1 + + + FW10 + Filter working + 10 + 1 + + + FW11 + Filter working + 11 + 1 + + + FW12 + Filter working + 12 + 1 + + + FW13 + Filter working + 13 + 1 + + + FW14 + Filter working + 14 + 1 + + + FW15 + Filter working + 15 + 1 + + + FW16 + Filter working + 16 + 1 + + + FW17 + Filter working + 17 + 1 + + + FW18 + Filter working + 18 + 1 + + + FW19 + Filter working + 19 + 1 + + + FW20 + Filter working + 20 + 1 + + + FW21 + Filter working + 21 + 1 + + + FW22 + Filter working + 22 + 1 + + + FW23 + Filter working + 23 + 1 + + + FW24 + Filter working + 24 + 1 + + + FW25 + Filter working + 25 + 1 + + + FW26 + Filter working + 26 + 1 + + + FW27 + Filter working + 27 + 1 + + + + + F0DATA0 + F0DATA0 + Filter 0 data 0 register + 0x240 + 0x20 + read-write + 0x00000000 + + + FD0 + Filter bits + 0 + 1 + + + FD1 + Filter bits + 1 + 1 + + + FD2 + Filter bits + 2 + 1 + + + FD3 + Filter bits + 3 + 1 + + + FD4 + Filter bits + 4 + 1 + + + FD5 + Filter bits + 5 + 1 + + + FD6 + Filter bits + 6 + 1 + + + FD7 + Filter bits + 7 + 1 + + + FD8 + Filter bits + 8 + 1 + + + FD9 + Filter bits + 9 + 1 + + + FD10 + Filter bits + 10 + 1 + + + FD11 + Filter bits + 11 + 1 + + + FD12 + Filter bits + 12 + 1 + + + FD13 + Filter bits + 13 + 1 + + + FD14 + Filter bits + 14 + 1 + + + FD15 + Filter bits + 15 + 1 + + + FD16 + Filter bits + 16 + 1 + + + FD17 + Filter bits + 17 + 1 + + + FD18 + Filter bits + 18 + 1 + + + FD19 + Filter bits + 19 + 1 + + + FD20 + Filter bits + 20 + 1 + + + FD21 + Filter bits + 21 + 1 + + + FD22 + Filter bits + 22 + 1 + + + FD23 + Filter bits + 23 + 1 + + + FD24 + Filter bits + 24 + 1 + + + FD25 + Filter bits + 25 + 1 + + + FD26 + Filter bits + 26 + 1 + + + FD27 + Filter bits + 27 + 1 + + + FD28 + Filter bits + 28 + 1 + + + FD29 + Filter bits + 29 + 1 + + + FD30 + Filter bits + 30 + 1 + + + FD31 + Filter bits + 31 + 1 + + + + + F0DATA1 + F0DATA1 + Filter 0 data 1 register + 0x244 + 0x20 + read-write + 0x00000000 + + + FD0 + Filter bits + 0 + 1 + + + FD1 + Filter bits + 1 + 1 + + + FD2 + Filter bits + 2 + 1 + + + FD3 + Filter bits + 3 + 1 + + + FD4 + Filter bits + 4 + 1 + + + FD5 + Filter bits + 5 + 1 + + + FD6 + Filter bits + 6 + 1 + + + FD7 + Filter bits + 7 + 1 + + + FD8 + Filter bits + 8 + 1 + + + FD9 + Filter bits + 9 + 1 + + + FD10 + Filter bits + 10 + 1 + + + FD11 + Filter bits + 11 + 1 + + + FD12 + Filter bits + 12 + 1 + + + FD13 + Filter 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+ FD19 + Filter bits + 19 + 1 + + + FD20 + Filter bits + 20 + 1 + + + FD21 + Filter bits + 21 + 1 + + + FD22 + Filter bits + 22 + 1 + + + FD23 + Filter bits + 23 + 1 + + + FD24 + Filter bits + 24 + 1 + + + FD25 + Filter bits + 25 + 1 + + + FD26 + Filter bits + 26 + 1 + + + FD27 + Filter bits + 27 + 1 + + + FD28 + Filter bits + 28 + 1 + + + FD29 + Filter bits + 29 + 1 + + + FD30 + Filter bits + 30 + 1 + + + FD31 + Filter bits + 31 + 1 + + + + + F27DATA1 + F27DATA1 + Filter 27 data 1 register + 0x31C + 0x20 + read-write + 0x00000000 + + + FD0 + Filter bits + 0 + 1 + + + FD1 + Filter bits + 1 + 1 + + + FD2 + Filter bits + 2 + 1 + + + FD3 + Filter bits + 3 + 1 + + + FD4 + Filter bits + 4 + 1 + + + FD5 + Filter bits + 5 + 1 + + + FD6 + Filter bits + 6 + 1 + + + FD7 + Filter bits + 7 + 1 + + + FD8 + Filter bits + 8 + 1 + + + FD9 + Filter bits + 9 + 1 + + + FD10 + Filter bits + 10 + 1 + + + FD11 + Filter bits + 11 + 1 + + + FD12 + Filter bits + 12 + 1 + + + FD13 + Filter bits + 13 + 1 + + + FD14 + Filter bits + 14 + 1 + + + FD15 + Filter bits + 15 + 1 + + + FD16 + Filter bits + 16 + 1 + + + FD17 + Filter bits + 17 + 1 + + + FD18 + Filter bits + 18 + 1 + + + FD19 + Filter bits + 19 + 1 + + + FD20 + Filter bits + 20 + 1 + + + FD21 + Filter bits + 21 + 1 + + + FD22 + Filter bits + 22 + 1 + + + FD23 + Filter bits + 23 + 1 + + + FD24 + Filter bits + 24 + 1 + + + FD25 + Filter bits + 25 + 1 + + + FD26 + Filter bits + 26 + 1 + + + FD27 + Filter bits + 27 + 1 + + + FD28 + Filter bits + 28 + 1 + + + FD29 + Filter bits + 29 + 1 + + + FD30 + Filter bits + 30 + 1 + + + FD31 + Filter bits + 31 + 1 + + + + + + + CAN1 + 0x40006800 + + CAN1_TX + 82 + + + CAN1_RX0 + 83 + + + CAN1_RX1 + 84 + + + CAN1_EWMC + 85 + + + + CRC + cyclic redundancy check calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DATA + DATA + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DATA + CRC calculation result bits + 0 + 32 + + + + + FDATA + FDATA + Free data register + 0x04 + 0x20 + read-write + 0x00000000 + + + FDATA + Free Data Register bits + 0 + 8 + + + + + CTL + CTL + Control register + 0x08 + 0x20 + read-write + 0x00000000 + + + RST + reset bit + 0 + 1 + + + + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTL + CTL + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DEN0 + DAC0 enable + 0 + 1 + + + DBOFF0 + DAC0 output buffer turn off + 1 + 1 + + + DTEN0 + DAC0 trigger enable + 2 + 1 + + + DTSEL0 + DAC0 trigger selection + 3 + 3 + + + DWM0 + DAC0 noise wave mode + 6 + 2 + + + DWBW0 + DAC0 noise wave bit width + 8 + 4 + + + DDMAEN0 + DAC0 DMA enable + 12 + 1 + + + DEN1 + DAC1 enable + 16 + 1 + + + DBOFF1 + DAC1 output buffer turn off + 17 + 1 + + + DTEN1 + DAC1 trigger enable + 18 + 1 + + + DTSEL1 + DAC1 trigger selection + 19 + 3 + + + DWM1 + DAC1 noise wave mode + 22 + 2 + + + DWBW1 + DAC1 noise wave bit width + 24 + 4 + + + DDMAEN1 + DAC1 DMA enable + 28 + 1 + + + + + SWT + SWT + software trigger register + 0x04 + 0x20 + write-only + 0x00000000 + + + SWTR0 + DAC0 software trigger + 0 + 1 + + + SWTR1 + DAC1 software trigger + 1 + 1 + + + + + DAC0_R12DH + DAC0_R12DH + DAC0 12-bit right-aligned data holding register + 0x08 + 0x20 + read-write + 0x00000000 + + + DAC0_DH + DAC0 12-bit right-aligned + data + 0 + 12 + + + + + DAC0_L12DH + DAC0_L12DH + DAC0 12-bit left-aligned data holding register + 0x0C + 0x20 + read-write + 0x00000000 + + + DAC0_DH + DAC0 12-bit left-aligned + data + 4 + 12 + + + + + DAC0_R8DH + DAC0_R8DH + DAC0 8-bit right aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DAC0_DH + DAC0 8-bit right-aligned + data + 0 + 8 + + + + + DAC1_R12DH + DAC1_R12DH + DAC1 12-bit right-aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DAC1_DH + DAC1 12-bit right-aligned + data + 0 + 12 + + + + + DAC1_L12DH + DAC1_L12DH + DAC1 12-bit left aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DAC1_DH + DAC1 12-bit left-aligned + data + 4 + 12 + + + + + DAC1_R8DH + DAC1_R8DH + DAC1 8-bit right aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DAC1_DH + DAC1 8-bit right-aligned + data + 0 + 8 + + + + + DACC_R12DH + DACC_R12DH + DAC concurrent mode 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DAC0_DH + DAC0 12-bit right-aligned + data + 0 + 12 + + + DAC1_DH + DAC1 12-bit right-aligned + data + 16 + 12 + + + + + DACC_L12DH + DACC_L12DH + DAC concurrent mode 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DAC0_DH + DAC0 12-bit left-aligned + data + 4 + 12 + + + DAC1_DH + DAC1 12-bit left-aligned + data + 20 + 12 + + + + + DACC_R8DH + DACC_R8DH + DAC concurrent mode 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DAC0_DH + DAC0 8-bit right-aligned + data + 0 + 8 + + + DAC1_DH + DAC1 8-bit right-aligned + data + 8 + 8 + + + + + DAC0_DO + DAC0_DO + DAC0 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DAC0_DO + DAC0 data output + 0 + 12 + + + + + DAC1_DO + DAC1_DO + DAC1 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DAC1_DO + DAC1 data output + 0 + 12 + + + + + + + DBG + Debug support + DBG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + ID + ID + ID code register + 0x0 + 0x20 + read-only + 0x00000000 + + + ID_CODE + DBG ID code register + 0 + 32 + + + + + CTL + CTL + Control register 0 + 0x4 + 0x20 + read-write + 0x00000000 + + + SLP_HOLD + Sleep mode hold register + 0 + 1 + + + DSLP_HOLD + Deep-sleep mode hold register + 1 + 1 + + + STB_HOLD + Standby mode hold register + 2 + 1 + + + FWDGT_HOLD + FWDGT hold bit + 8 + 1 + + + WWDGT_HOLD + WWDGT hold bit + 9 + 1 + + + TIMER0_HOLD + TIMER 0 hold bit + 10 + 1 + + + TIMER1_HOLD + TIMER 1 hold bit + 11 + 1 + + + TIMER2_HOLD + TIMER 2 hold bit + 12 + 1 + + + TIMER3_HOLD + TIMER 23 hold bit + 13 + 1 + + + CAN0_HOLD + CAN0 hold bit + 14 + 1 + + + I2C0_HOLD + I2C0 hold bit + 15 + 1 + + + I2C1_HOLD + I2C1 hold bit + 16 + 1 + + + TIMER4_HOLD + TIMER4_HOLD + 18 + 1 + + + TIMER5_HOLD + TIMER 5 hold bit + 19 + 1 + + + TIMER6_HOLD + TIMER 6 hold bit + 20 + 1 + + + CAN1_HOLD + CAN1 hold bit + 21 + 1 + + + + + + + DMA0 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA0_Channel0 + 30 + + + DMA0_Channel1 + 31 + + + DMA0_Channel2 + 32 + + + DMA0_Channel3 + 33 + + + DMA0_Channel4 + 34 + + + DMA0_Channel5 + 35 + + + DMA0_Channel6 + 36 + + + + INTF + INTF + Interrupt flag register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + Global interrupt flag of channel 0 + 0 + 1 + + + FTFIF0 + Full Transfer finish flag of channe 0 + 1 + 1 + + + HTFIF0 + Half transfer finish flag of channel 0 + 2 + 1 + + + ERRIF0 + Error flag of channel 0 + 3 + 1 + + + GIF1 + Global interrupt flag of channel 1 + 4 + 1 + + + FTFIF1 + Full Transfer finish flag of channe 1 + 5 + 1 + + + HTFIF1 + Half transfer finish flag of channel 1 + 6 + 1 + + + ERRIF1 + Error flag of channel 1 + 7 + 1 + + + GIF2 + Global interrupt flag of channel 2 + 8 + 1 + + + FTFIF2 + Full Transfer finish flag of channe 2 + 9 + 1 + + + HTFIF2 + Half transfer finish flag of channel 2 + 10 + 1 + + + ERRIF2 + Error flag of channel 2 + 11 + 1 + + + GIF3 + Global interrupt flag of channel 3 + 12 + 1 + + + FTFIF3 + Full Transfer finish flag of channe 3 + 13 + 1 + + + HTFIF3 + Half transfer finish flag of channel 3 + 14 + 1 + + + ERRIF3 + Error flag of channel 3 + 15 + 1 + + + GIF4 + Global interrupt flag of channel 4 + 16 + 1 + + + FTFIF4 + Full Transfer finish flag of channe 4 + 17 + 1 + + + HTFIF4 + Half transfer finish flag of channel 4 + 18 + 1 + + + ERRIF4 + Error flag of channel 4 + 19 + 1 + + + GIF5 + Global interrupt flag of channel 5 + 20 + 1 + + + FTFIF5 + Full Transfer finish flag of channe 5 + 21 + 1 + + + HTFIF5 + Half transfer finish flag of channel 5 + 22 + 1 + + + ERRIF5 + Error flag of channel 5 + 23 + 1 + + + GIF6 + Global interrupt flag of channel 6 + 24 + 1 + + + FTFIF6 + Full Transfer finish flag of channe 6 + 25 + 1 + + + HTFIF6 + Half transfer finish flag of channel 6 + 26 + 1 + + + ERRIF6 + Error flag of channel 6 + 27 + 1 + + + + + INTC + INTC + Interrupt flag clear register + 0x04 + 0x20 + write-only + 0x00000000 + + + GIFC0 + Clear global interrupt flag of channel 0 + 0 + 1 + + + FTFIFC0 + Clear bit for full transfer finish flag of channel 0 + 1 + 1 + + + HTFIFC0 + Clear bit for half transfer finish flag of channel 0 + 2 + 1 + + + ERRIFC0 + Clear bit for error flag of channel 0 + 3 + 1 + + + GIFC1 + Clear global interrupt flag of channel 1 + 4 + 1 + + + FTFIFC1 + Clear bit for full transfer finish flag of channel 1 + 5 + 1 + + + HTFIFC1 + Clear bit for half transfer finish flag of channel 1 + 6 + 1 + + + ERRIFC1 + Clear bit for error flag of channel 1 + 7 + 1 + + GIFC2 + Clear global interrupt flag of channel 2 + 8 + 1 + + + FTFIFC2 + Clear bit for full transfer finish flag of channel 2 + 9 + 1 + + + HTFIFC2 + Clear bit for half transfer finish flag of channel 2 + 10 + 1 + + + ERRIFC2 + Clear bit for error flag of channel 2 + 11 + 1 + + GIFC3 + Clear global interrupt flag of channel 3 + 12 + 1 + + + FTFIFC3 + Clear bit for full transfer finish flag of channel 3 + 13 + 1 + + + HTFIFC3 + Clear bit for half transfer finish flag of channel 3 + 14 + 1 + + + ERRIFC3 + Clear bit for error flag of channel 3 + 15 + 1 + + GIFC4 + Clear global interrupt flag of channel 4 + 16 + 1 + + + FTFIFC4 + Clear bit for full transfer finish flag of channel 4 + 17 + 1 + + + HTFIFC4 + Clear bit for half transfer finish flag of channel 4 + 18 + 1 + + + ERRIFC4 + Clear bit for error flag of channel 4 + 19 + 1 + + GIFC5 + Clear global interrupt flag of channel 5 + 20 + 1 + + + FTFIFC5 + Clear bit for full transfer finish flag of channel 5 + 21 + 1 + + + HTFIFC5 + Clear bit for half transfer finish flag of channel 5 + 22 + 1 + + + ERRIFC5 + Clear bit for error flag of channel 5 + 23 + 1 + + GIFC6 + Clear global interrupt flag of channel 6 + 24 + 1 + + + FTFIFC6 + Clear bit for full transfer finish flag of channel 6 + 25 + 1 + + + HTFIFC6 + Clear bit for half transfer finish flag of channel 6 + 26 + 1 + + + ERRIFC6 + Clear bit for error flag of channel 6 + 27 + 1 + + + + + CH0CTL + CH0CTL + Channel 0 control register + 0x08 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH0CNT + CH0CNT + Channel 0 counter register + 0x0C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH0PADDR + CH0PADDR + Channel 0 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH0MADDR + CH0MADDR + Channel 0 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH1CTL + CH1CTL + Channel 1 control register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH1CNT + CH1CNT + Channel 1 counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH1PADDR + CH1PADDR + Channel 1 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH1MADDR + CH1MADDR + Channel 1 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH2CTL + CH2CTL + Channel 2 control register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH2CNT + CH2CNT + Channel 2 counter register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH2PADDR + CH2PADDR + Channel 2 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH2MADDR + CH2MADDR + Channel 2 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH3CTL + CH3CTL + Channel 3 control register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH3CNT + CH3CNT + Channel 3 counter register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH3PADDR + CH3PADDR + Channel 3 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH3MADDR + CH3MADDR + Channel 3 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH4CTL + CH4CTL + Channel 4 control register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH4CNT + CH4CNT + Channel 4 counter register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH4PADDR + CH4PADDR + Channel 4 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH4MADDR + CH4MADDR + Channel 4 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH5CTL + CH5CTL + Channel 5 control register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH5CNT + CH5CNT + Channel 5 counter register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH5PADDR + CH5PADDR + Channel 5 peripheral base address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH5MADDR + CH5MADDR + Channel 5 memory base address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH6CTL + CH6CTL + Channel 6 control register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH6CNT + CH6CNT + Channel 6 counter register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH6PADDR + CH6PADDR + Channel 6 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH6MADDR + CH6MADDR + Channel 6 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + + + DMA1 + Direct memory access controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + 0x40020400 + + DMA1_Channel0 + 75 + + + DMA1_Channel1 + 76 + + + DMA1_Channel2 + 77 + + + DMA1_Channel3 + 78 + + + DMA1_Channel4 + 79 + + + + INTF + INTF + Interrupt flag register + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + Global interrupt flag of channel 0 + 0 + 1 + + + FTFIF0 + Full Transfer finish flag of channe 0 + 1 + 1 + + + HTFIF0 + Half transfer finish flag of channel 0 + 2 + 1 + + + ERRIF0 + Error flag of channel 0 + 3 + 1 + + + GIF1 + Global interrupt flag of channel 1 + 4 + 1 + + + FTFIF1 + Full Transfer finish flag of channe 1 + 5 + 1 + + + HTFIF1 + Half transfer finish flag of channel 1 + 6 + 1 + + + ERRIF1 + Error flag of channel 1 + 7 + 1 + + + GIF2 + Global interrupt flag of channel 2 + 8 + 1 + + + FTFIF2 + Full Transfer finish flag of channe 2 + 9 + 1 + + + HTFIF2 + Half transfer finish flag of channel 2 + 10 + 1 + + + ERRIF2 + Error flag of channel 2 + 11 + 1 + + + GIF3 + Global interrupt flag of channel 3 + 12 + 1 + + + FTFIF3 + Full Transfer finish flag of channe 3 + 13 + 1 + + + HTFIF3 + Half transfer finish flag of channel 3 + 14 + 1 + + + ERRIF3 + Error flag of channel 3 + 15 + 1 + + + GIF4 + Global interrupt flag of channel 4 + 16 + 1 + + + FTFIF4 + Full Transfer finish flag of channe 4 + 17 + 1 + + + HTFIF4 + Half transfer finish flag of channel 4 + 18 + 1 + + + ERRIF4 + Error flag of channel 4 + 19 + 1 + + + + + INTC + INTC + Interrupt flag clear register + 0x04 + 0x20 + write-only + 0x00000000 + + + GIFC0 + Clear global interrupt flag of channel 0 + 0 + 1 + + + FTFIFC0 + Clear bit for full transfer finish flag of channel 0 + 1 + 1 + + + HTFIFC0 + Clear bit for half transfer finish flag of channel 0 + 2 + 1 + + + ERRIFC0 + Clear bit for error flag of channel 0 + 3 + 1 + + + GIFC1 + Clear global interrupt flag of channel 1 + 4 + 1 + + + FTFIFC1 + Clear bit for full transfer finish flag of channel 1 + 5 + 1 + + + HTFIFC1 + Clear bit for half transfer finish flag of channel 1 + 6 + 1 + + + ERRIFC1 + Clear bit for error flag of channel 1 + 7 + 1 + + GIFC2 + Clear global interrupt flag of channel 2 + 8 + 1 + + + FTFIFC2 + Clear bit for full transfer finish flag of channel 2 + 9 + 1 + + + HTFIFC2 + Clear bit for half transfer finish flag of channel 2 + 10 + 1 + + + ERRIFC2 + Clear bit for error flag of channel 2 + 11 + 1 + + GIFC3 + Clear global interrupt flag of channel 3 + 12 + 1 + + + FTFIFC3 + Clear bit for full transfer finish flag of channel 3 + 13 + 1 + + + HTFIFC3 + Clear bit for half transfer finish flag of channel 3 + 14 + 1 + + + ERRIFC3 + Clear bit for error flag of channel 3 + 15 + 1 + + GIFC4 + Clear global interrupt flag of channel 4 + 16 + 1 + + + FTFIFC4 + Clear bit for full transfer finish flag of channel 4 + 17 + 1 + + + HTFIFC4 + Clear bit for half transfer finish flag of channel 4 + 18 + 1 + + + ERRIFC4 + Clear bit for error flag of channel 4 + 19 + 1 + + + + + CH0CTL + CH0CTL + Channel 0 control register + 0x08 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH0CNT + CH0CNT + Channel 0 counter register + 0x0C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH0PADDR + CH0PADDR + Channel 0 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH0MADDR + CH0MADDR + Channel 0 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH1CTL + CH1CTL + Channel 1 control register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH1CNT + CH1CNT + Channel 1 counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH1PADDR + CH1PADDR + Channel 1 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH1MADDR + CH1MADDR + Channel 1 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH2CTL + CH2CTL + Channel 2 control register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH2CNT + CH2CNT + Channel 2 counter register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH2PADDR + CH2PADDR + Channel 2 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH2MADDR + CH2MADDR + Channel 2 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH3CTL + CH3CTL + Channel 3 control register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH3CNT + CH3CNT + Channel 3 counter register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH3PADDR + CH3PADDR + Channel 3 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH3MADDR + CH3MADDR + Channel 3 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + CH4CTL + CH4CTL + Channel 4 control register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Enable bit for channel full transfer finish interrupt + 1 + 1 + + + HTFIE + Enable bit for channel half transfer finish interrupt + 2 + 1 + + + ERRIE + Enable bit for channel error interrupt + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority level + 12 + 2 + + + M2M + Memory to Memory Mode + 14 + 1 + + + + + CH4CNT + CH4CNT + Channel 4 counter register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH4PADDR + CH4PADDR + Channel 4 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH4MADDR + CH4MADDR + Channel 4 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory base address + 0 + 32 + + + + + + + EXMC + External memory controller + EXMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + + SNCTL0 + SNCTL0 + SRAM/NOR flash control register 0 + 0x0 + 0x20 + read-write + 0x000030DA + + + ASYNCWAIT + Asynchronous wait + 15 + 1 + + + NRWTEN + NWAIT signal enable + 13 + 1 + + + WREN + Write enable + 12 + 1 + + + NRWTPOL + NWAIT signal polarity + 9 + 1 + + + NREN + NOR Flash access enable + 6 + 1 + + + NRW + NOR bank memory data bus width + 4 + 2 + + + NRTP + NOR bank memory type + 2 + 2 + + + NRMUX + NOR bank memory address/data multiplexing + 1 + 1 + + + NRBKEN + NOR bank enable + 0 + 1 + + + + + SNTCFG0 + SNTCFG0 + SRAM/NOR flash timing configuration register 0 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + BUSLAT + Bus latency + 16 + 4 + + + DSET + Data setup time + 8 + 8 + + + AHLD + Address hold time + 4 + 4 + + + ASET + Address setup time + 0 + 4 + + + + + SNCTL1 + SNCTL1 + SRAM/NOR flash control register 1 + 0x8 + 0x20 + read-write + 0x000030DA + + + ASYNCWAIT + Asynchronous wait + 15 + 1 + + + NRWTEN + NWAIT signal enable + 13 + 1 + + + WREN + Write enable + 12 + 1 + + + NRWTPOL + NWAIT signal polarity + 9 + 1 + + + NREN + NOR Flash access enable + 6 + 1 + + + NRW + NOR bank memory data bus width + 4 + 2 + + + NRTP + NOR bank memory type + 2 + 2 + + + NRMUX + NOR bank memory address/data multiplexing + 1 + 1 + + + NRBKEN + NOR bank enable + 0 + 1 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + EXTI_Line0 + 25 + + + EXTI_Line1 + 26 + + + EXTI_Line2 + 27 + + + EXTI_Line3 + 28 + + + EXTI_Line4 + 29 + + + EXTI_line9_5 + 42 + + + EXTI_line15_10 + 59 + + + + INTEN + INTEN + Interrupt enable register + (EXTI_INTEN) + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Enable Interrupt on line 0 + 0 + 1 + + + INTEN1 + Enable Interrupt on line 1 + 1 + 1 + + + INTEN2 + Enable Interrupt on line 2 + 2 + 1 + + + INTEN3 + Enable Interrupt on line 3 + 3 + 1 + + + INTEN4 + Enable Interrupt on line 4 + 4 + 1 + + + INTEN5 + Enable Interrupt on line 5 + 5 + 1 + + + INTEN6 + Enable Interrupt on line 6 + 6 + 1 + + + INTEN7 + Enable Interrupt on line 7 + 7 + 1 + + + INTEN8 + Enable Interrupt on line 8 + 8 + 1 + + + INTEN9 + Enable Interrupt on line 9 + 9 + 1 + + + INTEN10 + Enable Interrupt on line 10 + 10 + 1 + + + INTEN11 + Enable Interrupt on line 11 + 11 + 1 + + + INTEN12 + Enable Interrupt on line 12 + 12 + 1 + + + INTEN13 + Enable Interrupt on line 13 + 13 + 1 + + + INTEN14 + Enable Interrupt on line 14 + 14 + 1 + + + INTEN15 + Enable Interrupt on line 15 + 15 + 1 + + + INTEN16 + Enable Interrupt on line 16 + 16 + 1 + + + INTEN17 + Enable Interrupt on line 17 + 17 + 1 + + + INTEN18 + Enable Interrupt on line 18 + 18 + 1 + + + + + EVEN + EVEN + Event enable register (EXTI_EVEN) + 0x04 + 0x20 + read-write + 0x00000000 + + + EVEN0 + Enable Event on line 0 + 0 + 1 + + + EVEN1 + Enable Event on line 1 + 1 + 1 + + + EVEN2 + Enable Event on line 2 + 2 + 1 + + + EVEN3 + Enable Event on line 3 + 3 + 1 + + + EVEN4 + Enable Event on line 4 + 4 + 1 + + + EVEN5 + Enable Event on line 5 + 5 + 1 + + + EVEN6 + Enable Event on line 6 + 6 + 1 + + + EVEN7 + Enable Event on line 7 + 7 + 1 + + + EVEN8 + Enable Event on line 8 + 8 + 1 + + + EVEN9 + Enable Event on line 9 + 9 + 1 + + + EVEN10 + Enable Event on line 10 + 10 + 1 + + + EVEN11 + Enable Event on line 11 + 11 + 1 + + + EVEN12 + Enable Event on line 12 + 12 + 1 + + + EVEN13 + Enable Event on line 13 + 13 + 1 + + + EVEN14 + Enable Event on line 14 + 14 + 1 + + + EVEN15 + Enable Event on line 15 + 15 + 1 + + + EVEN16 + Enable Event on line 16 + 16 + 1 + + + EVEN17 + Enable Event on line 17 + 17 + 1 + + + EVEN18 + Enable Event on line 18 + 18 + 1 + + + + + RTEN + RTEN + Rising Edge Trigger Enable register + (EXTI_RTEN) + 0x08 + 0x20 + read-write + 0x00000000 + + + RTEN0 + Rising edge trigger enable of + line 0 + 0 + 1 + + + RTEN1 + Rising edge trigger enable of + line 1 + 1 + 1 + + + RTEN2 + Rising edge trigger enable of + line 2 + 2 + 1 + + + RTEN3 + Rising edge trigger enable of + line 3 + 3 + 1 + + + RTEN4 + Rising edge trigger enable of + line 4 + 4 + 1 + + + RTEN5 + Rising edge trigger enable of + line 5 + 5 + 1 + + + RTEN6 + Rising edge trigger enable of + line 6 + 6 + 1 + + + RTEN7 + Rising edge trigger enable of + line 7 + 7 + 1 + + + RTEN8 + Rising edge trigger enable of + line 8 + 8 + 1 + + + RTEN9 + Rising edge trigger enable of + line 9 + 9 + 1 + + + RTEN10 + Rising edge trigger enable of + line 10 + 10 + 1 + + + RTEN11 + Rising edge trigger enable of + line 11 + 11 + 1 + + + RTEN12 + Rising edge trigger enable of + line 12 + 12 + 1 + + + RTEN13 + Rising edge trigger enable of + line 13 + 13 + 1 + + + RTEN14 + Rising edge trigger enable of + line 14 + 14 + 1 + + + RTEN15 + Rising edge trigger enable of + line 15 + 15 + 1 + + + RTEN16 + Rising edge trigger enable of + line 16 + 16 + 1 + + + RTEN17 + Rising edge trigger enable of + line 17 + 17 + 1 + + + RTEN18 + Rising edge trigger enable of + line 18 + 18 + 1 + + + + + FTEN + FTEN + Falling Egde Trigger Enable register + (EXTI_FTEN) + 0x0C + 0x20 + read-write + 0x00000000 + + + FTEN0 + Falling edge trigger enable of + line 0 + 0 + 1 + + + FTEN1 + Falling edge trigger enable of + line 1 + 1 + 1 + + + FTEN2 + Falling edge trigger enable of + line 2 + 2 + 1 + + + FTEN3 + Falling edge trigger enable of + line 3 + 3 + 1 + + + FTEN4 + Falling edge trigger enable of + line 4 + 4 + 1 + + + FTEN5 + Falling edge trigger enable of + line 5 + 5 + 1 + + + FTEN6 + Falling edge trigger enable of + line 6 + 6 + 1 + + + FTEN7 + Falling edge trigger enable of + line 7 + 7 + 1 + + + FTEN8 + Falling edge trigger enable of + line 8 + 8 + 1 + + + FTEN9 + Falling edge trigger enable of + line 9 + 9 + 1 + + + FTEN10 + Falling edge trigger enable of + line 10 + 10 + 1 + + + FTEN11 + Falling edge trigger enable of + line 11 + 11 + 1 + + + FTEN12 + Falling edge trigger enable of + line 12 + 12 + 1 + + + FTEN13 + Falling edge trigger enable of + line 13 + 13 + 1 + + + FTEN14 + Falling edge trigger enable of + line 14 + 14 + 1 + + + FTEN15 + Falling edge trigger enable of + line 15 + 15 + 1 + + + FTEN16 + Falling edge trigger enable of + line 16 + 16 + 1 + + + FTEN17 + Falling edge trigger enable of + line 17 + 17 + 1 + + + FTEN18 + Falling edge trigger enable of + line 18 + 18 + 1 + + + + + SWIEV + SWIEV + Software interrupt event register + (EXTI_SWIEV) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIEV0 + Interrupt/Event software trigger on line + 0 + 0 + 1 + + + SWIEV1 + Interrupt/Event software trigger on line + 1 + 1 + 1 + + + SWIEV2 + Interrupt/Event software trigger on line + 2 + 2 + 1 + + + SWIEV3 + Interrupt/Event software trigger on line + 3 + 3 + 1 + + + SWIEV4 + Interrupt/Event software trigger on line + 4 + 4 + 1 + + + SWIEV5 + Interrupt/Event software trigger on line + 5 + 5 + 1 + + + SWIEV6 + Interrupt/Event software trigger on line + 6 + 6 + 1 + + + SWIEV7 + Interrupt/Event software trigger on line + 7 + 7 + 1 + + + SWIEV8 + Interrupt/Event software trigger on line + 8 + 8 + 1 + + + SWIEV9 + Interrupt/Event software trigger on line + 9 + 9 + 1 + + + SWIEV10 + Interrupt/Event software trigger on line + 10 + 10 + 1 + + + SWIEV11 + Interrupt/Event software trigger on line + 11 + 11 + 1 + + + SWIEV12 + Interrupt/Event software trigger on line + 12 + 12 + 1 + + + SWIEV13 + Interrupt/Event software trigger on line + 13 + 13 + 1 + + + SWIEV14 + Interrupt/Event software trigger on line + 14 + 14 + 1 + + + SWIEV15 + Interrupt/Event software trigger on line + 15 + 15 + 1 + + + SWIEV16 + Interrupt/Event software trigger on line + 16 + 16 + 1 + + + SWIEV17 + Interrupt/Event software trigger on line + 17 + 17 + 1 + + + SWIEV18 + Interrupt/Event software trigger on line + 18 + 18 + 1 + + + + + PD + PD + Pending register (EXTI_PD) + 0x14 + 0x20 + read-write + 0x00000000 + + + PD0 + Interrupt pending status of line 0 + 0 + 1 + + + PD1 + Interrupt pending status of line 1 + 1 + 1 + + + PD2 + Interrupt pending status of line 2 + 2 + 1 + + + PD3 + Interrupt pending status of line 3 + 3 + 1 + + + PD4 + Interrupt pending status of line 4 + 4 + 1 + + + PD5 + Interrupt pending status of line 5 + 5 + 1 + + + PD6 + Interrupt pending status of line 6 + 6 + 1 + + + PD7 + Interrupt pending status of line 7 + 7 + 1 + + + PD8 + Interrupt pending status of line 8 + 8 + 1 + + + PD9 + Interrupt pending status of line 9 + 9 + 1 + + + PD10 + Interrupt pending status of line 10 + 10 + 1 + + + PD11 + Interrupt pending status of line 11 + 11 + 1 + + + PD12 + Interrupt pending status of line 12 + 12 + 1 + + + PD13 + Interrupt pending status of line 13 + 13 + 1 + + + PD14 + Interrupt pending status of line 14 + 14 + 1 + + + PD15 + Interrupt pending status of line 15 + 15 + 1 + + + PD16 + Interrupt pending status of line 16 + 16 + 1 + + + PD17 + Interrupt pending status of line 17 + 17 + 1 + + + PD18 + Interrupt pending status of line 18 + 18 + 1 + + + + + + + FMC + FMC + FMC + 0x40022000 + + 0x0 + 0x400 + registers + + + FMC + 23 + + + + WS + WS + wait state counter register + 0x0 + 0x20 + read-write + 0x00000000 + + + WSCNT + wait state counter register + 0 + 3 + + + + + KEY0 + KEY0 + Unlock key register 0 + 0x04 + 0x20 + write-only + 0x00000000 + + + KEY + FMC_CTL0 unlock key + 0 + 32 + + + + + OBKEY + OBKEY + Option byte unlock key register + 0x08 + 0x20 + write-only + 0x00000000 + + + OBKEY + FMC_ CTL0 option byte operation unlock register + 0 + 32 + + + + + STAT0 + STAT0 + Status register 0 + 0x0C + 0x20 + 0x00000000 + + + ENDF + End of operation flag bit + 5 + 1 + read-write + + + WPERR + Erase/Program protection error flag bit + 4 + 1 + read-write + + + PGERR + Program error flag bit + 2 + 1 + read-write + + + BUSY + The flash is busy bit + 0 + 1 + read-only + + + + + CTL0 + CTL0 + Control register 0 + 0x10 + 0x20 + read-write + 0x00000080 + + + ENDIE + End of operation interrupt enable bit + 12 + 1 + + + ERRIE + Error interrupt enable bit + 10 + 1 + + + OBWEN + Option byte erase/program enable bit + 9 + 1 + + + LK + FMC_CTL0 lock bit + 7 + 1 + + + START + Send erase command to FMC bit + 6 + 1 + + + OBER + Option bytes erase command bit + 5 + 1 + + + OBPG + Option bytes program command bit + 4 + 1 + + + MER + Main flash mass erase for bank0 command bit + 2 + 1 + + + PER + Main flash page erase for bank0 command bit + 1 + 1 + + + PG + Main flash program for bank0 command bit + 0 + 1 + + + + + ADDR0 + ADDR0 + Address register 0 + 0x14 + 0x20 + write-only + 0x00000000 + + + ADDR + Flash erase/program command address bits + 0 + 32 + + + + + OBSTAT + OBSTAT + Option byte status register + 0x1C + 0x20 + read-only + 0x00000000 + + + OBERR + Option bytes read error bit + 0 + 1 + + + SPC + Option bytes security protection code + 1 + 1 + + + USER + Store USER of option bytes block after system reset + 2 + 8 + + + DATA + Store DATA[15:0] of option bytes block after system reset + 10 + 16 + + + + + WP + WP + Erase/Program Protection register + 0x20 + 0x20 + read-only + 0x00000000 + + + WP + Store WP[31:0] of option bytes block after system reset + 0 + 32 + + + + + PID + PID + Product ID register + 0x100 + 0x20 + read-only + 0x00000000 + + + PID + Product reserved ID code register + 0 + 32 + + + + + + + FWDGT + free watchdog timer + FWDGT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CTL + CTL + Control register + 0x00 + 0x20 + write-only + 0x00000000 + + + CMD + Key value + 0 + 16 + + + + + PSC + PSC + Prescaler register + 0x04 + 0x20 + read-write + 0x00000000 + + + PSC + Free watchdog timer prescaler selection + 0 + 3 + + + + + RLD + RLD + Reload register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RLD + Free watchdog timer counter reload value + 0 + 12 + + + + + STAT + STAT + Status register + 0x0C + 0x20 + read-only + 0x00000000 + + + PUD + Free watchdog timer prescaler value update + 0 + 1 + + + RUD + Free watchdog timer counter reload value update + 1 + 1 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CTL0 + CTL0 + port control register 0 + 0x0 + 0x20 + read-write + 0x44444444 + + + CTL7 + Port x configuration bits (x = + 7) + 30 + 2 + + + MD7 + Port x mode bits (x = + 7) + 28 + 2 + + + CTL6 + Port x configuration bits (x = + 6) + 26 + 2 + + + MD6 + Port x mode bits (x = + 6) + 24 + 2 + + + CTL5 + Port x configuration bits (x = + 5) + 22 + 2 + + + MD5 + Port x mode bits (x = + 5) + 20 + 2 + + + CTL4 + Port x configuration bits (x = + 4) + 18 + 2 + + + MD4 + Port x mode bits (x = + 4) + 16 + 2 + + + CTL3 + Port x configuration bits (x = + 3) + 14 + 2 + + + MD3 + Port x mode bits (x = + 3 ) + 12 + 2 + + + CTL2 + Port x configuration bits (x = + 2) + 10 + 2 + + + MD2 + Port x mode bits (x = + 2 ) + 8 + 2 + + + CTL1 + Port x configuration bits (x = + 1) + 6 + 2 + + + MD1 + Port x mode bits (x = + 1) + 4 + 2 + + + CTL0 + Port x configuration bits (x = + 0) + 2 + 2 + + + MD0 + Port x mode bits (x = + 0) + 0 + 2 + + + + + CTL1 + CTL1 + port control register 1 + 0x04 + 0x20 + read-write + 0x44444444 + + + CTL15 + Port x configuration bits (x = + 15) + 30 + 2 + + + MD15 + Port x mode bits (x = + 15) + 28 + 2 + + + CTL14 + Port x configuration bits (x = + 14) + 26 + 2 + + + MD14 + Port x mode bits (x = + 14) + 24 + 2 + + + CTL13 + Port x configuration bits (x = + 13) + 22 + 2 + + + MD13 + Port x mode bits (x = + 13) + 20 + 2 + + + CTL12 + Port x configuration bits (x = + 12) + 18 + 2 + + + MD12 + Port x mode bits (x = + 12) + 16 + 2 + + + CTL11 + Port x configuration bits (x = + 11) + 14 + 2 + + + MD11 + Port x mode bits (x = + 11 ) + 12 + 2 + + + CTL10 + Port x configuration bits (x = + 10) + 10 + 2 + + + MD10 + Port x mode bits (x = + 10 ) + 8 + 2 + + + CTL9 + Port x configuration bits (x = + 9) + 6 + 2 + + + MD9 + Port x mode bits (x = + 9) + 4 + 2 + + + CTL8 + Port x configuration bits (x = + 8) + 2 + 2 + + + MD8 + Port x mode bits (x = + 8) + 0 + 2 + + + + + ISTAT + ISTAT + Port input status register + 0x08 + 0x20 + read-only + 0x00000000 + + + ISTAT15 + Port input status + 15 + 1 + + + ISTAT14 + Port input status + 14 + 1 + + + ISTAT13 + Port input status + 13 + 1 + + + ISTAT12 + Port input status + 12 + 1 + + + ISTAT11 + Port input status + 11 + 1 + + + ISTAT10 + Port input status + 10 + 1 + + + ISTAT9 + Port input status + 9 + 1 + + + ISTAT8 + Port input status + 8 + 1 + + + ISTAT7 + Port input status + 7 + 1 + + + ISTAT6 + Port input status + 6 + 1 + + + ISTAT5 + Port input status + 5 + 1 + + + ISTAT4 + Port input status + 4 + 1 + + + ISTAT3 + Port input status + 3 + 1 + + + ISTAT2 + Port input status + 2 + 1 + + + ISTAT1 + Port input status + 1 + 1 + + + ISTAT0 + Port input status + 0 + 1 + + + + + OCTL + OCTL + Port output control register + 0x0C + 0x20 + read-write + 0x00000000 + + + OCTL15 + Port output control + 15 + 1 + + + OCTL14 + Port output control + 14 + 1 + + + OCTL13 + Port output control + 13 + 1 + + + OCTL12 + Port output control + 12 + 1 + + + OCTL11 + Port output control + 11 + 1 + + + OCTL10 + Port output control + 10 + 1 + + + OCTL9 + Port output control + 9 + 1 + + + OCTL8 + Port output control + 8 + 1 + + + OCTL7 + Port output control + 7 + 1 + + + OCTL6 + Port output control + 6 + 1 + + + OCTL5 + Port output control + 5 + 1 + + + OCTL4 + Port output control + 4 + 1 + + + OCTL3 + Port output control + 3 + 1 + + + OCTL2 + Port output control + 2 + 1 + + + OCTL1 + Port output control + 1 + 1 + + + OCTL0 + Port output control + 0 + 1 + + + + + BOP + BOP + Port bit operate register + 0x10 + 0x20 + write-only + 0x00000000 + + + CR15 + Port 15 Clear bit + 31 + 1 + + + CR14 + Port 14 Clear bit + 30 + 1 + + + CR13 + Port 13 Clear bit + 29 + 1 + + + CR12 + Port 12 Clear bit + 28 + 1 + + + CR11 + Port 11 Clear bit + 27 + 1 + + + CR10 + Port 10 Clear bit + 26 + 1 + + + CR9 + Port 9 Clear bit + 25 + 1 + + + CR8 + Port 8 Clear bit + 24 + 1 + + + CR7 + Port 7 Clear bit + 23 + 1 + + + CR6 + Port 6 Clear bit + 22 + 1 + + + CR5 + Port 5 Clear bit + 21 + 1 + + + CR4 + Port 4 Clear bit + 20 + 1 + + + CR3 + Port 3 Clear bit + 19 + 1 + + + CR2 + Port 2 Clear bit + 18 + 1 + + + CR1 + Port 1 Clear bit + 17 + 1 + + + CR0 + Port 0 Clear bit + 16 + 1 + + + BOP15 + Port 15 Set bit + 15 + 1 + + + BOP14 + Port 14 Set bit + 14 + 1 + + + BOP13 + Port 13 Set bit + 13 + 1 + + + BOP12 + Port 12 Set bit + 12 + 1 + + + BOP11 + Port 11 Set bit + 11 + 1 + + + BOP10 + Port 10 Set bit + 10 + 1 + + + BOP9 + Port 9 Set bit + 9 + 1 + + + BOP8 + Port 8 Set bit + 8 + 1 + + + BOP7 + Port 7 Set bit + 7 + 1 + + + BOP6 + Port 6 Set bit + 6 + 1 + + + BOP5 + Port 5 Set bit + 5 + 1 + + + BOP4 + Port 4 Set bit + 4 + 1 + + + BOP3 + Port 3 Set bit + 3 + 1 + + + BOP2 + Port 2 Set bit + 2 + 1 + + + BOP1 + Port 1 Set bit + 1 + 1 + + + BOP0 + Port 0 Set bit + 0 + 1 + + + + + BC + BC + Port bit clear register + 0x14 + 0x20 + write-only + 0x00000000 + + + CR15 + Port 15 Clear bit + 15 + 1 + + + CR14 + Port 14 Clear bit + 14 + 1 + + + CR13 + Port 13 Clear bit + 13 + 1 + + + CR12 + Port 12 Clear bit + 12 + 1 + + + CR11 + Port 11 Clear bit + 11 + 1 + + + CR10 + Port 10 Clear bit + 10 + 1 + + + CR9 + Port 9 Clear bit + 9 + 1 + + + CR8 + Port 8 Clear bit + 8 + 1 + + + CR7 + Port 7 Clear bit + 7 + 1 + + + CR6 + Port 6 Clear bit + 6 + 1 + + + CR5 + Port 5 Clear bit + 5 + 1 + + + CR4 + Port 4 Clear bit + 4 + 1 + + + CR3 + Port 3 Clear bit + 3 + 1 + + + CR2 + Port 2 Clear bit + 2 + 1 + + + CR1 + Port 1 Clear bit + 1 + 1 + + + CR0 + Port 0 Clear bit + 0 + 1 + + + + + LOCK + LOCK + GPIO port configuration lock + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LKK + Lock sequence key + + 16 + 1 + + + LK15 + Port Lock bit 15 + 15 + 1 + + + LK14 + Port Lock bit 14 + 14 + 1 + + + LK13 + Port Lock bit 13 + 13 + 1 + + + LK12 + Port Lock bit 12 + 12 + 1 + + + LK11 + Port Lock bit 11 + 11 + 1 + + + LK10 + Port Lock bit 10 + 10 + 1 + + + LK9 + Port Lock bit 9 + 9 + 1 + + + LK8 + Port Lock bit 8 + 8 + 1 + + + LK7 + Port Lock bit 7 + 7 + 1 + + + LK6 + Port Lock bit 6 + 6 + 1 + + + LK5 + Port Lock bit 5 + 5 + 1 + + + LK4 + Port Lock bit 4 + 4 + 1 + + + LK3 + Port Lock bit 3 + 3 + 1 + + + LK2 + Port Lock bit 2 + 2 + 1 + + + LK1 + Port Lock bit 1 + 1 + 1 + + + LK0 + Port Lock bit 0 + 0 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + I2C0 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C0_EV + 50 + + + I2C0_ER + 51 + + + + CTL0 + CTL0 + Control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + SRESET + Software reset + 15 + 1 + + + SALT + SMBus alert + 13 + 1 + + + PECTRANS + PEC Transfer + 12 + 1 + + + POAP + Position of ACK and PEC when receiving + 11 + 1 + + + ACKEN + Whether or not to send an ACK + 10 + 1 + + + STOP + Generate a STOP condition on I2C bus + 9 + 1 + + + START + Generate a START condition on I2C bus + 8 + 1 + + + SS + Whether to stretch SCL low when data is not ready in slave mode + 7 + 1 + + + GCEN + Whether or not to response to a General Call (0x00) + 6 + 1 + + + PECEN + PEC Calculation Switch + 5 + 1 + + + ARPEN + ARP protocol in SMBus switch + 4 + 1 + + + SMBSEL + SMBusType Selection + 3 + 1 + + + SMBEN + SMBus/I2C mode switch + 1 + 1 + + + I2CEN + I2C peripheral enable + 0 + 1 + + + + + CTL1 + CTL1 + Control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + DMALST + Flag indicating DMA last transfer + 12 + 1 + + + DMAON + DMA mode switch + 11 + 1 + + + BUFIE + Buffer interrupt enable + 10 + 1 + + + EVIE + Event interrupt enable + 9 + 1 + + + ERRIE + Error interrupt enable + 8 + 1 + + + I2CCLK + I2C Peripheral clock frequency + 0 + 6 + + + + + SADDR0 + SADDR0 + Slave address register 0 + 0x08 + 0x10 + read-write + 0x0000 + + + ADDFORMAT + Address mode for the I2C slave + 15 + 1 + + + ADDRESS9_8 + Highest two bits of a 10-bit address + 8 + 2 + + + ADDRESS7_1 + 7-bit address or bits 7:1 of a 10-bit address + 1 + 7 + + + ADDRESS0 + Bit 0 of a 10-bit address + 0 + 1 + + + + + SADDR1 + SADDR1 + Slave address register 1 + 0x0C + 0x10 + read-write + 0x0000 + + + ADDRESS2 + Second I2C address for the slave in Dual-Address mode + 1 + 7 + + + DUADEN + Dual-Address mode switch + 0 + 1 + + + + + DATA + DATA + Transfer buffer register + 0x10 + 0x10 + read-write + 0x0000 + + + TRB + Transmission or reception data buffer register + 0 + 8 + + + + + STAT0 + STAT0 + Transfer status register 0 + 0x14 + 0x10 + 0x0000 + + + SMBALT + SMBus Alert status + 15 + 1 + read-write + + + SMBTO + Timeout signal in SMBus mode + 14 + 1 + read-write + + + PECERR + PEC error when receiving data + 12 + 1 + read-write + + + OUERR + Over-run or under-run situation occurs in slave mode + 11 + 1 + read-write + + + AERR + Acknowledge error + 10 + 1 + read-write + + + LOSTARB + Arbitration Lost in master mode + 9 + 1 + read-write + + + BERR + A bus error occurs indication a unexpected START or STOP condition on I2C bus + 8 + 1 + read-write + + + TBE + I2C_DATA is Empty during transmitting + 7 + 1 + read-only + + + RBNE + I2C_DATA is not Empty during receiving + 6 + 1 + read-only + + + STPDET + STOP condition detected in slave mode + 4 + 1 + read-only + + + ADD10SEND + Header of 10-bit address is sent in master mode + 3 + 1 + read-only + + + BTC + Byte transmission completed + 2 + 1 + read-only + + + ADDSEND + Address is sent in master mode or received and matches in slave mode + 1 + 1 + read-only + + + SBSEND + START condition sent out in master mode + 0 + 1 + read-only + + + + + STAT1 + STAT1 + Transfer status register 1 + 0x18 + 0x10 + read-only + 0x0000 + + + PECV + Packet Error Checking Value that calculated by hardware when PEC is enabled + 8 + 8 + + + DUMODF + Dual Flag in slave mode + 7 + 1 + + + HSTSMB + SMBus Host Header detected in slave mode + 6 + 1 + + + DEFSMB + Default address of SMBusDevice + 5 + 1 + + + RXGC + General call address (00h) received + 4 + 1 + + + TR + Whether the I2C is a transmitter or a receiver + 2 + 1 + + + I2CBSY + Busy flag + 1 + 1 + + + MASTER + A flag indicating whether I2C block is in master or slave mode + 0 + 1 + + + + + CKCFG + CKCFG + Clock configure register + 0x1C + 0x10 + read-write + 0x0000 + + + FAST + I2C speed selection in master mode + 15 + 1 + + + DTCY + Duty cycle in fast mode + 14 + 1 + + + CLKC + I2C Clock control in master mode + 0 + 12 + + + + + RT + RT + Rise time register + 0x20 + 0x10 + read-write + 0x0002 + + + RISETIME + Maximum rise time in master mode + 0 + 6 + + + + + + + I2C1 + 0x40005800 + + I2C1_EV + 52 + + + I2C1_ER + 53 + + + + + ECLIC + Enhanced Core Local Interrupt Controller + ECLIC + 0xD2000000 + + 0x0 + 0xFFFF + registers + + + + CLICCFG + CLICCFG + cliccfg Register + 0x0 + 0x08 + read-write + 0x00 + + + NLBITS + NLBITS + 1 + 4 + + + + + CLICINFO + CLICINFO + clicinfo Register + 0x04 + 0x20 + read-only + 0x00000000 + + + NUM_INTERRUPT + NUM_INTERRUPT + 0 + 13 + + + VERSION + VERSION + 13 + 8 + + + CLICINTCTLBITS + CLICINTCTLBITS + 21 + 4 + + + + + MTH + MTH + MTH Register + 0x0b + 0x08 + read-write + 0x00 + + + MTH + MTH + 0 + 8 + + + + + CLICINTIP_0 + CLICINTIP_0 + clicintip Register + 0x1000 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_1 + CLICINTIP_1 + clicintip Register + 0x1004 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_2 + CLICINTIP_2 + clicintip Register + 0x1008 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_3 + CLICINTIP_3 + clicintip Register + 0x100C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_4 + CLICINTIP_4 + clicintip Register + 0x1010 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_5 + CLICINTIP_5 + clicintip Register + 0x1014 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_6 + CLICINTIP_6 + clicintip Register + 0x1018 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_7 + CLICINTIP_7 + clicintip Register + 0x101C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_8 + CLICINTIP_8 + clicintip Register + 0x1020 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_9 + CLICINTIP_9 + clicintip Register + 0x1024 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_10 + CLICINTIP_10 + clicintip Register + 0x1028 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_11 + CLICINTIP_11 + clicintip Register + 0x102C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_12 + CLICINTIP_12 + clicintip Register + 0x1030 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_13 + CLICINTIP_13 + clicintip Register + 0x1034 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_14 + CLICINTIP_14 + clicintip Register + 0x1038 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_15 + CLICINTIP_15 + clicintip Register + 0x103C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_16 + CLICINTIP_16 + clicintip Register + 0x1040 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_17 + CLICINTIP_17 + clicintip Register + 0x1044 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_18 + CLICINTIP_18 + clicintip Register + 0x1048 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_19 + CLICINTIP_19 + clicintip Register + 0x104C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_20 + CLICINTIP_20 + clicintip Register + 0x1050 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_21 + CLICINTIP_21 + clicintip Register + 0x1054 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_22 + CLICINTIP_22 + clicintip Register + 0x1058 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_23 + CLICINTIP_23 + clicintip Register + 0x105C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_24 + CLICINTIP_24 + clicintip Register + 0x1060 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_25 + CLICINTIP_25 + clicintip Register + 0x1064 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_26 + CLICINTIP_26 + clicintip Register + 0x1068 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_27 + CLICINTIP_27 + clicintip Register + 0x106C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_28 + CLICINTIP_28 + clicintip Register + 0x1070 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_29 + CLICINTIP_29 + clicintip Register + 0x1074 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_30 + CLICINTIP_30 + clicintip Register + 0x1078 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_31 + CLICINTIP_31 + clicintip Register + 0x107C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_32 + CLICINTIP_32 + clicintip Register + 0x1080 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_33 + CLICINTIP_33 + clicintip Register + 0x1084 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_34 + CLICINTIP_34 + clicintip Register + 0x1088 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_35 + CLICINTIP_35 + clicintip Register + 0x108C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_36 + CLICINTIP_36 + clicintip Register + 0x1090 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_37 + CLICINTIP_37 + clicintip Register + 0x1094 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_38 + CLICINTIP_38 + clicintip Register + 0x1098 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_39 + CLICINTIP_39 + clicintip Register + 0x109C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_40 + CLICINTIP_40 + clicintip Register + 0x10A0 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_41 + CLICINTIP_41 + clicintip Register + 0x10A4 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_42 + CLICINTIP_42 + clicintip Register + 0x10A8 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_43 + CLICINTIP_43 + clicintip Register + 0x10AC + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_44 + CLICINTIP_44 + clicintip Register + 0x10B0 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_45 + CLICINTIP_45 + clicintip Register + 0x10B4 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_46 + CLICINTIP_46 + clicintip Register + 0x10B8 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_47 + CLICINTIP_47 + clicintip Register + 0x10BC + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_48 + CLICINTIP_48 + clicintip Register + 0x10C0 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_49 + CLICINTIP_49 + clicintip Register + 0x10C4 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_50 + CLICINTIP_50 + clicintip Register + 0x10C8 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_51 + CLICINTIP_51 + clicintip Register + 0x10CC + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_52 + CLICINTIP_52 + clicintip Register + 0x10D0 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_53 + CLICINTIP_53 + clicintip Register + 0x10D4 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_54 + CLICINTIP_54 + clicintip Register + 0x10D8 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_55 + CLICINTIP_55 + clicintip Register + 0x10DC + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_56 + CLICINTIP_56 + clicintip Register + 0x10E0 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_57 + CLICINTIP_57 + clicintip Register + 0x10E4 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_58 + CLICINTIP_58 + clicintip Register + 0x10E8 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_59 + CLICINTIP_59 + clicintip Register + 0x10EC + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_60 + CLICINTIP_60 + clicintip Register + 0x10F0 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_61 + CLICINTIP_61 + clicintip Register + 0x10F4 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_62 + CLICINTIP_62 + clicintip Register + 0x10F8 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_63 + CLICINTIP_63 + clicintip Register + 0x10FC + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_64 + CLICINTIP_64 + clicintip Register + 0x1100 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_65 + CLICINTIP_65 + clicintip Register + 0x1104 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_66 + CLICINTIP_66 + clicintip Register + 0x1108 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_67 + CLICINTIP_67 + clicintip Register + 0x110C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_68 + CLICINTIP_68 + clicintip Register + 0x1110 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_69 + CLICINTIP_69 + clicintip Register + 0x1114 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_70 + CLICINTIP_70 + clicintip Register + 0x1118 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_71 + CLICINTIP_71 + clicintip Register + 0x111C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_72 + CLICINTIP_72 + clicintip Register + 0x1120 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_73 + CLICINTIP_73 + clicintip Register + 0x1124 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_74 + CLICINTIP_74 + clicintip Register + 0x1128 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_75 + CLICINTIP_75 + clicintip Register + 0x112C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_76 + CLICINTIP_76 + clicintip Register + 0x1130 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_77 + CLICINTIP_77 + clicintip Register + 0x1134 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_78 + CLICINTIP_78 + clicintip Register + 0x1138 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_79 + CLICINTIP_79 + clicintip Register + 0x113C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_80 + CLICINTIP_80 + clicintip Register + 0x1140 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_81 + CLICINTIP_81 + clicintip Register + 0x1144 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_82 + CLICINTIP_82 + clicintip Register + 0x1148 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_83 + CLICINTIP_83 + clicintip Register + 0x114C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_84 + CLICINTIP_84 + clicintip Register + 0x1150 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_85 + CLICINTIP_85 + clicintip Register + 0x1158 + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIP_86 + CLICINTIP_86 + clicintip Register + 0x115C + 0x08 + read-write + 0x00 + + + IP + IP + 0 + 1 + + + + + CLICINTIE_0 + CLICINTIE_0 + clicintie Register + 0x1001 + 0x08 + read-write + 0x00 + + + IE + IE + 0 + 1 + + + + + CLICINTIE_1 + CLICINTIE_1 + clicintie Register + 0x1005 + 0x08 + read-write + 0x00 + + + IE + IE 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+ + + + + CLICINTATTR_54 + CLICINTIE_54 + clicintattr Register + 0x10DA + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_55 + CLICINTIE_55 + clicintattr Register + 0x10DE + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_56 + CLICINTIE_56 + clicintattr Register + 0x10E2 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_57 + CLICINTIE_57 + clicintattr Register + 0x10E6 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_58 + CLICINTIE_58 + clicintattr Register + 0x10EA + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_59 + CLICINTIE_59 + clicintattr Register + 0x10EE + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_60 + CLICINTIE_60 + clicintattr Register + 0x10F2 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_61 + CLICINTIE_61 + clicintattr Register + 0x10F6 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_62 + CLICINTIE_62 + clicintattr Register + 0x10FA + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_63 + CLICINTIE_63 + clicintattr Register + 0x10FE + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_64 + CLICINTIE_64 + clicintattr Register + 0x1102 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_65 + CLICINTIE_65 + clicintattr Register + 0x1106 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_66 + CLICINTIE_66 + clicintattr Register + 0x110A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_67 + CLICINTIE_67 + clicintattr Register + 0x110E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_68 + CLICINTIE_68 + clicintattr Register + 0x1112 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_69 + CLICINTIE_69 + clicintattr Register + 0x1116 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_70 + CLICINTIE_70 + clicintattr Register + 0x111A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_71 + CLICINTIE_71 + clicintattr Register + 0x111E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_72 + CLICINTIE_72 + clicintattr Register + 0x1122 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_73 + CLICINTIE_73 + clicintattr Register + 0x1126 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_74 + CLICINTIE_74 + clicintattr Register + 0x112A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_75 + CLICINTIE_75 + clicintattr Register + 0x112E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_76 + CLICINTIE_76 + clicintattr Register + 0x1132 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_77 + CLICINTIE_77 + clicintattr Register + 0x1136 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_78 + CLICINTIE_78 + clicintattr Register + 0x113A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_79 + CLICINTIE_79 + clicintattr Register + 0x113E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_80 + CLICINTIE_80 + clicintattr Register + 0x1142 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_81 + CLICINTIE_81 + clicintattr Register + 0x1146 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_82 + CLICINTIE_82 + clicintattr Register + 0x114A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_83 + CLICINTIE_83 + clicintattr Register + 0x114E + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_84 + CLICINTIE_84 + clicintattr Register + 0x1152 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_85 + CLICINTIE_85 + clicintattr Register + 0x1156 + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + CLICINTATTR_86 + CLICINTIE_86 + clicintattr Register + 0x115A + 0x08 + read-write + 0x00 + + + SHV + SHV + 0 + 1 + + + TRIG + TRIG + 1 + 2 + + + + + + CLICINTCTL_0 + CLICINTCTL_0 + clicintctl Register + 0x1003 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_1 + CLICINTCTL_1 + clicintctl Register + 0x1007 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_2 + CLICINTCTL_2 + clicintctl Register + 0x100B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_3 + CLICINTCTL_3 + clicintctl Register + 0x100F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_4 + CLICINTCTL_4 + clicintctl Register + 0x1013 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_5 + CLICINTCTL_5 + clicintctl Register + 0x1017 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_6 + CLICINTCTL_6 + clicintctl Register + 0x101B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_7 + CLICINTCTL_7 + clicintctl Register + 0x101F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_8 + CLICINTCTL_8 + clicintctl Register + 0x1023 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_9 + CLICINTCTL_9 + clicintctl Register + 0x1027 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_10 + CLICINTCTL_10 + clicintctl Register + 0x102B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_11 + CLICINTCTL_11 + clicintctl Register + 0x102F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_12 + CLICINTCTL_12 + clicintctl Register + 0x1033 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_13 + CLICINTCTL_13 + clicintctl Register + 0x1037 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_14 + CLICINTCTL_14 + clicintctl Register + 0x103B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_15 + CLICINTCTL_15 + clicintctl Register + 0x103F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_16 + CLICINTCTL_16 + clicintctl Register + 0x1043 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_17 + CLICINTCTL_17 + clicintctl Register + 0x1047 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_18 + CLICINTCTL_18 + clicintctl Register + 0x104B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_19 + CLICINTCTL_19 + clicintctl Register + 0x104F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_20 + CLICINTCTL_20 + clicintctl Register + 0x1053 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_21 + CLICINTCTL_21 + clicintctl Register + 0x1057 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_22 + CLICINTCTL_22 + clicintctl Register + 0x105B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_23 + CLICINTCTL_23 + clicintctl Register + 0x105F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_24 + CLICINTCTL_24 + clicintctl Register + 0x1063 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_25 + CLICINTCTL_25 + clicintctl Register + 0x1067 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_26 + CLICINTCTL_26 + clicintctl Register + 0x106B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_27 + CLICINTCTL_27 + clicintctl Register + 0x106F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_28 + CLICINTCTL_28 + clicintctl Register + 0x1073 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_29 + CLICINTCTL_29 + clicintctl Register + 0x1077 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_30 + CLICINTCTL_30 + clicintctl Register + 0x107B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_31 + CLICINTCTL_31 + clicintctl Register + 0x107F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_32 + CLICINTCTL_32 + clicintctl Register + 0x1083 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_33 + CLICINTCTL_33 + clicintctl Register + 0x1087 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_34 + CLICINTCTL_34 + clicintctl Register + 0x108B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_35 + CLICINTCTL_35 + clicintctl Register + 0x108F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_36 + CLICINTCTL_36 + clicintctl Register + 0x1093 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_37 + CLICINTCTL_37 + clicintctl Register + 0x1097 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_38 + CLICINTCTL_38 + clicintctl Register + 0x109B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_39 + CLICINTCTL_39 + clicintctl Register + 0x109F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_40 + CLICINTCTL_40 + clicintctl Register + 0x10A3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_41 + CLICINTCTL_41 + clicintctl Register + 0x10A7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_42 + CLICINTCTL_42 + clicintctl Register + 0x10AB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_43 + CLICINTCTL_43 + clicintctl Register + 0x10AF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_44 + CLICINTCTL_44 + clicintctl Register + 0x10B3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_45 + CLICINTCTL_45 + clicintctl Register + 0x10B7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_46 + CLICINTCTL_46 + clicintctl Register + 0x10BB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_47 + CLICINTCTL_47 + clicintctl Register + 0x10BF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_48 + CLICINTCTL_48 + clicintctl Register + 0x10C3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_49 + CLICINTCTL_49 + clicintctl Register + 0x10C7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_50 + CLICINTCTL_50 + clicintctl Register + 0x10CB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_51 + CLICINTCTL_51 + clicintctl Register + 0x10CF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_52 + CLICINTCTL_52 + clicintctl Register + 0x10D3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_53 + CLICINTCTL_53 + clicintctl Register + 0x10D7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_54 + CLICINTCTL_54 + clicintctl Register + 0x10DB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_55 + CLICINTCTL_55 + clicintctl Register + 0x10DF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_56 + CLICINTCTL_56 + clicintctl Register + 0x10E3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_57 + CLICINTCTL_57 + clicintctl Register + 0x10E7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_58 + CLICINTCTL_58 + clicintctl Register + 0x10EB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_59 + CLICINTCTL_59 + clicintctl Register + 0x10EF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_60 + CLICINTCTL_60 + clicintctl Register + 0x10F3 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_61 + CLICINTCTL_61 + clicintctl Register + 0x10F7 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_62 + CLICINTCTL_62 + clicintctl Register + 0x10FB + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_63 + CLICINTCTL_63 + clicintctl Register + 0x10FF + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_64 + CLICINTCTL_64 + clicintctl Register + 0x1103 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_65 + CLICINTCTL_65 + clicintctl Register + 0x1107 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_66 + CLICINTCTL_66 + clicintctl Register + 0x110B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_67 + CLICINTCTL_67 + clicintctl Register + 0x110F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_68 + CLICINTCTL_68 + clicintctl Register + 0x1113 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_69 + CLICINTCTL_69 + clicintctl Register + 0x1117 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_70 + CLICINTCTL_70 + clicintctl Register + 0x111B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_71 + CLICINTCTL_71 + clicintctl Register + 0x111F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_72 + CLICINTCTL_72 + clicintctl Register + 0x1123 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_73 + CLICINTCTL_73 + clicintctl Register + 0x1127 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_74 + CLICINTCTL_74 + clicintctl Register + 0x112B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_75 + CLICINTCTL_75 + clicintctl Register + 0x112F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_76 + CLICINTCTL_76 + clicintctl Register + 0x1133 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_77 + CLICINTCTL_77 + clicintctl Register + 0x1137 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_78 + CLICINTCTL_78 + clicintctl Register + 0x113B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_79 + CLICINTCTL_79 + clicintctl Register + 0x113F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_80 + CLICINTCTL_80 + clicintctl Register + 0x1143 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_81 + CLICINTCTL_81 + clicintctl Register + 0x1147 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_82 + CLICINTCTL_82 + clicintctl Register + 0x114B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_83 + CLICINTCTL_83 + clicintctl Register + 0x114F + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_84 + CLICINTCTL_84 + clicintctl Register + 0x1153 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_85 + CLICINTCTL_85 + clicintctl Register + 0x1157 + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + CLICINTCTL_86 + CLICINTCTL_86 + clicintctl Register + 0x115B + 0x08 + read-write + 0x00 + + + LEVEL_PRIORITY + LEVEL_PRIORITY + 0 + 8 + + + + + + + + PMU + Power management unit + PMU + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTL + CTL + power control register + 0x00 + 0x20 + read-write + 0x00000000 + + + BKPWEN + Backup Domain Write Enable + 8 + 1 + + + LVDT + Low Voltage Detector Threshold + 5 + 3 + + + LVDEN + Low Voltage Detector Enable + 4 + 1 + + + STBRST + Standby Flag Reset + 3 + 1 + + + WURST + Wakeup Flag Reset + 2 + 1 + + + STBMOD + Standby Mode + 1 + 1 + + + LDOLP + LDO Low Power Mode + 0 + 1 + + + + + CS + CS + power control/status register + 0x04 + 0x20 + 0x00000000 + + + WUPEN + Enable WKUP pin + 8 + 1 + read-write + + + LVDF + Low Voltage Detector Status Flag + 2 + 1 + read-only + + + STBF + Standby flag + 1 + 1 + read-only + + + WUF + Wakeup flag + 0 + 1 + read-only + + + + + + + RCU + Reset and clock unit + RCU + 0x40021000 + + 0x0 + 0x400 + registers + + + RCU + 24 + + + + CTL + CTL + Control register + 0x0 + 0x20 + 0x00000083 + + + IRC8MEN + Internal 8MHz RC oscillator Enable + 0 + 1 + read-write + + + IRC8MSTB + IRC8M Internal 8MHz RC Oscillator stabilization Flag + 1 + 1 + read-only + + + IRC8MADJ + Internal 8MHz RC Oscillator clock trim adjust value + 3 + 5 + read-write + + + IRC8MCALIB + Internal 8MHz RC Oscillator calibration value register + 8 + 8 + read-only + + + HXTALEN + External High Speed oscillator Enable + 16 + 1 + read-write + + + HXTALSTB + External crystal oscillator (HXTAL) clock stabilization flag + 17 + 1 + read-only + + + HXTALBPS + External crystal oscillator (HXTAL) clock bypass mode enable + 18 + 1 + read-write + + + CKMEN + HXTAL Clock Monitor Enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTB + PLL Clock Stabilization Flag + 25 + 1 + read-only + + + PLL1EN + PLL1 enable + 26 + 1 + read-write + + + PLL1STB + PLL1 Clock Stabilization Flag + 27 + 1 + read-only + + + PLL2EN + PLL2 enable + 28 + 1 + read-write + + + PLL2STB + PLL2 Clock Stabilization Flag + 29 + 1 + read-only + + + + + CFG0 + CFG0 + Clock configuration register 0 + (RCU_CFG0) + 0x04 + 0x20 + 0x00000000 + + + SCS + System clock switch + 0 + 2 + read-write + + + SCSS + System clock switch status + 2 + 2 + read-only + + + AHBPSC + AHB prescaler selection + 4 + 4 + read-write + + + APB1PSC + APB1 prescaler selection + 8 + 3 + read-write + + + APB2PSC + APB2 prescaler selection + 11 + 3 + read-write + + + ADCPSC_1_0 + ADC clock prescaler selection + 14 + 2 + read-write + + + PLLSEL + PLL Clock Source Selection + 16 + 1 + read-write + + + PREDV0_LSB + The LSB of PREDV0 division factor + 17 + 1 + read-write + + + PLLMF_3_0 + The PLL clock multiplication factor + 18 + 4 + read-write + + + USBFSPSC + USBFS clock prescaler selection + 22 + 2 + read-write + + + CKOUT0SEL + CKOUT0 Clock Source Selection + 24 + 4 + read-write + + + ADCPSC_2 + Bit 2 of ADCPSC + 28 + 1 + read-write + + + PLLMF_4 + Bit 4 of PLLMF + 29 + 1 + read-write + + + + + INT + INT + Clock interrupt register + (RCU_INT) + 0x08 + 0x20 + 0x00000000 + + + IRC40KSTBIF + IRC40K stabilization interrupt flag + 0 + 1 + read-only + + + LXTALSTBIF + LXTAL stabilization interrupt flag + 1 + 1 + read-only + + + IRC8MSTBIF + IRC8M stabilization interrupt flag + 2 + 1 + read-only + + + HXTALSTBIF + HXTAL stabilization interrupt flag + 3 + 1 + read-only + + + PLLSTBIF + PLL stabilization interrupt flag + 4 + 1 + read-only + + + PLL1STBIF + PLL1 stabilization interrupt flag + 5 + 1 + read-only + + + PLL2STBIF + PLL2 stabilization interrupt flag + 6 + 1 + read-only + + + CKMIF + HXTAL Clock Stuck Interrupt Flag + 7 + 1 + read-only + + + IRC40KSTBIE + IRC40K Stabilization interrupt enable + 8 + 1 + read-write + + + LXTALSTBIE + LXTAL Stabilization Interrupt Enable + 9 + 1 + read-write + + + IRC8MSTBIE + IRC8M Stabilization Interrupt Enable + 10 + 1 + read-write + + + HXTALSTBIE + HXTAL Stabilization Interrupt Enable + 11 + 1 + read-write + + + PLLSTBIE + PLL Stabilization Interrupt Enable + 12 + 1 + read-write + + + PLL1STBIE + PLL1 Stabilization Interrupt Enable + 13 + 1 + read-write + + + PLL2STBIE + PLL2 Stabilization Interrupt Enable + 14 + 1 + read-write + + + IRC40KSTBIC + IRC40K Stabilization Interrupt Clear + 16 + 1 + write-only + + + LXTALSTBIC + LXTAL Stabilization Interrupt Clear + 17 + 1 + write-only + + + IRC8MSTBIC + IRC8M Stabilization Interrupt Clear + 18 + 1 + write-only + + + HXTALSTBIC + HXTAL Stabilization Interrupt Clear + 19 + 1 + write-only + + + PLLSTBIC + PLL stabilization Interrupt Clear + 20 + 1 + write-only + + + PLL1STBIC + PLL1 stabilization Interrupt Clear + 21 + 1 + write-only + + + PLL2STBIC + PLL2 stabilization Interrupt Clear + 22 + 1 + write-only + + + CKMIC + HXTAL Clock Stuck Interrupt Clear + 23 + 1 + write-only + + + + + + APB2RST + APB2RST + APB2 reset register + (RCU_APB2RST) + 0x0C + 0x20 + read-write + 0x00000000 + + + AFRST + Alternate function I/O reset + 0 + 1 + + + PARST + GPIO port A reset + 2 + 1 + + + PBRST + GPIO port B reset + 3 + 1 + + + PCRST + GPIO port C reset + 4 + 1 + + + PDRST + GPIO port D reset + 5 + 1 + + + PERST + GPIO port E reset + 6 + 1 + + + ADC0RST + ADC0 reset + 9 + 1 + + + ADC1RST + ADC1 reset + 10 + 1 + + + TIMER0RST + Timer 0 reset + 11 + 1 + + + SPI0RST + SPI0 reset + 12 + 1 + + + USART0RST + USART0 Reset + 14 + 1 + + + + + APB1RST + APB1RST + APB1 reset register + (RCU_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIMER1RST + TIMER1 timer reset + 0 + 1 + + + TIMER2RST + TIMER2 timer reset + 1 + 1 + + + TIMER3RST + TIMER3 timer reset + 2 + 1 + + + TIMER4RST + TIMER4 timer reset + 3 + 1 + + + TIMER5RST + TIMER5 timer reset + 4 + 1 + + + TIMER6RST + TIMER6 timer reset + 5 + 1 + + + WWDGTRST + Window watchdog timer reset + 11 + 1 + + + SPI1RST + SPI1 reset + 14 + 1 + + + SPI2RST + SPI2 reset + 15 + 1 + + + USART1RST + USART1 reset + 17 + 1 + + + USART2RST + USART2 reset + 18 + 1 + + + UART3RST + UART3 reset + 19 + 1 + + + UART4RST + UART4 reset + 20 + 1 + + + I2C0RST + I2C0 reset + 21 + 1 + + + I2C1RST + I2C1 reset + 22 + 1 + + + CAN0RST + CAN0 reset + 25 + 1 + + + CAN1RST + CAN1 reset + 26 + 1 + + + BKPIRST + Backup interface reset + 27 + 1 + + + PMURST + Power control reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + + + + AHBEN + AHBEN + AHB enable register + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA0EN + DMA0 clock enable + 0 + 1 + + + DMA1EN + DMA1 clock enable + 1 + 1 + + + SRAMSPEN + SRAM interface clock enable when sleep mode + 2 + 1 + + + FMCSPEN + FMC clock enable when sleep mode + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + EXMCEN + EXMC clock enable + 8 + 1 + + + USBFSEN + USBFS clock enable + 12 + 1 + + + + + APB2EN + APB2EN + APB2 clock enable register + (RCU_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + AFEN + Alternate function IO clock enable + 0 + 1 + + + PAEN + GPIO port A clock enable + 2 + 1 + + + PBEN + GPIO port B clock enable + 3 + 1 + + + PCEN + GPIO port C clock enable + 4 + 1 + + + PDEN + GPIO port D clock enable + 5 + 1 + + + PEEN + GPIO port E clock enable + 6 + 1 + + + ADC0EN + ADC0 clock enable + 9 + 1 + + + ADC1EN + ADC1 clock enable + 10 + 1 + + + TIMER0EN + TIMER0 clock enable + 11 + 1 + + + SPI0EN + SPI0 clock enable + 12 + 1 + + + USART0EN + USART0 clock enable + 14 + 1 + + + + + + APB1EN + APB1EN + APB1 clock enable register + (RCU_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIMER1EN + TIMER1 timer clock enable + 0 + 1 + + + TIMER2EN + TIMER2 timer clock enable + 1 + 1 + + + TIMER3EN + TIMER3 timer clock enable + 2 + 1 + + + TIMER4EN + TIMER4 timer clock enable + 3 + 1 + + + TIMER5EN + TIMER5 timer clock enable + 4 + 1 + + + TIMER6EN + TIMER6 timer clock enable + 5 + 1 + + + WWDGTEN + Window watchdog timer clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 14 + 1 + + + SPI2EN + SPI2 clock enable + 15 + 1 + + + USART1EN + USART1 clock enable + 17 + 1 + + + USART2EN + USART2 clock enable + 18 + 1 + + + UART3EN + UART3 clock enable + 19 + 1 + + + UART4EN + UART4 clock enable + 20 + 1 + + + I2C0EN + I2C0 clock enable + 21 + 1 + + + I2C1EN + I2C1 clock enable + 22 + 1 + + + CAN0EN + CAN0 clock enable + 25 + 1 + + + CAN1EN + CAN1 clock enable + 26 + 1 + + + BKPIEN + Backup interface clock enable + 27 + 1 + + + PMUEN + Power control clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + + + + BDCTL + BDCTL + Backup domain control register + (RCU_BDCTL) + 0x20 + 0x20 + 0x00000018 + + + LXTALEN + LXTAL enable + 0 + 1 + read-write + + + LXTALSTB + External low-speed oscillator stabilization + 1 + 1 + read-only + + + LXTALBPS + LXTAL bypass mode enable + 2 + 1 + read-write + + + RTCSRC + RTC clock entry selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BKPRST + Backup domain reset + 16 + 1 + read-write + + + + + RSTSCK + RSTSCK + Reset source /clock register + (RCU_RSTSCK) + 0x24 + 0x20 + 0x0C000000 + + + IRC40KEN + IRC40K enable + 0 + 1 + read-write + + + IRC40KSTB + IRC40K stabilization + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + EPRSTF + External PIN reset flag + 26 + 1 + read-only + + + PORRSTF + Power reset flag + 27 + 1 + read-only + + + SWRSTF + Software reset flag + 28 + 1 + read-only + + + FWDGTRSTF + Free Watchdog timer reset flag + 29 + 1 + read-only + + + WWDGTRSTF + Window watchdog timer reset flag + 30 + 1 + read-only + + + LPRSTF + Low-power reset flag + 31 + 1 + read-only + + + + + + AHBRST + AHBRST + AHB reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + USBFSRST + USBFS reset + 12 + 1 + + + + + + CFG1 + CFG1 + Clock Configuration register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PREDV0 + PREDV0 division factor + 0 + 4 + + + PREDV1 + PREDV1 division factor + 4 + 4 + + + PLL1MF + The PLL1 clock multiplication factor + 8 + 4 + + + PLL2MF + The PLL2 clock multiplication factor + 12 + 4 + + + PREDV0SEL + PREDV0 input Clock Source Selection + 16 + 1 + + + I2S1SEL + I2S1 Clock Source Selection + 17 + 1 + + + I2S2SEL + I2S2 Clock Source Selection + 18 + 1 + + + + + DSV + DSV + Deep sleep mode Voltage register + 0x34 + 0x20 + 0x00000000 + + + DSLPVS + Deep-sleep mode voltage select + 0 + 2 + read-write + + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + 22 + + + RTC_Alarm + 60 + + + + INTEN + INTEN + RTC interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + OVIE + Overflow interrupt enable + 2 + 1 + + + ALRMIE + Alarm interrupt enable + 1 + 1 + + + SCIE + Second interrupt + 0 + 1 + + + + + CTL + CTL + control register + 0x04 + 0x20 + read-write + 0x00000020 + + + LWOFF + Last write operation finished flag + 5 + 1 + + + CMF + Configuration mode flag + 4 + 1 + + + RSYNF + Registers synchronized flag + 3 + 1 + + + OVIF + Overflow interrupt flag + 2 + 1 + + + ALRMIF + Alarm interrupt flag + 1 + 1 + + + SCIF + Sencond interrupt flag + 0 + 1 + + + + + PSCH + PSCH + RTC prescaler high register + 0x08 + 0x20 + 0x00000000 + + + PSC + RTC prescaler value high + 0 + 4 + write + + + + + PSCL + PSCL + RTC prescaler low + register + 0x0C + 0x20 + 0x00008000 + + + PSC + RTC prescaler value low + 0 + 16 + write + + + + + DIVH + DIVH + RTC divider high register + 0x10 + 0x20 + read-only + 0x00000000 + + + DIV + RTC divider value high + 0 + 4 + + + + + DIVL + DIVL + RTC divider low register + 0x14 + 0x20 + read-only + 0x00008000 + + + DIV + RTC divider value low + 0 + 16 + + + + + CNTH + CNTH + RTC counter high register + 0x18 + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter value high + 0 + 16 + + + + + CNTL + CNTL + RTC counter low register + 0x1C + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter value low + 0 + 16 + + + + + ALRMH + ALRMH + Alarm high register + 0x20 + 0x20 + write + 0x0000FFFF + + + ALRM + Alarm value high + 0 + 16 + + + + + ALRML + ALRML + RTC alarm low register + 0x24 + 0x20 + write + 0x0000FFFF + + + ALRM + alarm value low + 0 + 16 + + + + + + + + SPI0 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI0 + 54 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + BDEN + Bidirectional + enable + 15 + 1 + + + BDOEN + Bidirectional Transmit output enable + + 14 + 1 + + + CRCEN + CRC Calculation Enable + 13 + 1 + + + CRCNT + CRC Next Transfer + 12 + 1 + + + FF16 + Data frame format + 11 + 1 + + + RO + Receive only + 10 + 1 + + + SWNSSEN + NSS Software Mode Selection + 9 + 1 + + + SWNSS + NSS Pin Selection In NSS Software Mode + 8 + 1 + + + LF + LSB First Mode + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + PSC + Master Clock Prescaler Selection + 3 + 3 + + + MSTMOD + Master Mode Enable + 2 + 1 + + + CKPL + Clock polarity Selection + 1 + 1 + + + CKPH + Clock Phase Selection + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + TBEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RBNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TMOD + SPI TI mode enable + 4 + 1 + + + NSSP + SPI NSS pulse mode enable + 3 + 1 + + + NSSDRV + Drive NSS Output + 2 + 1 + + + DMATEN + Transmit Buffer DMA Enable + 1 + 1 + + + DMAREN + Rx buffer DMA enable + 0 + 1 + + + + + STAT + STAT + status register + 0x08 + 0x10 + 0x0002 + + + FERR + Format error + 8 + 1 + read-only + + + TRANS + Transmitting On-going Bit + 7 + 1 + read-only + + + RXORERR + Reception Overrun Error Bit + 6 + 1 + read-only + + + CONFERR + SPI Configuration error + 5 + 1 + read-only + + + CRCERR + SPI CRC Error Bit + 4 + 1 + read-write + + + TXURERR + Transmission underrun error bit + 3 + 1 + read-only + + + I2SCH + I2S channel side + 2 + 1 + read-only + + + TBE + Transmit Buffer Empty + 1 + 1 + read-only + + + RBNE + Receive Buffer Not Empty + 0 + 1 + read-only + + + + + DATA + DATA + data register + 0x0C + 0x10 + read-write + 0x0000 + + + SPI_DATA + Data transfer register + 0 + 16 + + + + + CRCPOLY + CRCPOLY + CRC polynomial register + 0x10 + 0x10 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial value + 0 + 16 + + + + + RCRC + RCRC + RX CRC register + 0x14 + 0x10 + read-only + 0x0000 + + + RCRC + RX CRC value + 0 + 16 + + + + + TCRC + TCRC + TX CRC register + 0x18 + 0x10 + read-only + 0x0000 + + + TCRC + Tx CRC value + 0 + 16 + + + + + I2SCTL + I2SCTL + I2S control register + 0x1C + 0x10 + read-write + 0x0000 + + + I2SSEL + I2S mode selection + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + I2SOPMOD + I2S operation mode + 8 + 2 + + + PCMSMOD + PCM frame synchronization mode + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPL + Idle state clock polarity + 3 + 1 + + + DTLEN + Data length + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPSC + I2SPSC + I2S prescaler register + 0x20 + 0x10 + read-write + 0x0002 + + + MCKOEN + I2S_MCK output enable + 9 + 1 + + + OF + Odd factor for the + prescaler + 8 + 1 + + + DIV + Dividing factor for the prescaler + 0 + 8 + + + + + + + SPI1 + 0x40003800 + + SPI1 + 55 + + + + SPI2 + 0x40003C00 + + SPI2 + 70 + + + + TIMER0 + Advanced-timers + TIMER + 0x40012c00 + + 0x0 + 0x400 + registers + + + TIMER0_BRK + 43 + + + TIMER0_UP + 44 + + + TIMER0_TRG_CMT + 45 + + + TIMER0_Channel + 46 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload shadow enable + 7 + 1 + + + CAM + Counter aligns mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + SPM + Single pulse mode + 3 + 1 + + + UPS + Update source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + ISO3 + Idle state of channel 3 output + 14 + 1 + + + ISO2N + Idle state of channel 2 complementary output + 13 + 1 + + + ISO2 + Idle state of channel 2 output + 12 + 1 + + + ISO1N + Idle state of channel 1 complementary output + 11 + 1 + + + ISO1 + Idle state of channel 1 output + 10 + 1 + + + ISO0N + Idle state of channel 0 complementary output + 9 + 1 + + + ISO0 + Idle state of channel 0 output + 8 + 1 + + + TI0S + Channel 0 trigger input selection + 7 + 1 + + + MMC + Master mode control + 4 + 3 + + + DMAS + DMA request source selection + 3 + 1 + + + CCUC + Commutation control shadow register update control + 2 + 1 + + + CCSE + Commutation control shadow enable + 0 + 1 + + + + + SMCFG + SMCFG + slave mode configuration register + 0x08 + 0x10 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + SMC1 + Part of SMC for enable External clock mode1 + 14 + 1 + + + ETPSC + External trigger prescaler + 12 + 2 + + + ETFC + External trigger filter control + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TRGS + Trigger selection + 4 + 3 + + + SMC + Slave mode selection + 0 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x10 + read-write + 0x0000 + + + TRGDEN + Trigger DMA request enable + 14 + 1 + + + CMTDEN + Commutation DMA request enable + 13 + 1 + + + CH3DEN + Channel 3 capture/compare DMA request enable + 12 + 1 + + + CH2DEN + Channel 2 capture/compare DMA request enable + 11 + 1 + + + CH1DEN + Channel 1 capture/compare DMA request enable + 10 + 1 + + + CH0DEN + Channel 0 capture/compare DMA request enable + 9 + 1 + + + UPDEN + Update DMA request enable + 8 + 1 + + + BRKIE + Break interrupt enable + 7 + 1 + + + TRGIE + Trigger interrupt enable + 6 + 1 + + + CMTIE + commutation interrupt enable + 5 + 1 + + + CH3IE + Channel 3 capture/compare interrupt enable + 4 + 1 + + + CH2IE + Channel 2 capture/compare interrupt enable + 3 + 1 + + + CH1IE + Channel 1 capture/compare interrupt enable + 2 + 1 + + + CH0IE + Channel 0 capture/compare interrupt enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + Interrupt flag register + 0x10 + 0x10 + read-write + 0x0000 + + + CH3OF + Channel 3 over capture flag + 12 + 1 + + + CH2OF + Channel 2 over capture flag + 11 + 1 + + + CH1OF + Channel 1 over capture flag + 10 + 1 + + + CH0OF + Channel 0 over capture flag + 9 + 1 + + + BRKIF + Break interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + CMTIF + Channel commutation interrupt flag + 5 + 1 + + + CH3IF + Channel 3 capture/compare interrupt flag + 4 + 1 + + + CH2IF + Channel 2 capture/compare interrupt flag + 3 + 1 + + + CH1IF + Channel 1 capture/compare interrupt flag + 2 + 1 + + + CH0IF + Channel 0 capture/compare interrupt flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + Software event generation register + 0x14 + 0x10 + write-only + 0x0000 + + + BRKG + Break event generation + 7 + 1 + + + TRGG + Trigger event generation + 6 + 1 + + + CMTG + Channel commutation event generation + 5 + 1 + + + CH3G + Channel 3 capture or compare event generation + 4 + 1 + + + CH2G + Channel 2 capture or compare event generation + 3 + 1 + + + CH1G + Channel 1 capture or compare event generation + 2 + 1 + + + CH0G + Channel 0 capture or compare event generation + 1 + 1 + + + UPG + Update event generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + Channel control register 0 (output + mode) + 0x18 + 0x10 + read-write + 0x0000 + + + CH1COMCEN + Channel 1 output compare clear enable + 15 + 1 + + + CH1COMCTL + Channel 1 compare output control + 12 + 3 + + + CH1COMSEN + Channel 1 output compare shadow enable + 11 + 1 + + + CH1COMFEN + Channel 1 output compare fast enable + 10 + 1 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0COMCEN + Channel 0 output compare clear enable + 7 + 1 + + + CH0COMCTL + Channel 0 compare output control + 4 + 3 + + + CH0COMSEN + Channel 0 compare output shadow enable + 3 + 1 + + + CH0COMFEN + Channel 0 output compare fast enable + 2 + 1 + + + CH0MS + Channel 0 I/O mode selection + 0 + 2 + + + + + CHCTL0_Input + CHCTL0_Input + Channel control register 0 (input + mode) + CHCTL0_Output + 0x18 + 0x10 + read-write + 0x0000 + + + CH1CAPFLT + Channel 1 input capture filter control + 12 + 4 + + + CH1CAPPSC + Channel 1 input capture prescaler + 10 + 2 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0CAPFLT + Channel 0 input capture filter control + 4 + 4 + + + CH0CAPPSC + Channel 0 input capture prescaler + 2 + 2 + + + CH0MS + Channel 0 mode selection + 0 + 2 + + + + + CHCTL1_Output + CHCTL1_Output + Channel control register 1 (output + mode) + 0x1C + 0x10 + read-write + 0x0000 + + + CH3COMCEN + Channel 3 output compare clear enable + 15 + 1 + + + CH3COMCTL + Channel 3 compare output control + 12 + 3 + + + CH3COMSEN + Channel 3 output compare shadow enable + 11 + 1 + + + CH3COMFEN + Channel 3 output compare fast enable + 10 + 1 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2COMCEN + Channel 2 output compare clear enable + 7 + 1 + + + CH2COMCTL + Channel 2 compare output control + 4 + 3 + + + CH2COMSEN + Channel 2 compare output shadow enable + 3 + 1 + + + CH2COMFEN + Channel 2 output compare fast enable + 2 + 1 + + + CH2MS + Channel 2 I/O mode selection + 0 + 2 + + + + + CHCTL1_Input + CHCTL1_Input + Channel control register 1 (input + mode) + CHCTL1_Output + 0x1C + 0x10 + read-write + 0x0000 + + + CH3CAPFLT + Channel 3 input capture filter control + 12 + 4 + + + CH3CAPPSC + Channel 3 input capture prescaler + 10 + 2 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2CAPFLT + Channel 2 input capture filter control + 4 + 4 + + + CH2CAPPSC + Channel 2 input capture prescaler + 2 + 2 + + + CH2MS + Channel 2 mode selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + Channel control register 2 + 0x20 + 0x10 + read-write + 0x0000 + + + CH3P + Channel 3 capture/compare function polarity + 13 + 1 + + + CH3EN + Channel 3 capture/compare function enable + 12 + 1 + + + CH2NP + Channel 2 complementary output polarity + 11 + 1 + + + CH2NEN + Channel 2 complementary output enable + 10 + 1 + + + CH2P + Channel 2 capture/compare function polarity + 9 + 1 + + + CH2EN + Channel 2 capture/compare function enable + 8 + 1 + + + CH1NP + Channel 1 complementary output polarity + 7 + 1 + + + CH1NEN + Channel 1 complementary output enable + 6 + 1 + + + CH1P + Channel 1 capture/compare function polarity + 5 + 1 + + + CH1EN + Channel 1 capture/compare function enable + 4 + 1 + + + CH0NP + Channel 0 complementary output polarity + 3 + 1 + + + CH0NEN + Channel 0 complementary output enable + 2 + 1 + + + CH0P + Channel 0 capture/compare function polarity + 1 + 1 + + + CH0EN + Channel 0 capture/compare function enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x10 + read-write + 0x0000 + + + CNT + current counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + Prescaler value of the counter clock + 0 + 16 + + + + + CAR + CAR + Counter auto reload register + 0x2C + 0x10 + read-write + 0x0000 + + + CARL + Counter auto reload value + 0 + 16 + + + + + CREP + CREP + Counter repetition register + 0x30 + 0x10 + read-write + 0x0000 + + + CREP + Counter repetition value + 0 + 8 + + + + + CH0CV + CH0CV + Channel 0 capture/compare value register + 0x34 + 0x10 + read-write + 0x0000 + + + CH0VAL + Capture or compare value of channel0 + 0 + 16 + + + + + CH1CV + CH1CV + Channel 1 capture/compare value register + 0x38 + 0x10 + read-write + 0x0000 + + + CH1VAL + Capture or compare value of channel1 + 0 + 16 + + + + + CH2CV + CH2CV + Channel 2 capture/compare value register + 0x3C + 0x10 + read-write + 0x0000 + + + CH2VAL + Capture or compare value of channel 2 + 0 + 16 + + + + + CH3CV + CH3CV + Channel 3 capture/compare value register + 0x40 + 0x10 + read-write + 0x0000 + + + CH3VAL + Capture or compare value of channel 3 + 0 + 16 + + + + + CCHP + CCHP + channel complementary protection register + 0x44 + 0x10 + read-write + 0x0000 + + + POEN + Primary output enable + 15 + 1 + + + OAEN + Output automatic enable + 14 + 1 + + + BRKP + Break polarity + 13 + 1 + + + BRKEN + Break enable + 12 + 1 + + + ROS + Run mode off-state configure + 11 + 1 + + + IOS + Idle mode off-state configure + 10 + 1 + + + PROT + Complementary register protect control + 8 + 2 + + + DTCFG + Dead time configure + 0 + 8 + + + + + DMACFG + DMACFG + DMA configuration register + 0x48 + 0x10 + read-write + 0x0000 + + + DMATC + DMA transfer count + 8 + 5 + + + DMATA + DMA transfer access start address + 0 + 5 + + + + + DMATB + DMATB + DMA transfer buffer register + 0x4C + 0x10 + read-write + 0x0000 + + + DMATB + DMA transfer buffer + 0 + 16 + + + + + + + TIMER1 + General-purpose-timers + TIMER + 0x40000000 + + 0x0 + 0x400 + registers + + + TIMER1 + 47 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload shadow enable + 7 + 1 + + + CAM + Counter aligns mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + SPM + Single pulse mode + 3 + 1 + + + UPS + Update source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + TI0S + Channel 0 trigger input selection + 7 + 1 + + + MMC + Master mode control + 4 + 3 + + + DMAS + DMA request source selection + 3 + 1 + + + + + SMCFG + SMCFG + slave mode control register + 0x08 + 0x10 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + SMC1 + Part of SMC for enable External clock mode1 + 14 + 1 + + + ETPSC + External trigger prescaler + 12 + 2 + + + ETFC + External trigger filter control + 8 + 4 + + + MSM + Master-slave mode + 7 + 1 + + + TRGS + Trigger selection + 4 + 3 + + + SMC + Slave mode control + 0 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x10 + read-write + 0x0000 + + + TRGDEN + Trigger DMA request enable + 14 + 1 + + + CH3DEN + Channel 3 capture/compare DMA request enable + 12 + 1 + + + CH2DEN + Channel 2 capture/compare DMA request enable + 11 + 1 + + + CH1DEN + Channel 1 capture/compare DMA request enable + 10 + 1 + + + CH0DEN + Channel 0 capture/compare DMA request enable + 9 + 1 + + + UPDEN + Update DMA request enable + 8 + 1 + + + TRGIE + Trigger interrupt enable + 6 + 1 + + + CH3IE + Channel 3 capture/compare interrupt enable + 4 + 1 + + + CH2IE + Channel 2 capture/compare interrupt enable + 3 + 1 + + + CH1IE + Channel 1 capture/compare interrupt enable + 2 + 1 + + + CH0IE + Channel 0 capture/compare interrupt enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + interrupt flag register + 0x10 + 0x10 + read-write + 0x0000 + + + CH3OF + Channel 3 over capture flag + 12 + 1 + + + CH2OF + Channel 2 over capture flag + 11 + 1 + + + CH1OF + Channel 1 over capture flag + 10 + 1 + + + CH0OF + Channel 0 over capture flag + 9 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + CH3IF + Channel 3 capture/compare interrupt enable + 4 + 1 + + + CH2IF + Channel 2 capture/compare interrupt enable + 3 + 1 + + + CH1IF + Channel 1 capture/compare interrupt flag + 2 + 1 + + + CH0IF + Channel 0 capture/compare interrupt flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x10 + write-only + 0x0000 + + + TRGG + Trigger event generation + 6 + 1 + + + CH3G + Channel 3 capture or compare event generation + 4 + 1 + + + CH2G + Channel 2 capture or compare event generation + 3 + 1 + + + CH1G + Channel 1 capture or compare event generation + 2 + 1 + + + CH0G + Channel 0 capture or compare event generation + 1 + 1 + + + UPG + Update generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + Channel control register 0 (output + mode) + 0x18 + 0x10 + read-write + 0x0000 + + + CH1COMCEN + Channel 1 output compare clear enable + 15 + 1 + + + CH1COMCTL + Channel 1 compare output control + 12 + 3 + + + CH1COMSEN + Channel 1 output compare shadow enable + 11 + 1 + + + CH1COMFEN + Channel 1 output compare fast enable + 10 + 1 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0COMCEN + Channel 0 output compare clear enable + 7 + 1 + + + CH0COMCTL + Channel 0 compare output control + 4 + 3 + + + CH0COMSEN + Channel 0 compare output shadow enable + 3 + 1 + + + CH0COMFEN + Channel 0 output compare fast enable + 2 + 1 + + + CH0MS + Channel 0 I/O mode selection + 0 + 2 + + + + + CHCTL0_Input + CHCTL0_Input + Channel control register 0 (input + mode) + CHCTL0_Output + 0x18 + 0x10 + read-write + 0x00000000 + + + CH1CAPFLT + Channel 1 input capture filter control + 12 + 4 + + + CH1CAPPSC + Channel 1 input capture prescaler + 10 + 2 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0CAPFLT + Channel 0 input capture filter control + 4 + 4 + + + CH0CAPPSC + Channel 0 input capture prescaler + 2 + 2 + + + CH0MS + Channel 0 mode selection + 0 + 2 + + + + + CHCTL1_Output + CHCTL1_Output + Channel control register 1 (output mode) + 0x1C + 0x10 + read-write + 0x0000 + + + CH3COMCEN + Channel 3 output compare clear enable + 15 + 1 + + + CH3COMCTL + Channel 3 compare output control + 12 + 3 + + + CH3COMSEN + Channel 3 output compare shadow enable + 11 + 1 + + + CH3COMFEN + Channel 3 output compare fast enable + 10 + 1 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2COMCEN + Channel 2 output compare clear enable + 7 + 1 + + + CH2COMCTL + Channel 2 compare output control + 4 + 3 + + + CH2COMSEN + Channel 2 compare output shadow enable + 3 + 1 + + + CH2COMFEN + Channel 2 output compare fast enable + 2 + 1 + + + CH2MS + Channel 2 I/O mode selection + 0 + 2 + + + + + CHCTL1_Input + CHCTL1_Input + Channel control register 1 (input + mode) + CHCTL1_Output + 0x1C + 0x10 + read-write + 0x0000 + + + CH3CAPFLT + Channel 3 input capture filter control + 12 + 4 + + + CH3CAPPSC + Channel 3 input capture prescaler + 10 + 2 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2CAPFLT + Channel 2 input capture filter control + 4 + 4 + + + CH2CAPPSC + Channel 2 input capture prescaler + 2 + 2 + + + CH2MS + Channel 2 mode selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + Channel control register 2 + 0x20 + 0x10 + read-write + 0x0000 + + + CH3P + Channel 3 capture/compare function polarity + 13 + 1 + + + CH3EN + Channel 3 capture/compare function enable + 12 + 1 + + + CH2P + Channel 2 capture/compare function polarity + 9 + 1 + + + CH2EN + Channel 2 capture/compare function enable + 8 + 1 + + + CH1P + Channel 1 capture/compare function polarity + 5 + 1 + + + CH1EN + Channel 1 capture/compare function enable + 4 + 1 + + + CH0P + Channel 0 capture/compare function polarity + 1 + 1 + + + CH0EN + Channel 0 capture/compare function enable + 0 + 1 + + + + + CNT + CNT + Counter register + 0x24 + 0x10 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + Prescaler register + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + Prescaler value of the counter clock + 0 + 16 + + + + + CAR + CAR + Counter auto reload register + 0x2C + 0x10 + read-write + 0x0000 + + + CARL + Counter auto reload value + 0 + 16 + + + + + CH0CV + CH0CV + Channel 0 capture/compare value register + 0x34 + 0x20 + read-write + 0x00000000 + + + CH0VAL + Capture or compare value of channel 0 + 0 + 16 + + + + + CH1CV + CH1CV + Channel 1 capture/compare value register + 0x38 + 0x20 + read-write + 0x00000000 + + + CH1VAL + Capture or compare value of channel1 + 0 + 16 + + + + + CH2CV + CH2CV + Channel 2 capture/compare value register + 0x3C + 0x20 + read-write + 0x00000000 + + + CH2VAL + Capture or compare value of channel 2 + 0 + 16 + + + + + CH3CV + CH3CV + Channel 3 capture/compare value register + 0x40 + 0x20 + read-write + 0x00000000 + + + CH3VAL + Capture or compare value of channel 3 + 0 + 16 + + + + + DMACFG + DMACFG + DMA configuration register + 0x48 + 0x10 + read-write + 0x0000 + + + DMATC + DMA transfer count + 8 + 5 + + + DMATA + DMA transfer access start address + 0 + 5 + + + + + DMATB + DMATB + DMA transfer buffer register + 0x4C + 0x20 + read-write + 0x0000 + + + DMATB + DMA transfer buffer + 0 + 16 + + + + + + + TIMER2 + TIMER + 0x40000400 + + TIMER2 + 48 + + + + TIMER3 + TIMER + 0x40000800 + + TIMER3 + 49 + + + + TIMER4 + TIMER + 0x40000C00 + + TIMER4 + 69 + + + + TIMER5 + Basic-timers + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TIMER5 + 73 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x10 + read-write + 0x0000 + + + ARSE + Auto-reload shadow enable + 7 + 1 + + + SPM + Single pulse mode + 3 + 1 + + + UPS + Update source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x10 + read-write + 0x0000 + + + MMC + Master mode control + 4 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x10 + read-write + 0x0000 + + + UPDEN + Update DMA request enable + 8 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + Interrupt flag register + 0x10 + 0x10 + read-write + 0x0000 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x10 + write-only + 0x0000 + + + UPG + Update generation + 0 + 1 + + + + + CNT + CNT + Counter register + 0x24 + 0x10 + read-write + 0x0000 + + + CNT + Low counter value + 0 + 16 + + + + + PSC + PSC + Prescaler register + 0x28 + 0x10 + read-write + 0x0000 + + + PSC + Prescaler value of the counter clock + 0 + 16 + + + + + CAR + CAR + Counter auto reload register + 0x2C + 0x10 + read-write + 0x0000 + + + CARL + Counter auto reload value + 0 + 16 + + + + + + + TIMER6 + TIMER + 0x40001400 + + TIMER6 + 74 + + + + + USART0 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART0 + 56 + + + + STAT + STAT + Status register + 0x00 + 0x20 + 0x000000C0 + + + CTSF + CTS change flag + 9 + 1 + read-write + + + LBDF + LIN break detection flag + 8 + 1 + read-write + + + TBE + Transmit data buffer empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RBNE + Read data buffer not empty + 5 + 1 + read-write + + + IDLEF + IDLE frame detected flag + 4 + 1 + read-only + + + ORERR + Overrun error + 3 + 1 + read-only + + + NERR + Noise error flag + 2 + 1 + read-only + + + FERR + Frame error flag + 1 + 1 + read-only + + + PERR + Parity error flag + 0 + 1 + read-only + + + + + DATA + DATA + Data register + 0x04 + 0x20 + read-write + 0x00000000 + + + DATA + Transmit or read data value + 0 + 9 + + + + + BAUD + BAUD + Baud rate register + 0x08 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integer part of baud-rate divider + 4 + 12 + + + FRADIV + Fraction part of baud-rate divider + 0 + 4 + + + + + CTL0 + CTL0 + Control register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + UEN + USART enable + 13 + 1 + + + WL + Word length + 12 + 1 + + + WM + Wakeup method in mute mode + 11 + 1 + + + PCEN + Parity check function enable + 10 + 1 + + + PM + Parity mode + 9 + 1 + + + PERRIE + Parity error interrupt enable + 8 + 1 + + + TBEIE + Transmitter buffer empty interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RBNEIE + Read data buffer not empty interrupt and overrun error interrupt enable + 5 + 1 + + + IDLEIE + IDLE line detected interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup from mute mode + 1 + 1 + + + SBKCMD + Send break command + 0 + 1 + + + + + CTL1 + CTL1 + Control register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + LMEN + LIN mode enable + 14 + 1 + + + STB + STOP bits length + 12 + 2 + + + CKEN + CK pin enable + 11 + 1 + + + CPL + Clock polarity + 10 + 1 + + + CPH + Clock phase + 9 + 1 + + + CLEN + CK Length + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBLEN + LIN break frame length + 5 + 1 + + + ADDR + Address of the USART + 0 + 4 + + + + + CTL2 + CTL2 + Control register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DENT + DMA request enable for transmission + 7 + 1 + + + DENR + DMA request enable for reception + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NKEN + Smartcard NACK enable + 4 + 1 + + + HDEN + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + ERRIE + Error interrupt enable + 0 + 1 + + + + + GP + GP + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x00000000 + + + GUAT + Guard time value in Smartcard mode + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + USART1 + 0x40004400 + + USART1 + 57 + + + + USART2 + 0x40004800 + + USART2 + 58 + + + + UART3 + Universal asynchronous receiver + transmitter + UART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART3 + 71 + + + + STAT + STAT + Status register + 0x00 + 0x20 + 0x000000C0 + + + LBDF + LIN break detection flag + 8 + 1 + read-write + + + TBE + Transmit data buffer empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RBNE + Read data buffer not empty + 5 + 1 + read-write + + + IDLEF + IDLE frame detected flag + 4 + 1 + read-only + + + ORERR + Overrun error + 3 + 1 + read-only + + + NERR + Noise error flag + 2 + 1 + read-only + + + FERR + Frame error flag + 1 + 1 + read-only + + + PERR + Parity error flag + 0 + 1 + read-only + + + + + DATA + DATA + Data register + 0x04 + 0x20 + read-write + 0x00000000 + + + DATA + Transmit or read data value + 0 + 9 + + + + + BAUD + BAUD + Baud rate register + 0x08 + 0x20 + read-write + 0x00000000 + + + INTDIV + Integer part of baud-rate divider + 4 + 12 + + + FRADIV + Fraction part of baud-rate divider + 0 + 4 + + + + + CTL0 + CTL0 + Control register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + UEN + USART enable + 13 + 1 + + + WL + Word length + 12 + 1 + + + WM + Wakeup method in mute mode + 11 + 1 + + + PCEN + Parity check function enable + 10 + 1 + + + PM + Parity mode + 9 + 1 + + + PERRIE + Parity error interrupt enable + 8 + 1 + + + TBEIE + Transmitter buffer empty interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RBNEIE + Read data buffer not empty interrupt and overrun error interrupt enable + 5 + 1 + + + IDLEIE + IDLE line detected interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup from mute mode + 1 + 1 + + + SBKCMD + Send break command + 0 + 1 + + + + + CTL1 + CTL1 + Control register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + LMEN + LIN mode enable + 14 + 1 + + + STB + STOP bits length + 12 + 2 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBLEN + LIN break frame length + 5 + 1 + + + ADDR + Address of the USART + 0 + 4 + + + + + CTL2 + CTL2 + Control register 2 + 0x14 + 0x20 + read-write + 0x00000000 + + + DENT + DMA request enable for transmission + 7 + 1 + + + DENR + DMA request enable for reception + 6 + 1 + + + HDEN + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + ERRIE + Error interrupt enable + 0 + 1 + + + + + GP + GP + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 8 + + + + + + + UART4 + 0x40005000 + + UART4 + 72 + + + + + USBFS_GLOBAL + USB full speed global registers + USBFS + 0x50000000 + + 0x0 + 0x400 + registers + + + USBFS_WKUP + 61 + + + USBFS + 86 + + + + GOTGCS + GOTGCS + Global OTG control and status register + (USBFS_GOTGCS) + 0x0 + 0x20 + 0x00000800 + + + SRPS + SRP success + 0 + 1 + read-only + + + SRPREQ + SRP request + 1 + 1 + read-write + + + HNPS + Host success + 8 + 1 + read-only + + + HNPREQ + HNP request + 9 + 1 + read-write + + + HHNPEN + Host HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + IDPS + ID pin status + 16 + 1 + read-only + + + DI + Debounce interval + 17 + 1 + read-only + + + ASV + A-session valid + 18 + 1 + read-only + + + BSV + B-session valid + 19 + 1 + read-only + + + + + GOTGINTF + GOTGINTF + Global OTG interrupt flag register + (USBFS_GOTGINTF) + 0x04 + 0x20 + read-write + 0x00000000 + + + SESEND + Session end + 2 + 1 + + + SRPEND + Session request success status + change + 8 + 1 + + + HNPEND + HNP end + 9 + 1 + + + HNPDET + Host negotiation request detected + 17 + 1 + + + ADTO + A-device timeout + 18 + 1 + + + DF + Debounce finish + 19 + 1 + + + + + GAHBCS + GAHBCS + Global AHB control and status register + (USBFS_GAHBCS) + 0x08 + 0x20 + read-write + 0x00000000 + + + GINTEN + Global interrupt enable + 0 + 1 + + + TXFTH + Tx FIFO threshold + 7 + 1 + + + PTXFTH + Periodic Tx FIFO threshold + 8 + 1 + + + + + GUSBCS + GUSBCS + Global USB control and status register + (USBFS_GUSBCSR) + 0x0C + 0x20 + 0x00000A80 + + + TOC + Timeout calibration + 0 + 3 + read-write + + + SRPCEN + SRP capability enable + 8 + 1 + read-write + + + HNPCEN + HNP capability enable + 9 + 1 + read-write + + + UTT + USB turnaround time + 10 + 4 + read-write + + + FHM + Force host mode + 29 + 1 + read-write + + + FDM + Force device mode + 30 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + Global reset control register (USBFS_GRSTCTL) + 0x10 + 0x20 + 0x80000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HCSRST + HCLK soft reset + 1 + 1 + read-write + + + HFCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFF + RxFIFO flush + 4 + 1 + read-write + + + TXFF + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + + + GINTF + GINTF + Global interrupt flag register (USBFS_GINTF) + 0x14 + 0x20 + 0x04000021 + + + COPM + Current operation mode + 0 + 1 + read-only + + + MFIF + Mode fault interrupt flag + 1 + 1 + read-write + + + OTGIF + OTG interrupt flag + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFNEIF + RxFIFO non-empty interrupt flag + 4 + 1 + read-only + + + NPTXFEIF + Non-periodic TxFIFO empty interrupt flag + 5 + 1 + read-only + + + GNPINAK + Global Non-Periodic IN NAK effective + 6 + 1 + read-only + + + GONAK + Global OUT NAK effective + 7 + 1 + read-only + + + ESP + Early suspend + 10 + 1 + read-write + + + SP + USB suspend + 11 + 1 + read-write + + + RST + USB reset + 12 + 1 + read-write + + + ENUMF + Enumeration finished + 13 + 1 + read-write + + + ISOOPDIF + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPFIF + End of periodic frame + interrupt flag + 15 + 1 + read-write + + + IEPIF + IN endpoint interrupt flag + 18 + 1 + read-only + + + OEPIF + OUT endpoint interrupt flag + 19 + 1 + read-only + + + ISOINCIF + Isochronous IN transfer Not Complete Interrupt Flag + 20 + 1 + read-write + + + PXNCIF_ISOONCIF + periodic transfer not complete interrupt flag(Host + mode)/isochronous OUT transfer not complete interrupt flag(Device + mode) + 21 + 1 + read-write + + + HPIF + Host port interrupt flag + 24 + 1 + read-only + + + HCIF + Host channels interrupt flag + 25 + 1 + read-only + + + PTXFEIF + Periodic TxFIFO empty interrupt flag + 26 + 1 + read-only + + + IDPSC + ID pin status change + 28 + 1 + read-write + + + DISCIF + Disconnect interrupt flag + 29 + 1 + read-write + + + SESIF + Session interrupt flag + 30 + 1 + read-write + + + WKUPIF + Wakeup interrupt flag + 31 + 1 + read-write + + + + + GINTEN + GINTEN + Global interrupt enable register + (USBFS_GINTEN) + 0x18 + 0x20 + 0x00000000 + + + MFIE + Mode fault interrupt + enable + 1 + 1 + read-write + + + OTGIE + OTG interrupt enable + 2 + 1 + read-write + + + SOFIE + Start of frame interrupt enable + 3 + 1 + read-write + + + RXFNEIE + Receive FIFO non-empty + interrupt enable + 4 + 1 + read-write + + + NPTXFEIE + Non-periodic TxFIFO empty + interrupt enable + 5 + 1 + read-write + + + GNPINAKIE + Global non-periodic IN NAK effective interrupt enable + 6 + 1 + read-write + + + GONAKIE + Global OUT NAK effective + interrupt enable + 7 + 1 + read-write + + + ESPIE + Early suspend interrupt enable + 10 + 1 + read-write + + + SPIE + USB suspend interrupt enable + 11 + 1 + read-write + + + RSTIE + USB reset interrupt enable + 12 + 1 + read-write + + + ENUMFIE + Enumeration finish interrupt enable + 13 + 1 + read-write + + + ISOOPDIE + Isochronous OUT packet dropped interrupt enable + 14 + 1 + read-write + + + EOPFIE + End of periodic frame interrupt enable + 15 + 1 + read-write + + + IEPIE + IN endpoints interrupt enable + 18 + 1 + read-write + + + OEPIE + OUT endpoints interrupt enable + 19 + 1 + read-write + + + ISOINCIE + isochronous IN transfer not complete + interrupt enable + 20 + 1 + read-write + + + PXNCIE_ISOONCIE + periodic transfer not compelete Interrupt enable(Host + mode)/isochronous OUT transfer not complete interrupt enable(Device + mode) + 21 + 1 + read-write + + + HPIE + Host port interrupt enable + 24 + 1 + read-only + + + HCIE + Host channels interrupt enable + 25 + 1 + read-write + + + PTXFEIE + Periodic TxFIFO empty interrupt enable + 26 + 1 + read-write + + + IDPSCIE + ID pin status change interrupt enable + 28 + 1 + read-write + + + DISCIE + Disconnect interrupt enable + 29 + 1 + read-write + + + SESIE + Session interrupt enable + 30 + 1 + read-write + + + WKUPIE + Wakeup interrupt enable + 31 + 1 + read-write + + + + + GRSTATR_Device + GRSTATR_Device + Global Receive status read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCOUNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + RPCKST + Recieve packet status + 17 + 4 + + + + + GRSTATR_Host + GRSTATR_Host + Global Receive status read(Host + mode) + GRSTATR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CNUM + Channel number + 0 + 4 + + + BCOUNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + RPCKST + Reivece packet status + 17 + 4 + + + + + + GRSTATP_Device + GRSTATP_Device + Global Receive status pop(Device + mode) + 0x20 + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCOUNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + RPCKST + Recieve packet status + 17 + 4 + + + + + GRSTATP_Host + GRSTATP_Host + Global Receive status pop(Host + mode) + GRSTATP_Device + 0x20 + 0x20 + read-only + 0x00000000 + + + CNUM + Channel number + 0 + 4 + + + BCOUNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + RPCKST + Reivece packet status + 17 + 4 + + + + + GRFLEN + GRFLEN + Global Receive FIFO size register + (USBFS_GRFLEN) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + Rx FIFO depth + 0 + 16 + + + + + HNPTFLEN + HNPTFLEN + Host non-periodic transmit FIFO length register + (Host mode) + 0x28 + 0x20 + read-write + 0x02000200 + + + HNPTXRSAR + host non-periodic transmit Tx RAM start + address + 0 + 16 + + + HNPTXFD + host non-periodic TxFIFO depth + 16 + 16 + + + + + DIEP0TFLEN + DIEP0TFLEN + Device IN endpoint 0 transmit FIFO length + (Device mode) + HNPTFLEN + 0x28 + 0x20 + read-write + 0x02000200 + + + IEP0TXFD + in endpoint 0 Tx FIFO depth + 16 + 16 + + + IEP0TXRSAR + in endpoint 0 Tx RAM start address + 0 + 16 + + + + + HNPTFQSTAT + HNPTFQSTAT + Host non-periodic transmit FIFO/queue + status register (HNPTFQSTAT) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFS + Non-periodic TxFIFO space + 0 + 16 + + + NPTXRQS + Non-periodic transmit request queue + space + 16 + 8 + + + NPTXRQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + Global core configuration register (USBFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRON + Power on + 16 + 1 + + + VBUSACEN + The VBUS A-device Comparer enable + 18 + 1 + + + VBUSBCEN + The VBUS B-device Comparer enable + 19 + 1 + + + SOFOEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS ignored + 21 + 1 + + + + + CID + CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + CID + Core ID + 0 + 32 + + + + + HPTFLEN + HPTFLEN + Host periodic transmit FIFO length register (HPTFLEN) + 0x100 + 0x20 + read-write + 0x02000600 + + + HPTXFSAR + Host periodic TxFIFO start + address + 0 + 16 + + + HPTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEP1TFLEN + DIEP1TFLEN + device IN endpoint transmit FIFO size + register (DIEP1TFLEN) + 0x104 + 0x20 + read-write + 0x02000400 + + + IEPTXRSAR + IN endpoint FIFO transmit RAM start + address + 0 + 16 + + + IEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEP2TFLEN + DIEP2TFLEN + device IN endpoint transmit FIFO size + register (DIEP2TFLEN) + 0x108 + 0x20 + read-write + 0x02000400 + + + IEPTXRSAR + IN endpoint FIFO transmit RAM start + address + 0 + 16 + + + IEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEP3TFLEN + DIEP3TFLEN + device IN endpoint transmit FIFO size + register (FS_DIEP3TXFLEN) + 0x10C + 0x20 + read-write + 0x02000400 + + + IEPTXRSAR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + IEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + + USBFS_HOST + USB on the go full speed host + USBFS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCTL + HCTL + host configuration register + (HCTL) + 0x00 + 0x20 + 0x00000000 + + + CLKSEL + clock select for USB clock + 0 + 2 + read-write + + + + + HFT + HFT + Host frame interval + register + 0x04 + 0x20 + read-write + 0x0000BB80 + + + FRI + Frame interval + 0 + 16 + + + + + HFINFR + HFINFR + FS host frame number/frame time + remaining register (HFINFR) + 0x08 + 0x20 + read-only + 0xBB800000 + + + FRNUM + Frame number + 0 + 16 + + + FRT + Frame remaining time + 16 + 16 + + + + + HPTFQSTAT + HPTFQSTAT + Host periodic transmit FIFO/queue + status register (HPTFQSTAT) + 0x10 + 0x20 + 0x00080200 + + + PTXFS + Periodic transmit data FIFO space + available + 0 + 16 + read-only + + + PTXREQS + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXREQT + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HACHINT + HACHINT + Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HACHINT + Host all channel interrupts + 0 + 8 + + + + + HACHINTEN + HACHINTEN + host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + CINTEN + Channel interrupt enable + 0 + 8 + + + + + HPCS + HPCS + Host port control and status register (USBFS_HPCS) + 0x40 + 0x20 + 0x00000000 + + + PCST + Port connect status + 0 + 1 + read-only + + + PCD + Port connect detected + 1 + 1 + read-write + + + PE + Port enable + 2 + 1 + read-write + + + PEDC + Port enable/disable change + 3 + 1 + read-write + + + PREM + Port resume + 6 + 1 + read-write + + + PSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLST + Port line status + 10 + 2 + read-only + + + PP + Port power + 12 + 1 + read-write + + + PS + Port speed + 17 + 2 + read-only + + + + + HCH0CTL + HCH0CTL + host channel-0 characteristics + register (HCH0CTL) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH1CTL + HCH1CTL + host channel-1 characteristics + register (HCH1CTL) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH2CTL + HCH2CTL + host channel-2 characteristics + register (HCH2CTL) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH3CTL + HCH3CTL + host channel-3 characteristics + register (HCH3CTL) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH4CTL + HCH4CTL + host channel-4 characteristics + register (HCH4CTL) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH5CTL + HCH5CTL + host channel-5 characteristics + register (HCH5CTL) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH6CTL + HCH6CTL + host channel-6 characteristics + register (HCH6CTL) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH7CTL + HCH7CTL + host channel-7 characteristics + register (HCH7CTL) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPL + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSD + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + DAR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CDIS + Channel disable + 30 + 1 + + + CEN + Channel enable + 31 + 1 + + + + + HCH0INTF + HCH0INTF + host channel-0 interrupt register + (USBFS_HCHxINTF) + 0x108 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH1INTF + HCH1INTF + host channel-1 interrupt register + (HCH1INTF) + 0x128 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH2INTF + HCH2INTF + host channel-2 interrupt register + (HCH2INTF) + 0x148 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH3INTF + HCH3INTF + host channel-3 interrupt register + (HCH3INTF) + 0x168 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH4INTF + HCH4INTF + host channel-4 interrupt register + (HCH4INTF) + 0x188 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH5INTF + HCH5INTF + host channel-5 interrupt register + (HCH5INTF) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH6INTF + HCH6INTF + host channel-6 interrupt register + (HCH6INTF) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH7INTF + HCH7INTF + host channel-7 interrupt register + (HCH7INTF) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + TF + Transfer finished + 0 + 1 + + + CH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + USBER + USB bus error + 7 + 1 + + + BBER + Babble error + 8 + 1 + + + REQOVR + Request queue overrun + 9 + 1 + + + DTER + Data toggle error + 10 + 1 + + + + + HCH0INTEN + HCH0INTEN + host channel-0 interrupt enable register + (HCH0INTEN) + 0x10C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH1INTEN + HCH1INTEN + host channel-1 interrupt enable register + (HCH1INTEN) + 0x12C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH2INTEN + HCH2INTEN + host channel-2 interrupt enable register + (HCH2INTEN) + 0x14C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH3INTEN + HCH3INTEN + host channel-3 interrupt enable register + (HCH3INTEN) + 0x16C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH4INTEN + HCH4INTEN + host channel-4 interrupt enable register + (HCH4INTEN) + 0x18C + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH5INTEN + HCH5INTEN + host channel-5 interrupt enable register + (HCH5INTEN) + 0x1AC + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH6INTEN + HCH6INTEN + host channel-6 interrupt enable register + (HCH6INTEN) + 0x1CC + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH7INTEN + HCH7INTEN + host channel-7 interrupt enable register + (HCH7INTEN) + 0x1EC + 0x20 + read-write + 0x00000000 + + + TFIE + Transfer completed interrupt enable + 0 + 1 + + + CHIE + Channel halted interrupt enable + 1 + 1 + + + STALLIE + STALL interrupt enable + 3 + 1 + + + NAKIE + NAK interrupt enable + 4 + 1 + + + ACKIE + ACK interrupt enable + 5 + 1 + + + USBERIE + USB bus error interrupt enable + 7 + 1 + + + BBERIE + Babble error interrupt enable + 8 + 1 + + + REQOVRIE + request queue overrun interrupt enable + 9 + 1 + + + DTERIE + Data toggle error interrupt enable + 10 + 1 + + + + + HCH0LEN + HCH0LEN + host channel-0 transfer length + register + 0x110 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH1LEN + HCH1LEN + host channel-1 transfer length + register + 0x130 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH2LEN + HCH2LEN + host channel-2 transfer length + register + 0x150 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH3LEN + HCH3LEN + host channel-3 transfer length + register + 0x170 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH4LEN + HCH4LEN + host channel-4 transfer length + register + 0x190 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH5LEN + HCH5LEN + host channel-5 transfer length + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH6LEN + HCH6LEN + host channel-6 transfer length + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + HCH7LEN + HCH7LEN + host channel-7 transfer length + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + TLEN + Transfer length + 0 + 19 + + + PCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + USBFS_DEVICE + USB on the go full speed device + USBFS + 0x50000800 + + 0x00 + 0x400 + registers + + + + DCFG + DCFG + device configuration register + (DCFG) + 0x0 + 0x20 + read-write + 0x00000000 + + + DS + Device speed + 0 + 2 + + + NZLSOH + Non-zero-length status OUT + handshake + 2 + 1 + + + DAR + Device address + 4 + 7 + + + EOPFT + end of periodic frame time + 11 + 2 + + + + + DCTL + DCTL + device control register + (DCTL) + 0x04 + 0x20 + 0x00000000 + + + RWKUP + Remote wakeup + 0 + 1 + read-write + + + SD + Soft disconnect + 1 + 1 + read-write + + + GINS + Global IN NAK status + 2 + 1 + read-only + + + GONS + Global OUT NAK status + 3 + 1 + read-only + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POIF + Power-on initialization flag + 11 + 1 + read-write + + + + + DSTAT + DSTAT + device status register + (DSTAT) + 0x08 + 0x20 + read-only + 0x00000000 + + + SPST + Suspend status + 0 + 1 + + + ES + Enumerated speed + 1 + 2 + + + FNRSOF + Frame number of the received + SOF + 8 + 14 + + + + + DIEPINTEN + DIEPINTEN + device IN endpoint common interrupt + mask register (DIEPINTEN) + 0x10 + 0x20 + read-write + 0x00000000 + + + TFEN + Transfer finished interrupt + enable + 0 + 1 + + + EPDISEN + Endpoint disabled interrupt + enable + 1 + 1 + + + CITOEN + Control IN timeout condition interrupt enable (Non-isochronous + endpoints) + 3 + 1 + + + EPTXFUDEN + Endpoint Tx FIFO underrun interrupt enable bit + 4 + 1 + + + IEPNEEN + IN endpoint NAK effective + interrupt enable + 6 + 1 + + + + + DOEPINTEN + DOEPINTEN + device OUT endpoint common interrupt + enable register (DOEPINTEN) + 0x14 + 0x20 + read-write + 0x00000000 + + + TFEN + Transfer finished interrupt + enable + 0 + 1 + + + EPDISEN + Endpoint disabled interrupt + enable + 1 + 1 + + + STPFEN + SETUP phase finished interrupt enable + 3 + 1 + + + EPRXFOVREN + Endpoint Rx FIFO overrun interrupt enable + 4 + 1 + + + BTBSTPEN + Back-to-back SETUP packets + interrupt enable + 6 + 1 + + + + + DAEPINT + DAEPINT + device all endpoints interrupt + register (DAEPINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPITB + Device all IN endpoint interrupt bits + 0 + 4 + + + OEPITB + Device all OUT endpoint interrupt bits + 16 + 4 + + + + + DAEPINTEN + DAEPINTEN + Device all endpoints interrupt enable register + (DAEPINTEN) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPIE + IN EP interrupt interrupt enable bits + 0 + 4 + + + OEPIE + OUT endpoint interrupt enable bits + 16 + 4 + + + + + DVBUSDT + DVBUSDT + device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + DVBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPT + DVBUSPT + device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSPT + Device VBUS pulsing time + 0 + 12 + + + + + DIEPFEINTEN + DIEPFEINTEN + device IN endpoint FIFO empty + interrupt enable register + 0x34 + 0x20 + read-write + 0x00000000 + + + IEPTXFEIE + IN EP Tx FIFO empty interrupt enable + bits + 0 + 4 + + + + + DIEP0CTL + DIEP0CTL + device IN endpoint 0 control + register (DIEP0CTL) + 0x100 + 0x20 + 0x00008000 + + + MPL + Maximum packet length + 0 + 2 + read-write + + + EPACT + endpoint active + 15 + 1 + read-only + + + NAKS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPD + Endpoint disable + 30 + 1 + read-write + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + + + DIEP1CTL + DIEP1CTL + device in endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + Set DATA1 PID/Set odd frame + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + TXFNUM + Tx FIFO number + 22 + 4 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DIEP2CTL + DIEP2CTL + device endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + Set DATA1 PID/Set odd frame + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + TXFNUM + Tx FIFO number + 22 + 4 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DIEP3CTL + DIEP3CTL + device endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + Set DATA1 PID/Set odd frame + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + TXFNUM + Tx FIFO number + 22 + 4 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DOEP0CTL + DOEP0CTL + device endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNOOP + Snoop mode + 20 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + NAKS + NAK status + 17 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-only + + + MPL + Maximum packet length + 0 + 2 + read-only + + + + + DOEP1CTL + DOEP1CTL + device endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + SD1PID/SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVENFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNOOP + Snoop mode + 20 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DOEP2CTL + DOEP2CTL + device endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + SD1PID/SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVENFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNOOP + Snoop mode + 20 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DOEP3CTL + DOEP3CTL + device endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + EPEN + Endpoint enable + 31 + 1 + read-write + + + EPD + Endpoint disable + 30 + 1 + read-write + + + SD1PID_SODDFRM + SD1PID/SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVENFRM + SD0PID/SEVENFRM + 28 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + CNAK + Clear NAK + 26 + 1 + write-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + SNOOP + Snoop mode + 20 + 1 + read-write + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + NAKS + NAK status + 17 + 1 + read-only + + + EOFRM_DPID + EOFRM/DPID + 16 + 1 + read-only + + + EPACT + Endpoint active + 15 + 1 + read-write + + + MPL + maximum packet length + 0 + 11 + read-write + + + + + DIEP0INTF + DIEP0INTF + device endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + IEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + EPTXFUD + Endpoint Tx FIFO underrun + 4 + 1 + read-write + + + CITO + Control in timeout interrupt + 3 + 1 + read-write + + + EPDIS + Endpoint finished + 1 + 1 + read-write + + + TF + Transfer finished + 0 + 1 + read-write + + + + + DIEP1INTF + DIEP1INTF + device endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + IEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + EPTXFUD + Endpoint Tx FIFO underrun + 4 + 1 + read-write + + + CITO + Control in timeout interrupt + 3 + 1 + read-write + + + EPDIS + Endpoint finished + 1 + 1 + read-write + + + TF + Transfer finished + 0 + 1 + read-write + + + + + DIEP2INTF + DIEP2INTF + device endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + IEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + EPTXFUD + Endpoint Tx FIFO underrun + 4 + 1 + read-write + + + CITO + Control in timeout interrupt + 3 + 1 + read-write + + + EPDIS + Endpoint finished + 1 + 1 + read-write + + + TF + Transfer finished + 0 + 1 + read-write + + + + + DIEP3INTF + DIEP3INTF + device endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + IEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + EPTXFUD + Endpoint Tx FIFO underrun + 4 + 1 + read-write + + + CITO + Control in timeout interrupt + 3 + 1 + read-write + + + EPDIS + Endpoint finished + 1 + 1 + read-write + + + TF + Transfer finished + 0 + 1 + read-write + + + + + DOEP0INTF + DOEP0INTF + device out endpoint-0 interrupt flag + register + 0x308 + 0x20 + read-write + 0x00000000 + + + BTBSTP + Back-to-back SETUP packets + 6 + 1 + + + EPRXFOVR + Endpoint Rx FIFO overrun + 4 + 1 + + + STPF + Setup phase finished + 3 + 1 + + + EPDIS + Endpoint disabled + 1 + 1 + + + TF + Transfer finished + 0 + 1 + + + + + DOEP1INTF + DOEP1INTF + device out endpoint-1 interrupt flag + register + 0x328 + 0x20 + read-write + 0x00000000 + + + BTBSTP + Back-to-back SETUP packets + 6 + 1 + + + EPRXFOVR + Endpoint Rx FIFO overrun + 4 + 1 + + + STPF + Setup phase finished + 3 + 1 + + + EPDIS + Endpoint disabled + 1 + 1 + + + TF + Transfer finished + 0 + 1 + + + + + DOEP2INTF + DOEP2INTF + device out endpoint-2 interrupt flag + register + 0x348 + 0x20 + read-write + 0x00000000 + + + BTBSTP + Back-to-back SETUP packets + 6 + 1 + + + EPRXFOVR + Endpoint Rx FIFO overrun + 4 + 1 + + + STPF + Setup phase finished + 3 + 1 + + + EPDIS + Endpoint disabled + 1 + 1 + + + TF + Transfer finished + 0 + 1 + + + + + DOEP3INTF + DOEP3INTF + device out endpoint-3 interrupt flag + register + 0x368 + 0x20 + read-write + 0x00000000 + + + BTBSTP + Back-to-back SETUP packets + 6 + 1 + + + EPRXFOVR + Endpoint Rx FIFO overrun + 4 + 1 + + + STPF + Setup phase finished + 3 + 1 + + + EPDIS + Endpoint disabled + 1 + 1 + + + TF + Transfer finished + 0 + 1 + + + + + DIEP0LEN + DIEP0LEN + device IN endpoint-0 transfer length + register + 0x110 + 0x20 + read-write + 0x00000000 + + + PCNT + Packet count + 19 + 2 + + + TLEN + Transfer length + 0 + 7 + + + + + DOEP0LEN + DOEP0LEN + device OUT endpoint-0 transfer length + register + 0x310 + 0x20 + read-write + 0x00000000 + + + STPCNT + SETUP packet count + 29 + 2 + + + PCNT + Packet count + 19 + 1 + + + TLEN + Transfer length + 0 + 7 + + + + + DIEP1LEN + DIEP1LEN + device IN endpoint-1 transfer length + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MCPF + Multi packet count per frame + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DIEP2LEN + DIEP2LEN + device IN endpoint-2 transfer length + register + 0x150 + 0x20 + read-write + 0x00000000 + + + MCPF + Multi packet count per frame + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DIEP3LEN + DIEP3LEN + device IN endpoint-3 transfer length + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MCPF + Multi packet count per frame + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DOEP1LEN + DOEP1LEN + device OUT endpoint-1 transfer length + register + 0x330 + 0x20 + read-write + 0x00000000 + + + STPCNT_RXDPID + SETUP packet count/Received data PID + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DOEP2LEN + DOEP2LEN + device OUT endpoint-2 transfer length + register + 0x350 + 0x20 + read-write + 0x00000000 + + + STPCNT_RXDPID + SETUP packet count/Received data PID + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DOEP3LEN + DOEP3LEN + device OUT endpoint-3 transfer length + register + 0x370 + 0x20 + read-write + 0x00000000 + + + STPCNT_RXDPID + SETUP packet count/Received data PID + 29 + 2 + + + PCNT + Packet count + 19 + 10 + + + TLEN + Transfer length + 0 + 19 + + + + + DIEP0TFSTAT + DIEP0TFSTAT + device IN endpoint 0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000200 + + + IEPTFS + IN endpoint TxFIFO space + remaining + 0 + 16 + + + + + DIEP1TFSTAT + DIEP1TFSTAT + device IN endpoint 1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000200 + + + IEPTFS + IN endpoint TxFIFO space + remaining + 0 + 16 + + + + + DIEP2TFSTAT + DIEP2TFSTAT + device IN endpoint 2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000200 + + + IEPTFS + IN endpoint TxFIFO space + remaining + 0 + 16 + + + + + DIEP3TFSTAT + DIEP3TFSTAT + device IN endpoint 3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000200 + + + IEPTFS + IN endpoint TxFIFO space + remaining + 0 + 16 + + + + + + + USBFS_PWRCLK + USB on the go full speed + USBFS + 0x50000E00 + + 0x0 + 0x100 + registers + + + + PWRCLKCTL + PWRCLKCTL + power and clock gating control + register (PWRCLKCTL) + 0x00 + 0x20 + read-write + 0x00000000 + + + SUCLK + Stop the USB clock + 0 + 1 + + + SHCLK + Stop HCLK + 1 + 1 + + + + + + + + WWDGT + Window watchdog timer + WWDGT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDGT + 0 + + + + CTL + CTL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGTEN + Activation bit + 7 + 1 + + + CNT + 7-bit counter + 0 + 7 + + + + + CFG + CFG + Configuration register + 0x04 + 0x20 + read-write + 0x0000007F + + + EWIE + Early wakeup interrupt + 9 + 1 + + + PSC + Prescaler + 7 + 2 + + + WIN + 7-bit window value + 0 + 7 + + + + + STAT + STAT + Status register + 0x08 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + diff --git a/platform.json b/platform.json index e5e8966..ead2fca 100644 --- a/platform.json +++ b/platform.json @@ -17,7 +17,7 @@ "type": "git", "url": "https://github.com/Nuclei-Software/platform-nuclei.git" }, - "version": "1.0.12", + "version": "1.2.0", "frameworks": { "nuclei-sdk": { "package": "framework-nuclei-sdk", @@ -28,28 +28,25 @@ } }, "packages": { - "toolchain-riscv-gcc-nuclei": { + "toolchain-riscv-nuclei": { "type": "toolchain", - "owner": "nuclei", - "version": "~9.2.1" + "version": "~1.1.0" }, "framework-nuclei-sdk": { "optional": true, "type": "framework", - "owner": "nuclei", - "version": "~0.3.1" + "version": ">=0.6.0" }, "tool-openocd-nuclei": { "optional": true, "type": "uploader", - "owner": "nuclei", - "version": "~0.10.2" + "version": "~1.1.0" }, "tool-jlink": { "type": "uploader", "optional": true, "owner": "platformio", - "version": "^1.65200.0" + "version": "^1.78811.0" } } } diff --git a/platform.py b/platform.py index 659bd90..5b1d29b 100644 --- a/platform.py +++ b/platform.py @@ -35,7 +35,7 @@ def _add_default_debug_tools(self, board): # debug tools debug = board.manifest.get("debug", {}) build = board.manifest.get("build", {}) - non_ftdi_tools = ["jlink", "gd-link", "rv-link", "altera-usb-blaster"] + non_ftdi_tools = ["jlink", "gd-link", "altera-usb-blaster"] upload_protocols = board.manifest.get("upload", {}).get("protocols", []) if "tools" not in debug: @@ -50,7 +50,7 @@ def _add_default_debug_tools(self, board): if link in debug["tools"]: continue - if link == "rv-link": + if link in ["rv-link", "gd-link"]: board_cfg = join( sdk_dir, "SoC", @@ -64,7 +64,7 @@ def _add_default_debug_tools(self, board): sdk_dir, "SoC", build_soc, "Board", build_board, "openocd.cfg", ) server_args = ["-c", "debug_level 1", "-f", board_cfg] - debug["tools"]["rv-link"] = { + debug["tools"][link] = { "hwids": [["0x28e9", "0x018a"]], "require_debug_port": True, } @@ -139,15 +139,23 @@ def _add_default_debug_tools(self, board): }, "init_cmds": [ "define pio_reset_halt_target", - " monitor halt", + " monitor reset halt", "end", "define pio_reset_run_target", + " interrupt" " monitor halt", + " monitor reset halt", " monitor resume", "end", + "define pio_restart_target", + " pio_reset_halt_target", + " $LOAD_CMDS", + " $INIT_BREAK", + " continue", + "end", "target extended-remote $DEBUG_PORT", - "$LOAD_CMDS", "pio_reset_halt_target", + "$LOAD_CMDS", "$INIT_BREAK", ], "onboard": link in debug.get("onboard_tools", []),