diff --git a/src/main/scala/nutcore/backend/fu/CSR.scala b/src/main/scala/nutcore/backend/fu/CSR.scala
index 3e594656..5071af6d 100644
--- a/src/main/scala/nutcore/backend/fu/CSR.scala
+++ b/src/main/scala/nutcore/backend/fu/CSR.scala
@@ -385,7 +385,9 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
 
     // User Trap Handling
     // MaskedRegMap(Uscratch, uscratch),
-    // MaskedRegMap(Uepc, uepc),
+    //Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use
+    //MaskedRegMap(Uepc, uepc, wfn = (value: UInt) => (value & ~1.U(64.W))),
+
     // MaskedRegMap(Ucause, ucause),
     // MaskedRegMap(Utval, utval),
     // MaskedRegMap(Uip, uip),
@@ -411,7 +413,9 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
 
     // Supervisor Trap Handling
     MaskedRegMap(Sscratch, sscratch),
-    MaskedRegMap(Sepc, sepc),
+    //Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use
+    MaskedRegMap(Sepc, sepc, wfn = (value: UInt) => (value & ~1.U(64.W))),
+
     MaskedRegMap(Scause, scause),
     MaskedRegMap(Stval, stval),
     MaskedRegMap(Sip, mip.asUInt, sipMask, MaskedRegMap.Unwritable, sipMask),
@@ -437,7 +441,10 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
 
     // Machine Trap Handling
     MaskedRegMap(Mscratch, mscratch),
-    MaskedRegMap(Mepc, mepc),
+    //MaskedRegMap(Mepc, mepc),
+    //Ensure that the value of epc[0] is 0 at the root, rather than clearing it at the time of use
+    MaskedRegMap(Mepc, mepc, wfn = (value: UInt) => (value & ~1.U(64.W))),
+
     MaskedRegMap(Mcause, mcause),
     MaskedRegMap(Mtval, mtval),
     MaskedRegMap(Mip, mip.asUInt, 0.U, MaskedRegMap.Unwritable),
@@ -668,7 +675,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     mstatusNew.mpp := ModeU
     mstatus := mstatusNew.asUInt
     lr := false.B
-    retTarget := mepc(VAddrBits-1, 0)
+    retTarget := mepc
   }
 
   when (valid && isSret) {
@@ -681,7 +688,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     mstatusNew.spp := ModeU
     mstatus := mstatusNew.asUInt
     lr := false.B
-    retTarget := sepc(VAddrBits-1, 0)
+    retTarget := sepc
   }
 
   when (valid && isUret) {
@@ -692,7 +699,7 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     priviledgeMode := ModeU
     mstatusNew.pie.u := true.B
     mstatus := mstatusNew.asUInt
-    retTarget := uepc(VAddrBits-1, 0)
+    retTarget := uepc
   }
 
   when (raiseExceptionIntr) {
@@ -946,3 +953,4 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{
     }
   }
 }
+