From 2c6b108c5b738bffbc0720a4741fd5ea131b7cfa Mon Sep 17 00:00:00 2001
From: klin02 <youkunlin20@mails.ucas.ac.cn>
Date: Wed, 6 Mar 2024 10:00:01 +0800
Subject: [PATCH 1/2] Support Difftest Argparser

This commit is only for dev-difftest to pass difftest CI. We will
add formal commit to master when bump difftest.
---
 Makefile                     | 6 +++---
 src/test/scala/TopMain.scala | 9 +++++----
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/Makefile b/Makefile
index 59c0fdfd..b1b02feb 100644
--- a/Makefile
+++ b/Makefile
@@ -21,14 +21,14 @@ DATAWIDTH ?= 64
 BOARD ?= sim  # sim  pynq  axu3cg
 CORE  ?= inorder  # inorder  ooo  embedded
 
-MILL_ARGS = -td $(RTL_DIR) BOARD=$(BOARD) CORE=$(CORE)
+override MILL_ARGS += -td $(RTL_DIR) BOARD=$(BOARD) CORE=$(CORE)
 FPGA_ARGS =
 
 ifneq ($(FIRTOOL),)
-MILL_ARGS += --firtool-binary-path $(FIRTOOL)
+override MILL_ARGS += --firtool-binary-path $(FIRTOOL)
 endif
 
-MILL_ARGS += --split-verilog
+override MILL_ARGS += --split-verilog
 
 .DEFAULT_GOAL = verilog
 
diff --git a/src/test/scala/TopMain.scala b/src/test/scala/TopMain.scala
index 4bb8c872..8e67f9f7 100644
--- a/src/test/scala/TopMain.scala
+++ b/src/test/scala/TopMain.scala
@@ -43,8 +43,9 @@ object TopMain extends App {
     require(target != "")
     target.substring(info.length()+1)
   }
-  val board = parseArgs("BOARD", args)
-  val core = parseArgs("CORE", args)
+  val newArgs = DifftestModule.parseArgs(args)
+  val board = parseArgs("BOARD", newArgs)
+  val core = parseArgs("CORE", newArgs)
 
   val s = (board match {
     case "sim"    => Nil
@@ -71,10 +72,10 @@ object TopMain extends App {
   else {
     ChiselGeneratorAnnotation(() => new Top)
   }
-  var exe_args = args.filter{
+  var exe_args = newArgs.filter{
     value => value.forall(char => char!='=')
   }
-  (new ChiselStage).execute(args, Seq(generator)
+  (new ChiselStage).execute(newArgs, Seq(generator)
     :+ CIRCTTargetAnnotation(CIRCTTarget.SystemVerilog)
     :+ FirtoolOption("--disable-annotation-unknown")
   )

From eb9914248c322d2f03beb0bba82b1d245d2fe17b Mon Sep 17 00:00:00 2001
From: Yinan Xu <xuyinan@ict.ac.cn>
Date: Sat, 9 Mar 2024 17:52:29 +0800
Subject: [PATCH 2/2] Bump Chisel 6.2.0 and Mill 0.11.7

---
 .mill-version |  2 +-
 Makefile      | 13 +++++++------
 build.sc      |  4 ++--
 difftest      |  2 +-
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/.mill-version b/.mill-version
index e5cbde33..b80f98e6 100644
--- a/.mill-version
+++ b/.mill-version
@@ -1 +1 @@
-0.11.6
+0.11.7
diff --git a/Makefile b/Makefile
index b1b02feb..5ef0a6d7 100644
--- a/Makefile
+++ b/Makefile
@@ -21,23 +21,24 @@ DATAWIDTH ?= 64
 BOARD ?= sim  # sim  pynq  axu3cg
 CORE  ?= inorder  # inorder  ooo  embedded
 
-override MILL_ARGS += -td $(RTL_DIR) BOARD=$(BOARD) CORE=$(CORE)
+MILL_ARGS_ALL  = $(MILL_ARGS)
+MILL_ARGS_ALL += --target-dir $(RTL_DIR) BOARD=$(BOARD) CORE=$(CORE)
 FPGA_ARGS =
 
 ifneq ($(FIRTOOL),)
-override MILL_ARGS += --firtool-binary-path $(FIRTOOL)
+MILL_ARGS_ALL += --firtool-binary-path $(FIRTOOL)
 endif
 
-override MILL_ARGS += --split-verilog
+MILL_ARGS_ALL += --split-verilog
 
 .DEFAULT_GOAL = verilog
 
 help:
-	mill -i generator.test.runMain top.$(TOP) --help $(MILL_ARGS)
+	mill -i generator.test.runMain top.$(TOP) --help $(MILL_ARGS_ALL)
 
 $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
-	mill -i generator.test.runMain top.$(TOP) $(MILL_ARGS) $(FPGA_ARGS)
+	mill -i generator.test.runMain top.$(TOP) $(MILL_ARGS_ALL) $(FPGA_ARGS)
 	@mv $(SIM_TOP_V) $(TOP_V)
 	sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
 	@git log -n 1 >> .__head__
@@ -60,7 +61,7 @@ verilog: $(TOP_V)
 
 $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	mkdir -p $(@D)
-	mill -i generator.test.runMain $(SIMTOP) $(MILL_ARGS)
+	mill -i generator.test.runMain $(SIMTOP) $(MILL_ARGS_ALL)
 	@for file in $(RTL_DIR)/*.$(RTL_SUFFIX); do                               \
 		sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' "$$file";           \
 		sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" "$$file";    \
diff --git a/build.sc b/build.sc
index c956dd59..4ff8dc3a 100644
--- a/build.sc
+++ b/build.sc
@@ -3,8 +3,8 @@ import coursier.maven.MavenRepository
 
 object ivys {
   val scala = "2.13.12"
-  val chisel = ivy"org.chipsalliance::chisel:6.1.0"
-  val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.1.0"
+  val chisel = ivy"org.chipsalliance::chisel:6.2.0"
+  val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.2.0"
 }
 
 trait CommonModule extends ScalaModule {
diff --git a/difftest b/difftest
index 08260b42..d9d86f45 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 08260b420e8447c539056555eba14fda19c5d07f
+Subproject commit d9d86f454fd707934d328d185481c02adaec37f0