diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 965159605..6f438aba8 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -45,7 +45,15 @@ jobs: source ./env.sh make clean make verilog - + - name: Generate Verilog for FPGA + run: | + cd $GITHUB_WORKSPACE/../xs-env + source ./env.sh + cd $GITHUB_WORKSPACE/../xs-env/NutShell + source ./env.sh + make clean + make verilog BOARD=pynq + - name: Microbench - Nutshell run: | cd $GITHUB_WORKSPACE/../xs-env diff --git a/Makefile b/Makefile index d1bc70153..ad2876460 100644 --- a/Makefile +++ b/Makefile @@ -1,12 +1,13 @@ TOP = TopMain SIM_TOP = SimTop -FPGATOP = NutShellFPGATop +FPGATOP = Top +REAL_TOP = $(if $(strip $(subst sim,,$(BOARD))),$(FPGATOP),$(SIM_TOP)) BUILD_DIR = $(abspath ./build) RTL_DIR = $(BUILD_DIR)/rtl RTL_SUFFIX ?= sv -SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) +SIM_TOP_V = $(RTL_DIR)/$(REAL_TOP).$(RTL_SUFFIX) # if use FPGA, use FPGATOP TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') @@ -40,7 +41,9 @@ $(TOP_V): $(SCALA_FILE) mkdir -p $(@D) mill -i generator.test.runMain top.$(TOP) $(MILL_ARGS_ALL) $(FPGA_ARGS) @mv $(SIM_TOP_V) $(TOP_V) - sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@ + @for file in $(RTL_DIR)/*.$(RTL_SUFFIX); do \ + sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' "$$file"; \ + done @git log -n 1 >> .__head__ @git diff >> .__diff__ @sed -i 's/^/\/\// ' .__head__ diff --git a/fpga/NutShell.tcl b/fpga/NutShell.tcl index 98371fbed..8a1edbc4f 100644 --- a/fpga/NutShell.tcl +++ b/fpga/NutShell.tcl @@ -25,9 +25,7 @@ set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 + catch {common::send_msg_id "BD_TCL-1002" "WARNING" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} } ################################################################ diff --git a/fpga/board/PXIe/bd/arm.tcl b/fpga/board/PXIe/bd/arm.tcl index dfe783a0c..415dbf2e1 100644 --- a/fpga/board/PXIe/bd/arm.tcl +++ b/fpga/board/PXIe/bd/arm.tcl @@ -25,9 +25,7 @@ set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 + catch {common::send_msg_id "BD_TCL-1002" "WARNING" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} } ################################################################ diff --git a/fpga/board/axu3cg/bd/arm.tcl b/fpga/board/axu3cg/bd/arm.tcl index cb59744af..d61e24e4e 100644 --- a/fpga/board/axu3cg/bd/arm.tcl +++ b/fpga/board/axu3cg/bd/arm.tcl @@ -25,9 +25,7 @@ set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 + catch {common::send_msg_id "BD_TCL-1002" "WARNING" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} } ################################################################ diff --git a/fpga/board/common.tcl b/fpga/board/common.tcl index 1ea7bf71b..ae7cb7af3 100644 --- a/fpga/board/common.tcl +++ b/fpga/board/common.tcl @@ -30,6 +30,7 @@ set bd_dir ${script_dir}/bd set constr_dir ${script_dir}/constr set data_dir ${script_dir}/data set ip_dir ${script_dir}/ip +set nutshell_build_dir ${fpga_dir}/../build/rtl create_project $project_name -force -dir $project_dir/ -part ${device} if {[info exists board]} { @@ -44,17 +45,15 @@ add_files -norecurse -fileset sources_1 $inc_files set_property is_global_include true [get_files $inc_files] # Add files for nutshell -lappend src_files "[file normalize "${fpga_dir}/../build/TopMain.v"]" \ - "[file normalize "${fpga_dir}/../build/DifftestRunaheadEvent.v"]" \ - "[file normalize "${fpga_dir}/../build/DifftestRunaheadRedirectEvent.v"]" +set nutshell_rtl [glob -d ${nutshell_build_dir} *.sv or *.v] -add_files -norecurse -fileset sources_1 $src_files +foreach src_file ${nutshell_rtl} { + lappend src_files [file normalize $src_file] +} -# Mark file type of difftest files as SystemVerilog to support DPI statements -set_property file_type SystemVerilog -objects [get_files -of_objects [get_filesets sources_1] [list \ - "*/DifftestRunaheadRedirectEvent.v" \ - "*/DifftestRunaheadEvent.v" \ -]] +add_files -norecurse -fileset sources_1 $src_files +set_property file_type Verilog -objects [get_files -of_objects [get_filesets sources_1] *NutShell.sv] +# vivado do not support a system verilog file be the top of a reference design, this may be removed as reference design is not need actually if {[info exists xdc_files]} { add_files -norecurse -fileset constrs_1 $xdc_files diff --git a/fpga/board/pynq/bd/standalone.tcl b/fpga/board/pynq/bd/standalone.tcl index 1051bd7dd..72cc34184 100644 --- a/fpga/board/pynq/bd/standalone.tcl +++ b/fpga/board/pynq/bd/standalone.tcl @@ -25,9 +25,7 @@ set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 + catch {common::send_msg_id "BD_TCL-1002" "WARNING" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} } ################################################################ diff --git a/src/main/scala/nutcore/backend/fu/CSR.scala b/src/main/scala/nutcore/backend/fu/CSR.scala index c197df88e..9a9e41a20 100644 --- a/src/main/scala/nutcore/backend/fu/CSR.scala +++ b/src/main/scala/nutcore/backend/fu/CSR.scala @@ -885,7 +885,11 @@ class CSR(implicit val p: NutCoreConfig) extends NutCoreModule with HasCSRConst{ }} val nutcoretrap = WireInit(false.B) - BoringUtils.addSink(nutcoretrap, "nutcoretrap") + if (!p.FPGAPlatform) { + BoringUtils.addSink(nutcoretrap, "nutcoretrap") + } else { + nutcoretrap := 0.U + } def readWithScala(addr: Int): UInt = mapping(addr)._1 if (!p.FPGAPlatform) { diff --git a/src/main/scala/top/Settings.scala b/src/main/scala/top/Settings.scala index 95605c413..2d988e8cc 100644 --- a/src/main/scala/top/Settings.scala +++ b/src/main/scala/top/Settings.scala @@ -51,21 +51,24 @@ object PynqSettings { "MemMapBase" -> 0x0000000010000000L, "MemMapRegionBits" -> 28, "MMIOBase" -> 0x00000000e0000000L, - "MMIOSize" -> 0x0000000020000000L + "MMIOSize" -> 0x0000000020000000L, + "EnableDebug" -> false ) } object Axu3cgSettings { def apply() = Map( "FPGAPlatform" -> true, - "NrExtIntr" -> 2 + "NrExtIntr" -> 2, + "EnableDebug" -> false ) } object PXIeSettings { def apply() = Map( "FPGAPlatform" -> true, - "NrExtIntr" -> 5 + "NrExtIntr" -> 5, + "EnableDebug" -> false ) } diff --git a/src/main/scala/utils/Debug.scala b/src/main/scala/utils/Debug.scala index 98fa133a1..4bd0183ba 100644 --- a/src/main/scala/utils/Debug.scala +++ b/src/main/scala/utils/Debug.scala @@ -42,12 +42,14 @@ object LogUtil { def apply(debugLevel: LogLevel) (prefix: Boolean, cond: Bool, pable: Printable) (implicit name: String): Any = { - val c = control() - val commonInfo = p"[${c._2}] $name: " - when (cond && c._1) { - if(prefix) printf(commonInfo) - printf(pable) - } + if (NutCoreConfig().EnableDebug){ + val c = control() + val commonInfo = p"[${c._2}] $name: " + when (cond && c._1) { + if(prefix) printf(commonInfo) + printf(pable) + } + } } }