Usage:
- Put your RTL source files under
src/ - Set the correct top module name and file list in
config.tcl - Change the FPGA device in
config.tclif necessary - Modify the clock port name and clock frequency in
constr/constr.xdc - Run
make - Get reports under
report/
Note: if the file list is updated, you should clean the old project
by make clean first to make it take effect.