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boards.cfg
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boards.cfg
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#
# List of boards
#
# Syntax:
# white-space separated list of entries;
# each entry has the fields documented below.
#
# Unused fields can be specified as "-", or omitted if they
# are the last field on the line.
#
# Lines starting with '#' are comments.
# Blank lines are ignored.
#
# The CPU field takes the form:
# cpu[:spl_cpu]
# If spl_cpu is specified the make variable CPU will be set to this
# during the SPL build.
#
# The options field takes the form:
# <board config name>[:comma separated config options]
# Each config option has the form (value defaults to "1"):
# option[=value]
# So if you have:
# FOO:HAS_BAR,BAZ=64
# The file include/configs/FOO.h will be used, and these defines created:
# #define CONFIG_HAS_BAR 1
# #define CONFIG_BAZ 64
#
# The list should be ordered according to the following fields,
# from most to least significant:
#
# ARCH, CPU, SoC, Vendor, Target
#
# To keep the list sorted, use something like
# :.,$! sort -bdf -k2,2 -k3,3 -k6,6 -k5,5 -k1,1
#
# To reformat the list, use something like
# :.,$! column -t
#
# Target ARCH CPU Board name Vendor SoC Options
###########################################################################################################
burner_jz4775_ddr3 mips xburst burner_jz4775 ingenic jz4775 burner_jz4775:DDR_TYPE_DDR3
burner_jz4775_lpddr mips xburst burner_jz4775 ingenic jz4775 burner_jz4775:DDR_TYPE_LPDDR,SPL_DDR_SOFT_TRAINING
burner_jz4775_ddr2 mips xburst burner_jz4775 ingenic jz4775 burner_jz4775:DDR_TYPE_DDR2
burner_jz4780_ddr3 mips xburst burner_jz4780 ingenic jz4780 burner_jz4780:DDR_TYPE_DDR3
burner_jz4780_lpddr mips xburst burner_jz4780 ingenic jz4780 burner_jz4780:DDR_TYPE_LPDDR
burner_jz4780_lpddr2 mips xburst burner_jz4780 ingenic jz4780 burner_jz4780:DDR_TYPE_LPDDR2
burner_m200_ddr3 mips xburst burner_m200 ingenic m200 burner_m200:DDR_TYPE_DDR3
burner_m200_lpddr mips xburst burner_m200 ingenic m200 burner_m200:DDR_TYPE_LPDDR
burner_m200_lpddr2 mips xburst burner_m200 ingenic m200 burner_m200:DDR_TYPE_LPDDR2
burner_t15_ddr3 mips xburst burner_t15 ingenic t15 burner_t15:DDR_TYPE_DDR3
burner_t15_lpddr mips xburst burner_t15 ingenic t15 burner_t15:DDR_TYPE_LPDDR
burner_t15_lpddr2 mips xburst burner_t15 ingenic t15 burner_t15:DDR_TYPE_LPDDR2
######################################################################################################################
#################################################### T41 start #######################################################
###T41L###
isvp_t41l_msc0 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41L
isvp_t41l_msc1 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41L
isvp_t41l_sfc_nor mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41L
isvp_t41l_sfc0_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41L
isvp_t41l_sfc1_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41L
isvp_t41l_uart_sfc mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41L
isvp_t41l_uart_msc mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41L
isvp_t41l_sfc_params mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41L
isvp_t41l_msc0_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41L,LP
isvp_t41l_msc1_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41L,LP
isvp_t41l_sfc_nor_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41L,LP
isvp_t41l_sfc0_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41L,LP
isvp_t41l_sfc1_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41L,LP
isvp_t41l_uart_sfc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41L,LP
isvp_t41l_uart_msc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41L,LP
isvp_t41l_sfc_params_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41L,LP
###T41LQ###
isvp_t41lq_msc0 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41LQ
isvp_t41lq_msc1 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41LQ
isvp_t41lq_sfc_nor mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41LQ
isvp_t41lq_sfc0_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41LQ
isvp_t41lq_sfc1_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41LQ
isvp_t41lq_uart_sfc mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41LQ
isvp_t41lq_uart_msc mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41LQ
isvp_t41lq_sfc_params mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41LQ
isvp_t41lq_msc0_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41LQ,LP
isvp_t41lq_msc1_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41LQ,LP
isvp_t41lq_sfc_nor_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41LQ,LP
isvp_t41lq_sfc0_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41LQ,LP
isvp_t41lq_sfc1_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41LQ,LP
isvp_t41lq_uart_sfc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41LQ,LP
isvp_t41lq_uart_msc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41LQ,LP
isvp_t41lq_sfc_params_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41LQ,LP
###T41N###
isvp_t41n_msc0 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41N
isvp_t41n_msc1 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41N
isvp_t41n_sfc_nor mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41N
isvp_t41n_sfc0_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41N
isvp_t41n_sfc1_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41N
isvp_t41n_uart_sfc mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41N
isvp_t41n_uart_msc mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41N
isvp_t41n_sfc_params mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41N
isvp_t41n_msc0_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41N,LP
isvp_t41n_msc1_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41N,LP
isvp_t41n_sfc_nor_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41N,LP
isvp_t41n_sfc0_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41N,LP
isvp_t41n_sfc1_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41N,LP
isvp_t41n_uart_sfc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41N,LP
isvp_t41n_uart_msc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41N,LP
isvp_t41n_sfc_params_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41N,LP
###T41NQ###
isvp_t41nq_msc0 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41NQ
isvp_t41nq_msc1 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41NQ
isvp_t41nq_sfc_nor mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41NQ
isvp_t41nq_sfc0_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41NQ
isvp_t41nq_sfc1_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41NQ
isvp_t41nq_uart_sfc mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41NQ
isvp_t41nq_uart_msc mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41NQ
isvp_t41nq_sfc_params mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41NQ
isvp_t41nq_msc0_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41NQ,LP
isvp_t41nq_msc1_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41NQ,LP
isvp_t41nq_sfc_nor_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41NQ,LP
isvp_t41nq_sfc0_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41NQ,LP
isvp_t41nq_sfc1_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41NQ,LP
isvp_t41nq_uart_sfc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41NQ,LP
isvp_t41nq_uart_msc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41NQ,LP
isvp_t41nq_sfc_params_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41NQ,LP
###T41A###
isvp_t41a_msc0 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41A
isvp_t41a_msc1 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41A
isvp_t41a_sfc_nor mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41A
isvp_t41a_sfc0_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41A
isvp_t41a_sfc1_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41A
isvp_t41a_uart_sfc mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41A
isvp_t41a_uart_msc mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41A
isvp_t41a_sfc_params mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41A
###T41ZX###
isvp_t41zx_msc0 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41ZX
isvp_t41zx_msc1 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41ZX
isvp_t41zx_sfc_nor mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41ZX
isvp_t41zx_sfc0_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41ZX
isvp_t41zx_sfc1_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41ZX
isvp_t41zx_uart_sfc mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41ZX
isvp_t41zx_uart_msc mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41ZX
isvp_t41zx_sfc_params mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41ZX
isvp_t41zx_msc0_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41ZX,LP
isvp_t41zx_msc1_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41ZX,LP
isvp_t41zx_sfc_nor_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41ZX,LP
isvp_t41zx_sfc0_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41ZX,LP
isvp_t41zx_sfc1_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41ZX,LP
isvp_t41zx_uart_sfc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41ZX,LP
isvp_t41zx_uart_msc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41ZX,LP
isvp_t41zx_sfc_params_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41ZX,LP
###T41XQ###
isvp_t41xq_msc0 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41XQ
isvp_t41xq_msc1 mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41XQ
isvp_t41xq_sfc_nor mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41XQ
isvp_t41xq_sfc0_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41XQ
isvp_t41xq_sfc1_nand mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41XQ
isvp_t41xq_uart_sfc mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41XQ
isvp_t41xq_uart_msc mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41XQ
isvp_t41xq_sfc_params mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41XQ
isvp_t41xq_msc0_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,T41XQ,LP
isvp_t41xq_msc1_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMAND,T41XQ,LP
isvp_t41xq_sfc_nor_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,T41XQ,LP
isvp_t41xq_sfc0_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC0_NAND,T41XQ,LP
isvp_t41xq_sfc1_nand_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SFC_NAND,SPL_SFC_NAND,JZ_MMC_MSC0,SFC1_NAND,T41XQ,LP
isvp_t41xq_uart_sfc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41XQ,LP
isvp_t41xq_uart_msc_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC0,SFC_COMMAND,UART_LOAD,T41XQ,LP
isvp_t41xq_sfc_params_lp mips xburst2 isvp_t41 ingenic t41 isvp_t41:ENV_IS_IN_SPI_FLASH,SPL_SFC_NOR,JZ_MMC_MSC0,SFC0_NOR,SFC1_NOR,SPL_PARAMS_FIXER,T41XQ,LP
#################################################### T41 end #########################################################
######################################################################################################################
columba_uImage_rvms_sfcnor mips xburst columba ingenic t10 columba:SPL_SFC_SUPPORT,SFC_NOR
bootes_uImage_rvms_msc1 mips xburst bootes ingenic t15 bootes:SPL_MMC_SUPPORT,ENV_IS_IN_MMC,GPT_CREATOR,JZ_MMC_MSC1,SFC_COMMOND
bootes_uImage_rvms_sfcnor_16M mips xburst bootes ingenic t15 bootes:SPL_SFC_SUPPORT,ENV_IS_IN_SPI_FLASH,SFC_NOR,SFC_NOR_16M
bootes_uImage_rvms_sfcnor_8M mips xburst bootes ingenic t15 bootes:SPL_SFC_SUPPORT,ENV_IS_IN_SPI_FLASH,SFC_NOR,SFC_NOR_8M
bootes_uImage_rvms_sfcnor_4M mips xburst bootes ingenic t15 bootes:SPL_SFC_SUPPORT,ENV_IS_IN_SPI_FLASH,SFC_NOR,SFC_NOR_4M
# Target ARCH CPU Board name Vendor SoC Options
########################################################################################################################