From 7e50c7a8d3a501ed2640edc34a28e1bcf1c8550b Mon Sep 17 00:00:00 2001 From: tastynoob <934348725@qq.com> Date: Thu, 15 Aug 2024 10:38:41 +0800 Subject: [PATCH] mem-ruby: set ruby clock to 3GHz, enlarge memory bandwidth Change-Id: Icf0d09d583052ee376e934c2abbadf0fb878c640 --- configs/ruby/CHI.py | 4 ++-- configs/ruby/CHI_config.py | 24 ++++++++++++++------ configs/ruby/Ruby.py | 2 +- src/cpu/o3/issue_queue.cc | 3 +++ src/mem/ruby/network/BasicLink.py | 4 ++-- src/mem/ruby/network/simple/SimpleNetwork.py | 2 +- src/mem/ruby/slicc_interface/Controller.py | 2 +- 7 files changed, 27 insertions(+), 14 deletions(-) diff --git a/configs/ruby/CHI.py b/configs/ruby/CHI.py index e2fa75c29b..683e6abd9e 100644 --- a/configs/ruby/CHI.py +++ b/configs/ruby/CHI.py @@ -126,14 +126,14 @@ class L1DCache(RubyCache): class L2Cache(RubyCache): level = 2 - dataAccessLatency = 6 + dataAccessLatency = 13 tagAccessLatency = 2 size = options.l2_size assoc = options.l2_assoc class HNFCache(RubyCache): level = 3 - dataAccessLatency = 10 + dataAccessLatency = 17 tagAccessLatency = 2 size = options.l3_size assoc = options.l3_assoc diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py index bfc9b83942..9df852f83c 100644 --- a/configs/ruby/CHI_config.py +++ b/configs/ruby/CHI_config.py @@ -86,9 +86,9 @@ class NoC_Params: router_link_latency = 1 node_link_latency = 1 router_latency = 1 - router_buffer_size = 4 - cntrl_msg_size = 8 - data_width = 32 + router_buffer_size = 128 + cntrl_msg_size = 0 + data_width = 64 cross_links = [] cross_link_latency = 0 @@ -257,7 +257,7 @@ def __init__(self, ruby_system, sequencer, cache, prefetcher, is_dcache=False): self.dealloc_backinv_shared = False self.is_dcache = is_dcache # Some reasonable default TBE params - self.number_of_TBEs = 32 + self.number_of_TBEs = 32+8 self.number_of_repl_TBEs = 16 self.number_of_snoop_TBEs = 4 self.number_of_DVM_TBEs = 16 @@ -265,6 +265,9 @@ def __init__(self, ruby_system, sequencer, cache, prefetcher, is_dcache=False): self.unify_repl_TBEs = False + self.response_latency = 4 + self.request_latency = 1 + class CHI_L2Controller(CHI_Cache_Controller): """ @@ -295,13 +298,15 @@ def __init__(self, ruby_system, cache, prefetcher): self.dealloc_backinv_unique = False self.dealloc_backinv_shared = False # Some reasonable default TBE params - self.number_of_TBEs = 64 + self.number_of_TBEs = 64+16 self.number_of_repl_TBEs = 32 - self.number_of_snoop_TBEs = 16 + self.number_of_snoop_TBEs = 32 self.number_of_DVM_TBEs = 1 # should not receive any dvm self.number_of_DVM_snoop_TBEs = 1 # should not receive any dvm self.unify_repl_TBEs = False + self.response_latency = 12 + self.request_latency = 1 class CHI_HNFController(CHI_Cache_Controller): """ @@ -333,13 +338,17 @@ def __init__(self, ruby_system, cache, prefetcher, addr_ranges): self.dealloc_backinv_unique = False self.dealloc_backinv_shared = False # Some reasonable default TBE params - self.number_of_TBEs = 256 + self.number_of_TBEs = 256 + 32 self.number_of_repl_TBEs = 32 self.number_of_snoop_TBEs = 1 # should not receive any snoop self.number_of_DVM_TBEs = 1 # should not receive any dvm self.number_of_DVM_snoop_TBEs = 1 # should not receive any dvm self.unify_repl_TBEs = False + self.response_latency = 40 + self.request_latency = 1 + + class CHI_MNController(MiscNode_Controller): """ @@ -711,6 +720,7 @@ def __init__(self, ruby_system, parent): requestToMemory=MemCtrlMessageBuffer(), reqRdy=TriggerMessageBuffer(), transitions_per_cycle=1024, + number_of_TBEs = 1024 ) # The Memory_Controller implementation deallocates the TBE for diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index 305f6f5ccb..0e31196bab 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -69,7 +69,7 @@ def define_options(parser): "--ruby-clock", action="store", type=str, - default="2GHz", + default="3GHz", help="Clock for blocks running at Ruby system's speed", ) diff --git a/src/cpu/o3/issue_queue.cc b/src/cpu/o3/issue_queue.cc index bf59ef64e1..5b7d16bb00 100644 --- a/src/cpu/o3/issue_queue.cc +++ b/src/cpu/o3/issue_queue.cc @@ -709,6 +709,9 @@ Scheduler::insertSlot(const DynInstPtr& inst) void Scheduler::loadCancel(const DynInstPtr& inst) { + if (inst->canceled()) { + return; + } DPRINTF(Schedule, "[sn %lu] %s cache miss, cancel consumers\n", inst->seqNum, enums::OpClassStrings[inst->opClass()]); inst->setCancel(); diff --git a/src/mem/ruby/network/BasicLink.py b/src/mem/ruby/network/BasicLink.py index a275d9bd85..4515506c32 100644 --- a/src/mem/ruby/network/BasicLink.py +++ b/src/mem/ruby/network/BasicLink.py @@ -54,7 +54,7 @@ class BasicExtLink(BasicLink): ext_node = Param.RubyController("External node") int_node = Param.BasicRouter("ID of internal node") - bandwidth_factor = 16 # only used by simple network + bandwidth_factor = 64 # only used by simple network class BasicIntLink(BasicLink): @@ -70,4 +70,4 @@ class BasicIntLink(BasicLink): dst_inport = Param.String("", "Inport direction at dst router") # only used by simple network - bandwidth_factor = 16 + bandwidth_factor = 64 diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py index e52333b24d..ea0dfcecee 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.py +++ b/src/mem/ruby/network/simple/SimpleNetwork.py @@ -55,7 +55,7 @@ class SimpleNetwork(RubyNetwork): "default internal buffer size for links and\ routers; 0 indicates infinite buffering", ) - endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor") + endpoint_bandwidth = Param.Int(2048, "bandwidth adjustment factor") physical_vnets_channels = VectorParam.Int( [], diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index ef8a0afbf1..ead3327617 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -54,7 +54,7 @@ class RubyController(ClockedObject): cluster_id = Param.UInt32(0, "Id of this controller's cluster") transitions_per_cycle = Param.Int( - 32, "no. of SLICC state machine transitions per cycle" + 1024, "no. of SLICC state machine transitions per cycle" ) buffer_size = Param.UInt32(0, "max buffer size 0 means infinite")