From 3e2798e618ea9f8abee351da37d94c16ac921453 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Sat, 11 May 2024 17:03:59 +0800 Subject: [PATCH] configs: Use MaxHartIdBits for hartIdLen Signed-off-by: Yangyu Chen --- src/main/scala/huancun/HuanCun.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/huancun/HuanCun.scala b/src/main/scala/huancun/HuanCun.scala index 5722a713..52f9eb9c 100644 --- a/src/main/scala/huancun/HuanCun.scala +++ b/src/main/scala/huancun/HuanCun.scala @@ -23,6 +23,7 @@ import org.chipsalliance.cde.config.Parameters import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy._ +import freechips.rocketchip.tile.MaxHartIdBits import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink.TLMessages._ import freechips.rocketchip.util.{BundleField, BundleFieldBase, UIntToOH1} @@ -103,7 +104,7 @@ trait HasHuanCunParameters { lazy val outerSinkBits = edgeOut.bundle.sinkBits - lazy val hartIdLen: Int = log2Up(cacheParams.hartIds.length) + lazy val hartIdLen: Int = p(MaxHartIdBits) val block_granularity = if (!cacheParams.inclusive && cacheParams.clientCaches.nonEmpty) { cacheParams.clientCaches.head.blockGranularity