diff --git a/Utility b/Utility
index 575aff86..1b7acf09 160000
--- a/Utility
+++ b/Utility
@@ -1 +1 @@
-Subproject commit 575aff86cc7463193671542e6adad565c2437c6e
+Subproject commit 1b7acf0998ddf175527aa0609788c3fea1262b1f
diff --git a/rocket-chip b/rocket-chip
index 16b7bcb0..175dfe09 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 16b7bcb013350e49c9c11d80e17dcff842fccfd6
+Subproject commit 175dfe096e3b7c630f93ef328df1cf0b2ed55de1
diff --git a/src/main/scala/huancun/inclusive/MSHR.scala b/src/main/scala/huancun/inclusive/MSHR.scala
index df4ac155..eec60539 100644
--- a/src/main/scala/huancun/inclusive/MSHR.scala
+++ b/src/main/scala/huancun/inclusive/MSHR.scala
@@ -109,7 +109,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr
         Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
         MuxLookup(
           meta.state,
-          BRANCH,
+          BRANCH)(
           Seq(
             INVALID -> BRANCH,
             BRANCH -> BRANCH,
@@ -392,7 +392,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr
     req.fromB,
     MuxLookup(
       Cat(meta.state, probe_next_state),
-      NtoN,
+      NtoN)(
       Seq( // TODO: optimize this
         Cat(TRUNK, TRUNK) -> TtoT,
         Cat(TIP, TIP) -> TtoT,
@@ -428,7 +428,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr
     Mux(
       !req_acquire,
       req.param,
-      MuxLookup(req.param, req.param, Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT))
+      MuxLookup(req.param, req.param)(Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT))
     )
 
   od.size := req.size
diff --git a/src/main/scala/huancun/noninclusive/MSHR.scala b/src/main/scala/huancun/noninclusive/MSHR.scala
index c29455b4..5b8d3fae 100644
--- a/src/main/scala/huancun/noninclusive/MSHR.scala
+++ b/src/main/scala/huancun/noninclusive/MSHR.scala
@@ -139,7 +139,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
   val replace_need_release = self_meta.state > replace_clients_perm || self_meta.dirty && isT(self_meta.state)
   val replace_param = MuxLookup(
     Cat(self_meta.state, replace_clients_perm),
-    TtoB,
+    TtoB)(
     Seq(
       Cat(BRANCH, INVALID) -> BtoN,
       Cat(BRANCH, BRANCH) -> BtoB,
@@ -249,7 +249,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
     new_self_meta.dirty := self_meta.hit && self_meta.dirty || req.dirty && isParamFromT(req.param)
     new_self_meta.state := MuxLookup(
       req.param,
-      self_meta.state,
+      self_meta.state)(
       Seq(
         TtoT -> TRUNK,
         TtoB -> TIP,
@@ -345,7 +345,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
             BRANCH
           ),
         ),
-        MuxLookup(self_meta.state, INVALID, Seq(
+        MuxLookup(self_meta.state, INVALID)(Seq(
           INVALID -> BRANCH,
           BRANCH -> BRANCH,
           // if prefetch read && hit && self is Trunk
@@ -1107,7 +1107,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
 
   val probeack_param = MuxLookup( // TODO: optimize this
     Cat(highest_perm, probe_next_state(highest_perm, req.param)),
-    NtoN,
+    NtoN)(
     Seq(
       Cat(TRUNK, TRUNK) -> TtoT,
       Cat(TIP, TIP) -> TtoT,
@@ -1159,7 +1159,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
     Mux(
       !req_acquire,
       req.param,
-      MuxLookup(req.param, req.param, Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT))
+      MuxLookup(req.param, req.param)(Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT))
     )
   od.size := req.size
   od.way := meta_reg.self.way