From a69ea2cf169947ecf8f8df775aa7bd9744be3293 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Sun, 7 Apr 2024 16:52:05 +0800 Subject: [PATCH] configs: correct MaxHartIdBits (#173) Currently, many different lengths of HartId in Xiangshan, making it hard to configure it to scale more than 16 cores since we have set 4bits somewhere. This commit corrects MaxHartIdBits in config and uses MaxHartIDBits where it needs to get this solved. Signed-off-by: Yangyu Chen --- src/main/scala/huancun/Common.scala | 8 ++++---- src/main/scala/huancun/HuanCun.scala | 2 ++ src/main/scala/huancun/prefetch/TPmeta.scala | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main/scala/huancun/Common.scala b/src/main/scala/huancun/Common.scala index d1aa19ca..f6356c54 100644 --- a/src/main/scala/huancun/Common.scala +++ b/src/main/scala/huancun/Common.scala @@ -237,16 +237,16 @@ class PrefetchRecv extends Bundle { val l2_pf_en = Bool() } -class TPmetaReq extends Bundle { +class TPmetaReq(implicit p: Parameters) extends HuanCunBundle { // FIXME: parameterize the hard code - val hartid = UInt(4.W) // max 16 harts + val hartid = UInt(hartIdLen.W) val set = UInt(32.W) val way = UInt(4.W) val wmode = Bool() val rawData = Vec(16, UInt((36-6).W)) } -class TPmetaResp extends Bundle { - val hartid = UInt(4.W) +class TPmetaResp(implicit p: Parameters) extends HuanCunBundle { + val hartid = UInt(hartIdLen.W) val rawData = Vec(16, UInt((36-6).W)) } diff --git a/src/main/scala/huancun/HuanCun.scala b/src/main/scala/huancun/HuanCun.scala index 452098ac..c7d929c7 100644 --- a/src/main/scala/huancun/HuanCun.scala +++ b/src/main/scala/huancun/HuanCun.scala @@ -103,6 +103,8 @@ trait HasHuanCunParameters { lazy val outerSinkBits = edgeOut.bundle.sinkBits + lazy val hartIdLen: Int = log2Up(cacheParams.hartIds.length) + val block_granularity = if (!cacheParams.inclusive && cacheParams.clientCaches.nonEmpty) { cacheParams.clientCaches.head.blockGranularity } else setBits diff --git a/src/main/scala/huancun/prefetch/TPmeta.scala b/src/main/scala/huancun/prefetch/TPmeta.scala index ac2bd9b3..55712c61 100644 --- a/src/main/scala/huancun/prefetch/TPmeta.scala +++ b/src/main/scala/huancun/prefetch/TPmeta.scala @@ -31,7 +31,7 @@ class TPmetaIO(implicit p: Parameters) extends TPmetaBundle { class metaEntry(implicit p:Parameters) extends TPmetaBundle { val rawData = Vec(16, UInt((36-6).W)) - val hartid = UInt(4.W) + val hartid = UInt(hartIdLen.W) // TODO: val compressedData = UInt(512.W) }