From 03567dae98f73baa6b3cd2b658fdc4b46b90aced Mon Sep 17 00:00:00 2001
From: xiaofeibao <1441675923@qq.com>
Date: Sun, 15 Dec 2024 14:27:49 +0800
Subject: [PATCH] timing(vldMgu): fix timing of wbReg's gate enable

---
 src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala b/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
index 149db61b249..40fc0cee578 100644
--- a/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
+++ b/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
@@ -20,7 +20,7 @@ class VldMergeUnit(val params: ExeUnitParams)(implicit p: Parameters) extends XS
   val vdAfterMerge = Wire(UInt(VLEN.W))
 
   val wbFire = !io.writeback.bits.robIdx.needFlush(io.flush) && io.writeback.fire
-  wbReg.bits := Mux(wbFire, io.writeback.bits, wbReg.bits)
+  wbReg.bits := Mux(io.writeback.fire, io.writeback.bits, wbReg.bits)
   wbReg.valid := wbFire
   mgu.io.in.vd := wbReg.bits.data(0)
   // oldVd is contained in data and is already masked with new data