From 97e37a223733159f1551ec3dee630e30dd95387a Mon Sep 17 00:00:00 2001 From: Ziyue Zhang <46214232+Ziyue-Zhang@users.noreply.github.com> Date: Fri, 27 Sep 2024 12:28:29 +0800 Subject: [PATCH] fix(rv64v): not modify fflags when vl is zero (#3658) --- src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala b/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala index ba8ad8e9ec..4a52c28e27 100644 --- a/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala +++ b/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala @@ -413,7 +413,6 @@ class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) val outFFlags = allFFlagsEn.zip(allFFlags).map{ case(en,fflags) => Mux(en, fflags, 0.U(5.W)) }.reduce(_ | _) - io.out.bits.res.fflags.get := outFFlags val cmpResultOldVd = Wire(UInt(cmpResultWidth.W)) @@ -498,6 +497,7 @@ class VFAlu(cfg: FuConfig)(implicit p: Parameters) extends VecPipedFuncUnit(cfg) resultFpMask := Mux(isFclass || isCmp, Fill(16, 1.U(1.W)), Fill(VLEN, 1.U(1.W))) // when dest is mask, the result need to be masked by mgtu io.out.bits.res.data := Mux(notModifyVd, outOldVd, Mux(outVecCtrl.isDstMask, mgtu.io.out.vd, mgu.io.out.vd) & resultFpMask) + io.out.bits.res.fflags.get := Mux(notModifyVd, 0.U(5.W), outFFlags) io.out.bits.ctrl.exceptionVec.get(ExceptionNO.illegalInstr) := mgu.io.out.illegal }