From f4b08c240986b6eb3a1c9e9bc06da4dd8cd75e3d Mon Sep 17 00:00:00 2001
From: Haojin Tang <tanghaojin@outlook.com>
Date: Fri, 10 May 2024 17:47:07 +0800
Subject: [PATCH] Config: set minimal hartid width to 6

This can help users who only build one core but
then manually instantiate more than two cores in
the SoC.
---
 src/main/scala/top/ArgParser.scala | 2 +-
 src/main/scala/top/Configs.scala   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/top/ArgParser.scala b/src/main/scala/top/ArgParser.scala
index d082559bdbe..a9978a035d9 100644
--- a/src/main/scala/top/ArgParser.scala
+++ b/src/main/scala/top/ArgParser.scala
@@ -73,7 +73,7 @@ object ArgParser {
             }
             case MaxHartIdBits =>
               require(log2Up(value.toInt) <= 10, "MaxHartIdBits should not be larger than 10.")
-              log2Up(value.toInt)
+              log2Up(value.toInt) max 6
           }), tail)
         case "--with-dramsim3" :: tail =>
           nextOption(config.alter((site, here, up) => {
diff --git a/src/main/scala/top/Configs.scala b/src/main/scala/top/Configs.scala
index fbb7c91065c..ad38c8440d9 100644
--- a/src/main/scala/top/Configs.scala
+++ b/src/main/scala/top/Configs.scala
@@ -50,7 +50,7 @@ class BaseConfig(n: Int) extends Config((site, here, up) => {
   case ExportDebug => DebugAttachParams(protocols = Set(JTAG))
   case DebugModuleKey => Some(XSDebugModuleParams(site(XLen)))
   case JtagDTMKey => JtagDTMKey
-  case MaxHartIdBits => log2Up(n)
+  case MaxHartIdBits => log2Up(n) max 6
   case EnableJtag => true.B
 })