From 8a5cdb8b8260815d64e7036993e7d6c2466b0901 Mon Sep 17 00:00:00 2001 From: xiaofeibao <1441675923@qq.com> Date: Thu, 19 Sep 2024 16:18:19 +0800 Subject: [PATCH 1/2] power(rob): add clock gate for walkingPtrVec and vstart --- src/main/scala/xiangshan/backend/rob/Rob.scala | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala index 06bc4a90be..54822e2668 100644 --- a/src/main/scala/xiangshan/backend/rob/Rob.scala +++ b/src/main/scala/xiangshan/backend/rob/Rob.scala @@ -554,7 +554,8 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP XSPerfAccumulate("replay_inst_num", io.flushOut.valid && isFlushPipe && deqHasReplayInst) val exceptionHappen = (state === s_idle) && deqPtrEntryValid && (intrEnable || deqHasException) && !lastCycleFlush - io.exception.valid := RegNext(exceptionHappen) + val exceptionHappenReg = GatedValidRegNext(exceptionHappen) + io.exception.valid := exceptionHappenReg io.exception.bits.pc := RegEnable(debug_deqUop.pc, exceptionHappen) io.exception.bits.gpaddr := io.readGPAMemData io.exception.bits.instr := RegEnable(debug_deqUop.instr, exceptionHappen) @@ -585,10 +586,12 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP */ // T redirect.valid, T+1 use walkPtrVec read robEntries, T+2 start walk, shouldWalkVec used in T+2 val shouldWalkVec = Wire(Vec(CommitWidth,Bool())) - val walkingPtrVec = RegNext(walkPtrVec) + // Maybe we can use walkPtrVec - CommitWidth here to save area + val walkingPtrVec = RegEnable(walkPtrVec, state === s_walk) + val redirectValidReg = RegNext(io.redirect.valid) when(io.redirect.valid){ shouldWalkVec := 0.U.asTypeOf(shouldWalkVec) - }.elsewhen(RegNext(io.redirect.valid)){ + }.elsewhen(redirectValidReg){ shouldWalkVec := 0.U.asTypeOf(shouldWalkVec) }.elsewhen(state === s_walk){ shouldWalkVec := VecInit(walkingPtrVec.map(_ <= lastWalkPtr).zip(donotNeedWalk).map(x => x._1 && !x._2)) @@ -622,8 +625,8 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP val resetVstart = dirty_vs && !io.vstartIsZero - io.csr.vstart.valid := RegNext(Mux(exceptionHappen, exceptionDataRead.bits.vstartEn, resetVstart)) - io.csr.vstart.bits := RegNext(Mux(exceptionHappen, exceptionDataRead.bits.vstart, 0.U)) + io.csr.vstart.valid := GatedValidRegNext(Mux(exceptionHappen, exceptionDataRead.bits.vstartEn, resetVstart)) + io.csr.vstart.bits := Mux(exceptionHappenReg, RegEnable(exceptionDataRead.bits.vstart, exceptionHappen), 0.U) val vxsat = Wire(Valid(Bool())) vxsat.valid := io.commits.isCommit && vxsat.bits @@ -735,7 +738,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP * (2) walk: when walking comes to the end, switch to s_idle */ val state_next = Mux( - io.redirect.valid || RegNext(io.redirect.valid), s_walk, + io.redirect.valid || redirectValidReg, s_walk, Mux( state === s_walk && walkFinished && rab.io.status.walkEnd && vtypeBuffer.io.status.walkEnd, s_idle, state @@ -797,7 +800,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP } when(io.redirect.valid) { donotNeedWalk := Fill(donotNeedWalk.length, true.B).asTypeOf(donotNeedWalk) - }.elsewhen(RegNext(io.redirect.valid)){ + }.elsewhen(redirectValidReg){ donotNeedWalk := (0 until CommitWidth).map(i => (i.U < walkPtrLowBits)) }.otherwise{ donotNeedWalk := 0.U.asTypeOf(donotNeedWalk) @@ -828,7 +831,6 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP deqPtrGroup.zipWithIndex.map { case (deq, i) => deq := deqPtrVec(0) + i.U } val commitReadAddr = Mux(state === s_idle, VecInit(deqPtrVec.map(_.value)), VecInit(walkPtrVec.map(_.value))) - val redirectValidReg = RegNext(io.redirect.valid) val redirectBegin = Reg(UInt(log2Up(RobSize).W)) val redirectEnd = Reg(UInt(log2Up(RobSize).W)) when(io.redirect.valid){ From abf449665feb0584167228e6885e501c69a30871 Mon Sep 17 00:00:00 2001 From: xiaofeibao <1441675923@qq.com> Date: Thu, 19 Sep 2024 16:19:03 +0800 Subject: [PATCH 2/2] timing(IssueQueue): fix timing of ldCancel --- .../backend/issue/EntryBundles.scala | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/src/main/scala/xiangshan/backend/issue/EntryBundles.scala b/src/main/scala/xiangshan/backend/issue/EntryBundles.scala index 7bc328f17f..eff9809cec 100644 --- a/src/main/scala/xiangshan/backend/issue/EntryBundles.scala +++ b/src/main/scala/xiangshan/backend/issue/EntryBundles.scala @@ -420,16 +420,19 @@ object EntryBundles extends HasCircularQueuePtrHelper { } } - val srcLoadDependencyForCancel = Wire(chiselTypeOf(common.srcLoadDependencyNext)) + val srcIsLoadCancel = Wire(chiselTypeOf(common.srcLoadCancelVec)) val srcLoadDependencyOut = Wire(chiselTypeOf(common.srcLoadDependencyNext)) if(params.hasIQWakeUp) { + val wakeupIsLoadCancelVec = hasIQWakeupGet.wakeupLoadDependencyByIQVec.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)) + val srcWakeupIsLoadCancel = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, wakeupIsLoadCancelVec)) + val statusIsLoadCancel = status.srcStatus.map(x => LoadShouldCancel(Some(x.srcLoadDependency), commonIn.ldCancel)) val wakeupSrcLoadDependency = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.wakeupLoadDependencyByIQVec)) val wakeupSrcLoadDependencyNext = hasIQWakeupGet.srcWakeupByIQWithoutCancel.map(x => Mux1H(x, hasIQWakeupGet.shiftedWakeupLoadDependencyByIQVec)) - srcLoadDependencyForCancel.zipWithIndex.foreach { case (ldOut, srcIdx) => - ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, - wakeupSrcLoadDependency(srcIdx), - status.srcStatus(srcIdx).srcLoadDependency) - else status.srcStatus(srcIdx).srcLoadDependency) + srcIsLoadCancel.zipWithIndex.foreach { case (ldCancel, srcIdx) => + ldCancel := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, + srcWakeupIsLoadCancel(srcIdx), + statusIsLoadCancel(srcIdx)) + else statusIsLoadCancel(srcIdx)) } srcLoadDependencyOut.zipWithIndex.foreach { case (ldOut, srcIdx) => ldOut := (if (isComp) Mux(hasIQWakeupGet.srcWakeupByIQWithoutCancel(srcIdx).asUInt.orR, @@ -438,10 +441,10 @@ object EntryBundles extends HasCircularQueuePtrHelper { else common.srcLoadDependencyNext(srcIdx)) } } else { - srcLoadDependencyForCancel := status.srcStatus.map(_.srcLoadDependency) + srcIsLoadCancel := 0.U.asTypeOf(srcIsLoadCancel) srcLoadDependencyOut := common.srcLoadDependencyNext } - commonOut.cancelBypass := srcLoadDependencyForCancel.map(x => LoadShouldCancel(Some(x), commonIn.ldCancel)).reduce(_ | _) + commonOut.cancelBypass := srcIsLoadCancel.reduce(_ || _) commonOut.entry.bits.status.srcStatus.map(_.srcLoadDependency).zipWithIndex.foreach { case (ldOut, srcIdx) => ldOut := srcLoadDependencyOut(srcIdx) }