From 613565c531f3e326b268ea787fdfd333d2897e17 Mon Sep 17 00:00:00 2001 From: sinceforYy <1017657683@qq.com> Date: Mon, 11 Nov 2024 18:42:15 +0800 Subject: [PATCH 1/2] fix(format): fix code format --- .../scala/xiangshan/backend/CtrlBlock.scala | 23 ++++++++----------- .../xiangshan/backend/ctrlblock/MemCtrl.scala | 6 ++--- .../backend/decode/DecodeStage.scala | 2 +- .../xiangshan/backend/issue/Dispatch2Iq.scala | 16 ++++++------- .../xiangshan/backend/rename/Rename.scala | 2 +- 5 files changed, 23 insertions(+), 26 deletions(-) diff --git a/src/main/scala/xiangshan/backend/CtrlBlock.scala b/src/main/scala/xiangshan/backend/CtrlBlock.scala index a1678d4ff3..95150402ba 100644 --- a/src/main/scala/xiangshan/backend/CtrlBlock.scala +++ b/src/main/scala/xiangshan/backend/CtrlBlock.scala @@ -308,12 +308,10 @@ class CtrlBlockImp( io.frontend.toFtq.redirect.bits.cfiUpdate.backendIGPF := RegEnable(s5_trapTargetIGPF, s5_flushFromRobValidAhead) } - for (i <- 0 until DecodeWidth) { - gpaMem.io.fromIFU := io.frontend.fromIfu - gpaMem.io.exceptionReadAddr.valid := rob.io.readGPAMemAddr.valid - gpaMem.io.exceptionReadAddr.bits.ftqPtr := rob.io.readGPAMemAddr.bits.ftqPtr - gpaMem.io.exceptionReadAddr.bits.ftqOffset := rob.io.readGPAMemAddr.bits.ftqOffset - } + gpaMem.io.fromIFU := io.frontend.fromIfu + gpaMem.io.exceptionReadAddr.valid := rob.io.readGPAMemAddr.valid + gpaMem.io.exceptionReadAddr.bits.ftqPtr := rob.io.readGPAMemAddr.bits.ftqPtr + gpaMem.io.exceptionReadAddr.bits.ftqOffset := rob.io.readGPAMemAddr.bits.ftqOffset // vtype commit decode.io.fromCSR := io.fromCSR.toDecode @@ -338,7 +336,6 @@ class CtrlBlockImp( dontTouch(decodeFromFrontendNotAccept) dontTouch(decodeFromFrontendAcceptNum) } - val a = decodeBufNotAccept.drop(2) for (i <- 0 until DecodeWidth) { // decodeBufValid update when(decode.io.redirect || decodeBufValid(0) && decodeBufValid(i) && decode.io.in(i).ready && !VecInit(decodeBufNotAccept.drop(i)).asUInt.orR) { @@ -462,11 +459,11 @@ class CtrlBlockImp( // memory dependency predict // when decode, send fold pc to mdp - private val mdpFlodPcVecVld = Wire(Vec(DecodeWidth, Bool())) - private val mdpFlodPcVec = Wire(Vec(DecodeWidth, UInt(MemPredPCWidth.W))) + private val mdpFoldPcVecVld = Wire(Vec(DecodeWidth, Bool())) + private val mdpFoldPcVec = Wire(Vec(DecodeWidth, UInt(MemPredPCWidth.W))) for (i <- 0 until DecodeWidth) { - mdpFlodPcVecVld(i) := decode.io.out(i).fire || GatedValidRegNext(decode.io.out(i).fire) - mdpFlodPcVec(i) := Mux( + mdpFoldPcVecVld(i) := decode.io.out(i).fire || GatedValidRegNext(decode.io.out(i).fire) + mdpFoldPcVec(i) := Mux( decode.io.out(i).fire, decode.io.in(i).bits.foldpc, rename.io.in(i).bits.foldpc @@ -478,8 +475,8 @@ class CtrlBlockImp( memCtrl.io.csrCtrl := io.csrCtrl // RegNext in memCtrl memCtrl.io.stIn := io.fromMem.stIn // RegNext in memCtrl memCtrl.io.memPredUpdate := redirectGen.io.memPredUpdate // RegNext in memCtrl - memCtrl.io.mdpFoldPcVecVld := mdpFlodPcVecVld - memCtrl.io.mdpFlodPcVec := mdpFlodPcVec + memCtrl.io.mdpFoldPcVecVld := mdpFoldPcVecVld + memCtrl.io.mdpFoldPcVec := mdpFoldPcVec memCtrl.io.dispatchLFSTio <> dispatch.io.lfst rat.io.redirect := s1_s3_redirect.valid diff --git a/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala b/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala index f94e8ef299..7141818f34 100644 --- a/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala +++ b/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala @@ -21,8 +21,8 @@ class MemCtrl(params: BackendParams)(implicit p: Parameters) extends XSModule { for (i <- 0 until RenameWidth) { ssit.io.ren(i) := io.mdpFoldPcVecVld(i) - ssit.io.raddr(i) := io.mdpFlodPcVec(i) - waittable.io.raddr(i) := io.mdpFlodPcVec(i) + ssit.io.raddr(i) := io.mdpFoldPcVec(i) + waittable.io.raddr(i) := io.mdpFoldPcVec(i) } lfst.io.redirect <> RegNext(io.redirect) lfst.io.storeIssue <> RegNext(io.stIn) @@ -39,7 +39,7 @@ class MemCtrlIO(params: BackendParams)(implicit p: Parameters) extends XSBundle val stIn = Vec(params.StaExuCnt, Flipped(ValidIO(new DynInst))) // use storeSetHit, ssid, robIdx val memPredUpdate = Input(new MemPredUpdateReq) val mdpFoldPcVecVld = Input(Vec(DecodeWidth, Bool())) - val mdpFlodPcVec = Input(Vec(DecodeWidth, UInt(MemPredPCWidth.W))) + val mdpFoldPcVec = Input(Vec(DecodeWidth, UInt(MemPredPCWidth.W))) val dispatchLFSTio = Flipped(new DispatchLFSTIO) val waitTable2Rename = Vec(DecodeWidth, Output(Bool())) // loadWaitBit val ssit2Rename = Vec(RenameWidth, Output(new SSITEntry)) // ssit read result diff --git a/src/main/scala/xiangshan/backend/decode/DecodeStage.scala b/src/main/scala/xiangshan/backend/decode/DecodeStage.scala index 77195f6024..5609231565 100644 --- a/src/main/scala/xiangshan/backend/decode/DecodeStage.scala +++ b/src/main/scala/xiangshan/backend/decode/DecodeStage.scala @@ -229,7 +229,7 @@ class DecodeStage(implicit p: Parameters) extends XSModule debug_globalCounter := debug_globalCounter + PopCount(io.out.map(_.fire)) io.stallReason.in.backReason := io.stallReason.out.backReason - io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => + io.stallReason.out.reason.zip(io.stallReason.in.reason).foreach { case (out, in) => out := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, in) diff --git a/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala b/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala index 40f711aa2f..2aee69bd0a 100644 --- a/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala +++ b/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala @@ -136,8 +136,8 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par private val vlReqPsrcVec: IndexedSeq[UInt] = io.in.map(in => in.bits.psrc(numRegSrc - 1)) private val intRenVec: IndexedSeq[Bool] = io.in.flatMap(in => in.bits.psrc.take(numRegSrcInt).map(x => in.valid)) private val intSrcStateVec = Option.when(io.readIntState.isDefined)(Wire(Vec(numIntStateRead, SrcState()))) - private val fpSrcStateVec = Option.when(io.readFpState.isDefined )(Wire(Vec(numFpStateRead, SrcState()))) - private val vfSrcStateVec = Option.when(io.readVfState.isDefined )(Wire(Vec(numVfStateRead, SrcState()))) + private val fpSrcStateVec = Option.when(io.readFpState.isDefined )(Wire(Vec(numFpStateRead, SrcState()))) + private val vfSrcStateVec = Option.when(io.readVfState.isDefined )(Wire(Vec(numVfStateRead, SrcState()))) private val v0SrcStateVec = Option.when(io.readV0State.isDefined )(Wire(Vec(numV0StateRead, SrcState()))) private val vlSrcStateVec = Option.when(io.readVlState.isDefined )(Wire(Vec(numVlStateRead, SrcState()))) private val vlSrcIsZeroVec = Option.when(io.readVlInfo.isDefined )(Wire(Vec(numVlStateRead, Bool()))) @@ -213,13 +213,13 @@ abstract class Dispatch2IqImp(override val wrapper: Dispatch2Iq)(implicit p: Par for (i <- 0 until numIn) { for (j <- 0 until numRegSrcVf) { - vecAllSrcStateVec.get(i * numRegSrc + j) := vfSrcStateVec.get(i * numRegSrcVf + j); - vecAllSrcLoadDependency.get(i * numRegSrc + j) := vfSrcLoadDependency.get(i * numRegSrcVf + j); + vecAllSrcStateVec.get(i * numRegSrc + j) := vfSrcStateVec.get(i * numRegSrcVf + j) + vecAllSrcLoadDependency.get(i * numRegSrc + j) := vfSrcLoadDependency.get(i * numRegSrcVf + j) } - vecAllSrcStateVec.get(i * numRegSrc + numRegSrc - 2) := v0SrcStateVec.get(i); - vecAllSrcStateVec.get(i * numRegSrc + numRegSrc - 1) := vlSrcStateVec.get(i); - vecAllSrcLoadDependency.get(i * numRegSrc + numRegSrc - 2) := v0SrcLoadDependency.get(i); - vecAllSrcLoadDependency.get(i * numRegSrc + numRegSrc - 1) := vlSrcLoadDependency.get(i); + vecAllSrcStateVec.get(i * numRegSrc + numRegSrc - 2) := v0SrcStateVec.get(i) + vecAllSrcStateVec.get(i * numRegSrc + numRegSrc - 1) := vlSrcStateVec.get(i) + vecAllSrcLoadDependency.get(i * numRegSrc + numRegSrc - 2) := v0SrcLoadDependency.get(i) + vecAllSrcLoadDependency.get(i * numRegSrc + numRegSrc - 1) := vlSrcLoadDependency.get(i) // same as eliminate the old vd dependency in issue queue when wake up by wakeup val isDependOldVd = io.in(i).bits.vpu.isDependOldVd diff --git a/src/main/scala/xiangshan/backend/rename/Rename.scala b/src/main/scala/xiangshan/backend/rename/Rename.scala index 9e99997903..47710671c8 100644 --- a/src/main/scala/xiangshan/backend/rename/Rename.scala +++ b/src/main/scala/xiangshan/backend/rename/Rename.scala @@ -682,7 +682,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe multiFlStall -> TopDownCounters.MultiFlStall.id.U, ) )) - io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => + io.stallReason.out.reason.zip(io.stallReason.in.reason).foreach { case (out, in) => out := Mux(io.stallReason.in.backReason.valid, io.stallReason.in.backReason.bits, in) } From ae673f63d39a6e9b240e354281277d09a5eb497a Mon Sep 17 00:00:00 2001 From: sinceforYy <1017657683@qq.com> Date: Mon, 11 Nov 2024 18:43:49 +0800 Subject: [PATCH 2/2] fix(perf): fix dq perf and add vec dq perf --- .../scala/xiangshan/backend/dispatch/Dispatch.scala | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala index 573b0f66d5..0294ec5ba7 100644 --- a/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala +++ b/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala @@ -433,11 +433,12 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents { XSError(enqFireCnt > renameFireCnt, "enqFireCnt should not be greater than renameFireCnt\n") val stall_rob = hasValidInstr && !io.enqRob.canAccept && dqCanAccept - val stall_int_dq = hasValidInstr && io.enqRob.canAccept && !toIntDqCanAccept && io.toVecDq.canAccept && io.toLsDq.canAccept - val stall_int_dq0 = hasValidInstr && io.enqRob.canAccept && !io.toIntDq0.canAccept && io.toVecDq.canAccept && io.toLsDq.canAccept - val stall_int_dq1 = hasValidInstr && io.enqRob.canAccept && !io.toIntDq1.canAccept && io.toVecDq.canAccept && io.toLsDq.canAccept - val stall_fp_dq = hasValidInstr && io.enqRob.canAccept && toIntDqCanAccept && !io.toVecDq.canAccept && io.toLsDq.canAccept - val stall_ls_dq = hasValidInstr && io.enqRob.canAccept && toIntDqCanAccept && io.toVecDq.canAccept && !io.toLsDq.canAccept + val stall_int_dq = hasValidInstr && io.enqRob.canAccept && !toIntDqCanAccept && io.toFpDq.canAccept && io.toVecDq.canAccept && io.toLsDq.canAccept + val stall_int_dq0 = hasValidInstr && io.enqRob.canAccept && !io.toIntDq0.canAccept && io.toFpDq.canAccept && io.toVecDq.canAccept && io.toLsDq.canAccept + val stall_int_dq1 = hasValidInstr && io.enqRob.canAccept && !io.toIntDq1.canAccept && io.toFpDq.canAccept && io.toVecDq.canAccept && io.toLsDq.canAccept + val stall_fp_dq = hasValidInstr && io.enqRob.canAccept && toIntDqCanAccept && !io.toFpDq.canAccept && io.toVecDq.canAccept && io.toLsDq.canAccept + val stall_vec_dq = hasValidInstr && io.enqRob.canAccept && toIntDqCanAccept && io.toFpDq.canAccept && !io.toVecDq.canAccept && io.toLsDq.canAccept + val stall_ls_dq = hasValidInstr && io.enqRob.canAccept && toIntDqCanAccept && io.toFpDq.canAccept && io.toVecDq.canAccept && !io.toLsDq.canAccept XSPerfAccumulate("in_valid_count", PopCount(io.fromRename.map(_.valid))) XSPerfAccumulate("in_fire_count", PopCount(io.fromRename.map(_.fire))) @@ -448,6 +449,7 @@ class Dispatch(implicit p: Parameters) extends XSModule with HasPerfEvents { XSPerfAccumulate("stall_cycle_int_dq0", stall_int_dq0) XSPerfAccumulate("stall_cycle_int_dq1", stall_int_dq1) XSPerfAccumulate("stall_cycle_fp_dq", stall_fp_dq) + XSPerfAccumulate("stall_cycle_vec_dq", stall_vec_dq) XSPerfAccumulate("stall_cycle_ls_dq", stall_ls_dq) val notIssue = !io.debugTopDown.fromRob.robHeadLsIssue