diff --git a/src/main/scala/xiangshan/XSCore.scala b/src/main/scala/xiangshan/XSCore.scala
index b52ba4bcf52..2ea0fb3e64b 100644
--- a/src/main/scala/xiangshan/XSCore.scala
+++ b/src/main/scala/xiangshan/XSCore.scala
@@ -148,6 +148,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   backend.io.mem.writebackHyuSta <> memBlock.io.mem_to_ooo.writebackHyuSta
   backend.io.mem.writebackStd <> memBlock.io.mem_to_ooo.writebackStd
   backend.io.mem.writebackVldu <> memBlock.io.mem_to_ooo.writebackVldu
+  backend.io.mem.robLsqIO.update := memBlock.io.mem_to_ooo.lsqio.update
   backend.io.mem.robLsqIO.mmio := memBlock.io.mem_to_ooo.lsqio.mmio
   backend.io.mem.robLsqIO.uop := memBlock.io.mem_to_ooo.lsqio.uop
 
@@ -215,6 +216,7 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   memBlock.io.ooo_to_mem.lsqio.commit           := backend.io.mem.robLsqIO.commit
   memBlock.io.ooo_to_mem.lsqio.pendingPtr       := backend.io.mem.robLsqIO.pendingPtr
   memBlock.io.ooo_to_mem.lsqio.pendingPtrNext   := backend.io.mem.robLsqIO.pendingPtrNext
+  memBlock.io.ooo_to_mem.lsqio.pendingIntr      := backend.io.mem.robLsqIO.pendingIntr
   memBlock.io.ooo_to_mem.isStoreException       := backend.io.mem.isStoreException
   memBlock.io.ooo_to_mem.isVlsException         := backend.io.mem.isVlsException
 
diff --git a/src/main/scala/xiangshan/backend/MemBlock.scala b/src/main/scala/xiangshan/backend/MemBlock.scala
index 0dde7f92c88..82fc04166de 100644
--- a/src/main/scala/xiangshan/backend/MemBlock.scala
+++ b/src/main/scala/xiangshan/backend/MemBlock.scala
@@ -96,6 +96,7 @@ class ooo_to_mem(implicit p: Parameters) extends MemBlockBundle {
     val commit = Input(Bool())
     val pendingPtr = Input(new RobPtr)
     val pendingPtrNext = Input(new RobPtr)
+    val pendingIntr = Input(Bool())
   }
 
   val isStoreException = Input(Bool())
@@ -142,6 +143,7 @@ class mem_to_ooo(implicit p: Parameters) extends MemBlockBundle {
     val vl = Output(UInt((log2Up(VLEN) + 1).W))
     val gpaddr = Output(UInt(XLEN.W))
     val isForVSnonLeafPTE = Output(Bool())
+    val update = Output(Vec(LoadPipelineWidth, Bool()))
     val mmio = Output(Vec(LoadPipelineWidth, Bool()))
     val uop = Output(Vec(LoadPipelineWidth, new DynInst))
     val lqCanAccept = Output(Bool())
@@ -1081,6 +1083,7 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   loadMisalignBuffer.io.rob.commit              := io.ooo_to_mem.lsqio.commit
   loadMisalignBuffer.io.rob.pendingPtr          := io.ooo_to_mem.lsqio.pendingPtr
   loadMisalignBuffer.io.rob.pendingPtrNext      := io.ooo_to_mem.lsqio.pendingPtrNext
+  loadMisalignBuffer.io.rob.pendingIntr         := io.ooo_to_mem.lsqio.pendingIntr
 
   lsq.io.flushFrmMaBuf                          := loadMisalignBuffer.io.flushLdExpBuff
 
@@ -1094,6 +1097,7 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   storeMisalignBuffer.io.rob.commit             := io.ooo_to_mem.lsqio.commit
   storeMisalignBuffer.io.rob.pendingPtr         := io.ooo_to_mem.lsqio.pendingPtr
   storeMisalignBuffer.io.rob.pendingPtrNext     := io.ooo_to_mem.lsqio.pendingPtrNext
+  storeMisalignBuffer.io.rob.pendingIntr        := io.ooo_to_mem.lsqio.pendingIntr
 
   lsq.io.maControl                              <> storeMisalignBuffer.io.sqControl
 
@@ -1272,6 +1276,7 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   lsq.io.uncacheOutstanding := io.ooo_to_mem.csrCtrl.uncache_write_outstanding_enable
 
   // Lsq
+  io.mem_to_ooo.lsqio.update     := lsq.io.rob.update
   io.mem_to_ooo.lsqio.mmio       := lsq.io.rob.mmio
   io.mem_to_ooo.lsqio.uop        := lsq.io.rob.uop
   lsq.io.rob.lcommit             := io.ooo_to_mem.lsqio.lcommit
@@ -1283,6 +1288,7 @@ class MemBlockInlinedImp(outer: MemBlockInlined) extends LazyModuleImp(outer)
   lsq.io.rob.commit              := io.ooo_to_mem.lsqio.commit
   lsq.io.rob.pendingPtr          := io.ooo_to_mem.lsqio.pendingPtr
   lsq.io.rob.pendingPtrNext      := io.ooo_to_mem.lsqio.pendingPtrNext
+  lsq.io.rob.pendingIntr         := io.ooo_to_mem.lsqio.pendingIntr
 
   //  lsq.io.rob            <> io.lsqio.rob
   lsq.io.enq            <> io.ooo_to_mem.enqLsq
diff --git a/src/main/scala/xiangshan/backend/rob/Rob.scala b/src/main/scala/xiangshan/backend/rob/Rob.scala
index 510285e55b9..b238d8be9ef 100644
--- a/src/main/scala/xiangshan/backend/rob/Rob.scala
+++ b/src/main/scala/xiangshan/backend/rob/Rob.scala
@@ -539,8 +539,12 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   XSInfo(writebackNum =/= 0.U, "writebacked %d insts\n", writebackNum)
 
   for (i <- 0 until LoadPipelineWidth) {
-    when(RegNext(io.lsq.mmio(i))) {
-      robEntries(RegEnable(io.lsq.uop(i).robIdx, io.lsq.mmio(i)).value).mmio := true.B
+    when(RegNext(io.lsq.update(i))) {
+      when(RegEnable(io.lsq.mmio(i), io.lsq.update(i))) {
+        robEntries(RegEnable(io.lsq.uop(i).robIdx, io.lsq.update(i)).value).mmio := true.B
+      }.otherwise {
+        robEntries(RegEnable(io.lsq.uop(i).robIdx, io.lsq.update(i)).value).interrupt_safe := true.B
+      }
     }
   }
 
@@ -808,6 +812,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
   io.lsq.commit := RegNext(io.commits.isCommit && io.commits.commitValid(0))
   io.lsq.pendingPtr := RegNext(deqPtr)
   io.lsq.pendingPtrNext := RegNext(deqPtrVec_next.head)
+  io.lsq.pendingIntr := RegNext(intrEnable)
 
   /**
    * state changes
diff --git a/src/main/scala/xiangshan/backend/rob/RobBundles.scala b/src/main/scala/xiangshan/backend/rob/RobBundles.scala
index ac1dc82b76d..fbbc5a64a7e 100644
--- a/src/main/scala/xiangshan/backend/rob/RobBundles.scala
+++ b/src/main/scala/xiangshan/backend/rob/RobBundles.scala
@@ -239,7 +239,9 @@ class RobLsqIO(implicit p: Parameters) extends XSBundle {
   val commit = Output(Bool())
   val pendingPtr = Output(new RobPtr)
   val pendingPtrNext = Output(new RobPtr)
+  val pendingIntr = Output(Bool())
 
+  val update = Input(Vec(LoadPipelineWidth, Bool()))
   val mmio = Input(Vec(LoadPipelineWidth, Bool()))
   // Todo: what's this?
   val uop = Input(Vec(LoadPipelineWidth, new DynInst))
diff --git a/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala b/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
index ea0ecbea4f8..c4198915621 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
@@ -130,6 +130,7 @@ class LoadMisalignBuffer(implicit p: Parameters) extends XSModule
     val flushLdExpBuff  = Output(Bool())
   })
 
+  io.rob.update := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool()))
   io.rob.mmio := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool()))
   io.rob.uop  := 0.U.asTypeOf(Vec(LoadPipelineWidth, new DynInst))
 
@@ -569,7 +570,7 @@ class LoadMisalignBuffer(implicit p: Parameters) extends XSModule
   io.writeBack.bits.debug.paddr := req.paddr
   io.writeBack.bits.debug.vaddr := req.vaddr
 
-  val flush = req_valid && req.uop.robIdx.needFlush(io.redirect)
+  val flush = req_valid && req.uop.robIdx.needFlush(io.redirect) || io.rob.pendingIntr
 
   when (flush && (bufferState =/= s_idle)) {
     bufferState := s_idle
diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
index f4585d78c6e..1c71f60d98c 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
@@ -102,6 +102,7 @@ class StoreMisalignBuffer(implicit p: Parameters) extends XSModule
     val sqControl       = new StoreMaBufToSqControlIO
   })
 
+  io.rob.update := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool()))
   io.rob.mmio := 0.U.asTypeOf(Vec(LoadPipelineWidth, Bool()))
   io.rob.uop  := 0.U.asTypeOf(Vec(LoadPipelineWidth, new DynInst))
 
@@ -584,7 +585,7 @@ class StoreMisalignBuffer(implicit p: Parameters) extends XSModule
 
   io.sqControl.control.removeSq := req_valid && (bufferState === s_wait) && !(globalMMIO || globalException) && (io.rob.scommit =/= 0.U)
 
-  val flush = req_valid && req.uop.robIdx.needFlush(io.redirect)
+  val flush = req_valid && req.uop.robIdx.needFlush(io.redirect) || io.rob.pendingIntr
 
   when (flush && (bufferState =/= s_idle)) {
     bufferState := s_idle
diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
index f5437650dea..bb30fee3185 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
@@ -306,6 +306,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   io.maControl.storeInfo.completeSbTrans := doMisalignSt && dataBuffer.io.enq(0).fire
 
   // store can be committed by ROB
+  io.rob.update := DontCare
   io.rob.mmio := DontCare
   io.rob.uop := DontCare
 
@@ -789,6 +790,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   val uncacheUop = Reg(new DynInst)
   val uncacheVAddr = Reg(UInt(VAddrBits.W))
   val cboFlushedSb = RegInit(false.B)
+  val pendingIntr = RegNext(io.rob.pendingIntr)
   val cmoOpCode = uncacheUop.fuOpType(1, 0)
   switch(uncacheState) {
     is(s_idle) {
@@ -894,7 +896,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   io.mmioStout.bits.uop := uncacheUop
   io.mmioStout.bits.uop.exceptionVec := ExceptionNO.selectByFu(uncacheUop.exceptionVec, StaCfg)
   io.mmioStout.bits.uop.sqIdx := deqPtrExt(0)
-  io.mmioStout.bits.uop.flushPipe := deqCanDoCbo // flush Pipeline to keep order in CMO
+  io.mmioStout.bits.uop.flushPipe := deqCanDoCbo || pendingIntr // flush Pipeline to keep order in CMO
   io.mmioStout.bits.data := shiftDataToLow(paddrModule.io.rdata(0), dataModule.io.rdata(0).data) // dataModule.io.rdata.read(deqPtr)
   io.mmioStout.bits.isFromLoadUnit := DontCare
   io.mmioStout.bits.debug.isMMIO := true.B
diff --git a/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala b/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
index ca583a41de1..77a3b0f4953 100644
--- a/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
@@ -94,10 +94,12 @@ class UncacheBufferEntry(entryIndex: Int)(implicit p: Parameters) extends XSModu
     * (5) ROB commits the instruction: same as normal instructions
     */
 
+  io.rob.update := DontCare
   io.rob.mmio := DontCare
   io.rob.uop := DontCare
   val pendingld = GatedValidRegNext(io.rob.pendingUncacheld)
   val pendingPtr = GatedRegNext(io.rob.pendingPtr)
+  val pendingIntr = GatedRegNext(io.rob.pendingIntr)
 
   switch (uncacheState) {
     is (s_idle) {
@@ -172,6 +174,7 @@ class UncacheBufferEntry(entryIndex: Int)(implicit p: Parameters) extends XSModu
   io.ldout.valid              := (uncacheState === s_wait)
   io.ldout.bits               := DontCare
   io.ldout.bits.uop           := selUop
+  io.ldout.bits.uop.flushPipe := pendingIntr
   io.ldout.bits.uop.lqIdx     := req.uop.lqIdx
   io.ldout.bits.uop.exceptionVec(loadAccessFault) := nderr
   io.ldout.bits.data          := rdataPartialLoad
@@ -373,7 +376,8 @@ class UncacheBuffer(implicit p: Parameters) extends XSModule
   io.ld_raw_data(UncacheWBPort)      := RegEnable(ld_raw_data, ldout.fire)
 
   for (i <- 0 until LoadPipelineWidth) {
-    io.rob.mmio(i) := RegNext(s1_valid(i) && s1_req(i).mmio)
+    io.rob.update(i) := RegNext(s1_valid(i))
+    io.rob.mmio(i) := RegEnable(s1_req(i).mmio, s1_valid(i))
     io.rob.uop(i) := RegEnable(s1_req(i).uop, s1_valid(i))
   }