From e5f67d9f5e83749d98ab2582f22fc31b7f4bdd15 Mon Sep 17 00:00:00 2001 From: klin02 Date: Tue, 12 Mar 2024 13:50:12 +0800 Subject: [PATCH] Add built-in Perf for difftest We will dump built-in Perf for difftest at the end of simulation. These printfs can be controled by difftest_perfCtrl_dump. For emu, we call Emulator::trigger_stat_dump. For simv, we raise difftest_perfCtrl_dump when simv_result is not zero. We add system task decl $fwrite to Palladium scripts, otherwise it will be ignored automatically. --- .github/workflows/main.yml | 8 ++++---- scripts/palladium/argConfigs.qel | 1 + src/main/scala/Batch.scala | 14 +++++++++++--- src/main/scala/Gateway.scala | 2 ++ src/main/scala/common/LogPerfControl.scala | 12 ++++++++++++ src/test/vsrc/vcs/top.v | 7 ++++++- 6 files changed, 36 insertions(+), 8 deletions(-) diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 3148ebdeb..9cc2a96de 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -304,7 +304,7 @@ jobs: cd $GITHUB_WORKSPACE/../xs-env/NutShell source ./env.sh make clean - make simv MILL_ARGS="--difftest-config Z" DIFFTEST_PERFCNT=1 VCS=verilator -j2 + make simv MILL_ARGS="--difftest-config ZP" DIFFTEST_PERFCNT=1 VCS=verilator -j2 ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000 ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so @@ -315,7 +315,7 @@ jobs: cd $GITHUB_WORKSPACE/../xs-env/NutShell source ./env.sh make clean - make simv MILL_ARGS="--difftest-config BI" DIFFTEST_PERFCNT=1 VCS=verilator -j2 + make simv MILL_ARGS="--difftest-config BIP" DIFFTEST_PERFCNT=1 VCS=verilator -j2 ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000 ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so @@ -326,7 +326,7 @@ jobs: cd $GITHUB_WORKSPACE/../xs-env/NutShell source ./env.sh make clean - make simv MILL_ARGS="--difftest-config ZESRB" DIFFTEST_PERFCNT=1 VCS=verilator -j2 + make simv MILL_ARGS="--difftest-config ZESRBP" DIFFTEST_PERFCNT=1 VCS=verilator -j2 ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000 ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so @@ -337,7 +337,7 @@ jobs: cd $GITHUB_WORKSPACE/../xs-env/NutShell source ./env.sh make clean - make simv MILL_ARGS="--difftest-config ESRBIN" DIFFTEST_PERFCNT=1 VCS=verilator -j2 + make simv MILL_ARGS="--difftest-config ESRBINP" DIFFTEST_PERFCNT=1 VCS=verilator -j2 ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000 ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so diff --git a/scripts/palladium/argConfigs.qel b/scripts/palladium/argConfigs.qel index d4e70dac0..6ef0dd6c5 100644 --- a/scripts/palladium/argConfigs.qel +++ b/scripts/palladium/argConfigs.qel @@ -2,3 +2,4 @@ * $value$plusargs TB_IMPORT * $finish TB_IMPORT * $random TB_IMPORT +* $fwrite GFIFO diff --git a/src/main/scala/Batch.scala b/src/main/scala/Batch.scala index 57b0b0463..804701c9b 100644 --- a/src/main/scala/Batch.scala +++ b/src/main/scala/Batch.scala @@ -19,6 +19,7 @@ import chisel3._ import chisel3.util._ import difftest._ import difftest.gateway.GatewayConfig +import difftest.common.DifftestPerf class BatchIO(dataType: UInt, infoType: UInt) extends Bundle { val data = dataType @@ -131,9 +132,16 @@ class BatchEndpoint(template: Seq[DifftestBundle], bundles: Seq[DifftestBundle], val state_info_len = RegInit(0.U(MaxInfoByteWidth.W)) val state_step_cnt = RegInit(0.U(log2Ceil(config.batchSize + 1).W)) - val exceed = (state_data_len +& step_data_len > MaxDataByteLen.U) | - (state_info_len +& step_info_len + (infoWidth / 8).U > MaxInfoByteLen.U) - val should_tick = delayed_enable && (exceed || state_step_cnt === config.batchSize.U) + val data_exceed = state_data_len +& step_data_len > MaxDataByteLen.U + val info_exceed = state_info_len +& step_info_len + (infoWidth / 8).U > MaxInfoByteLen.U + val step_exceed = state_step_cnt === config.batchSize.U + if (config.hasBuiltInPerf) { + DifftestPerf("BatchExceed_data", data_exceed.asUInt) + DifftestPerf("BatchExceed_info", info_exceed.asUInt) + DifftestPerf("BatchExceed_step", step_exceed.asUInt) + } + + val should_tick = delayed_enable && (data_exceed | info_exceed | step_exceed) when(delayed_enable) { when(should_tick) { state_data := step_data diff --git a/src/main/scala/Gateway.scala b/src/main/scala/Gateway.scala index 341237dd2..b7832373b 100644 --- a/src/main/scala/Gateway.scala +++ b/src/main/scala/Gateway.scala @@ -36,6 +36,7 @@ case class GatewayConfig( batchSize: Int = 32, hasInternalStep: Boolean = false, isNonBlock: Boolean = false, + hasBuiltInPerf: Boolean = false, ) { def dutZoneSize: Int = if (hasDutZone) 2 else 1 def dutZoneWidth: Int = log2Ceil(dutZoneSize) @@ -105,6 +106,7 @@ object Gateway { case 'B' => config = config.copy(isBatch = true) case 'I' => config = config.copy(hasInternalStep = true) case 'N' => config = config.copy(isNonBlock = true) + case 'P' => config = config.copy(hasBuiltInPerf = true) case x => println(s"Unknown Gateway Config $x") } config.check() diff --git a/src/main/scala/common/LogPerfControl.scala b/src/main/scala/common/LogPerfControl.scala index c39431029..bffc78b4b 100644 --- a/src/main/scala/common/LogPerfControl.scala +++ b/src/main/scala/common/LogPerfControl.scala @@ -61,3 +61,15 @@ object LogPerfControl { def apply(): LogPerfControl = instances.find(_.isVisible).getOrElse(instantiate()) } + +object DifftestPerf { + def apply(perfName: String, perfCnt: UInt) = { + val helper = LogPerfControl.apply() + val counter = RegInit(0.U(64.W)) + val next_counter = WireInit(counter + perfCnt) + counter := Mux(helper.clean, 0.U, next_counter) + when(helper.dump) { + printf(p"[DIFFTEST_PERF][time=${helper.timer}] $perfName, $next_counter\n") + } + } +} diff --git a/src/test/vsrc/vcs/top.v b/src/test/vsrc/vcs/top.v index 510405d96..9dae5db99 100644 --- a/src/test/vsrc/vcs/top.v +++ b/src/test/vsrc/vcs/top.v @@ -213,7 +213,6 @@ SimTop sim( assign difftest_logCtrl_level = 0; assign difftest_perfCtrl_clean = 0; -assign difftest_perfCtrl_dump = 0; assign difftest_uart_in_ch = 8'hff; always @(posedge clock) begin @@ -244,6 +243,12 @@ assign workload_switch = simv_result == `SIMV_DONE; `endif // ENABLE_WORKLOAD_SWITCH `endif // TB_NO_DPIC +`ifndef TB_NO_DPIC +assign difftest_perfCtrl_dump = simv_result != 0; +`else +assign difftest_perfCtrl_dump = 0; +`endif // TB_NO_DPIC + reg [63:0] n_cycles; always @(posedge clock) begin if (reset) begin