diff --git a/src/main/scala/Gateway.scala b/src/main/scala/Gateway.scala
index 15ae2a9cf..481099e5d 100644
--- a/src/main/scala/Gateway.scala
+++ b/src/main/scala/Gateway.scala
@@ -53,7 +53,7 @@ case class GatewayConfig(
   def dutBufLen: Int = if (isBatch) batchSize else 1
   def maxStep: Int = if (isBatch) batchSize else 1
   def stepWidth: Int = log2Ceil(maxStep + 1)
-  def batchArgByteLen: (Int, Int) = if (isNonBlock) (3600, 400) else (7200, 800)
+  def batchArgByteLen: (Int, Int) = if (isNonBlock || isFPGA) (3600, 400) else (7200, 800)
   def hasDeferredResult: Boolean = isNonBlock || hasInternalStep
   def needTraceInfo: Boolean = hasReplay
   def needEndpoint: Boolean =
@@ -266,6 +266,17 @@ object GatewaySink {
       case "dpic" => DPIC.batch(template, control, io, config)
       case _      => DPIC.batch(template, control, io, config) // Default: DPI-C
     }
+    val out = Option.when(config.isFPGA) {
+      IO(new Bundle {
+        val batch = Output(chiselTypeOf(io))
+        val enable = Output(Bool())
+      })
+    }
+    if (config.isFPGA) {
+      out.get.batch := io
+      out.get.enable := control.enable
+      dontTouch(out.get)
+    }
   }
 
   def collect(config: GatewayConfig): GatewayResult = {