diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml
index 4d4ce179b..f217c7eec 100644
--- a/.github/workflows/nightly.yml
+++ b/.github/workflows/nightly.yml
@@ -1,4 +1,4 @@
-name: CI
+name: Nightly Regression
 
 on:
   schedule:
@@ -65,3 +65,39 @@ jobs:
             make emu XFUZZ=1 REF=$SPIKE_HOME/difftest/build/riscv64-spike-so LLVM_COVER=1 -j2
             ./build/fuzzer -v -- $CORPUS/I-add-01.bin
             ./build/fuzzer -f --max-runs 100 --corpus-input $CORPUS -- --max-cycles 10000 | grep max_runs
+
+  test-difftest-xiangshan:
+    strategy:
+      matrix:
+        os: [ubuntu-20.04, ubuntu-22.04, ubuntu-24.04]
+    runs-on: ${{ matrix.os }}
+    steps:
+      - uses: actions/checkout@v4
+
+      - name: Prepare environment
+        run: |
+          cd $GITHUB_WORKSPACE/..
+          wget https://github.com/OpenXiangShan/xs-env/raw/refs/heads/master/install-verilator.sh
+          wget https://github.com/OpenXiangShan/xs-env/raw/refs/heads/master/setup-tools.sh
+          sudo bash setup-tools.sh
+
+      - name: Prepare XiangShan
+        run: |
+          cd $GITHUB_WORKSPACE/..
+          git clone --depth 1 https://github.com/OpenXiangShan/XiangShan.git
+          cd XiangShan && make init && rm -rf difftest && cp -r $GITHUB_WORKSPACE .
+          echo "NOOP_HOME=$(pwd)" >> $GITHUB_ENV
+
+      - name: Chisel Elaboration
+        run: |
+          make -C $NOOP_HOME sim-verilog CHISEL_TARGET=chirrtl JVM_XMX=10G
+
+      - name: Build libdifftest.so
+        run: |
+          make -C $NOOP_HOME/difftest difftest-so
+
+      - name: Release libdifftest.so to artifacts
+        uses: actions/upload-artifact@v4
+        with:
+          name: libdifftest-${{ matrix.os }}-xiangshan.so
+          path: $NOOP_HOME/build/libdifftest.so
diff --git a/libso.mk b/libso.mk
index 332a75b87..c80ee0200 100644
--- a/libso.mk
+++ b/libso.mk
@@ -10,10 +10,26 @@ ifeq ($(WITH_DRAMSIM3),1)
 LD_LIB  	 = -L $(DRAMSIM3_HOME)/ -ldramsim3 -Wl,-rpath-link=$(DRAMSIM3_HOME)/libdramsim3.so
 endif
 
+# Include headers that are implicitly included by RTL simulators
+# Priority: (1) VCS, (2) Verilator
+ifneq ($(VCS_HOME),)
+LIB_CXXFLAGS += -I$(VCS_HOME)/include
+else
+VERILATOR_ROOT = $(shell verilator -V 2>/dev/null | awk '/VERILATOR_ROOT/ {print $$3; exit}')
+ifneq ($(VERILATOR_ROOT),)
+LIB_CXXFLAGS += -I$(VERILATOR_ROOT)/include/vltstd
+else
+LIBSO_WARNING_MISSING_HEADERS = 1
+endif
+endif
+
 $(CC_OBJ_DIR):
 	mkdir -p $(CC_OBJ_DIR)
 
 difftest-so: $(CC_OBJ_DIR)
+ifeq ($(LIBSO_WARNING_MISSING_HEADERS),1)
+	@echo "No available RTL simulators. Headers may be missing. Still try to build it."
+endif
 	cd $(CC_OBJ_DIR) 					&& \
 	$(CC) $(LIB_CXXFLAGS) $(LIB_CXXFILES)			&& \
 	$(CC) -o $(LIBDIFFTEST_SO) -m64 -shared *.o $(LD_LIB)