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p06.qsf
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p06.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 18:12:31 May 20, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# p06_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY p06
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:12:31 MAY 20, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name VHDL_FILE mod10.vhd
set_global_assignment -name VHDL_FILE Dek7segBCD.vhd
set_location_assignment PIN_87 -to empty
set_location_assignment PIN_128 -to jed[0]
set_location_assignment PIN_86 -to full
set_location_assignment PIN_88 -to button1
set_location_assignment PIN_89 -to button2
set_location_assignment PIN_90 -to button3
set_location_assignment PIN_121 -to jed[1]
set_location_assignment PIN_125 -to jed[2]
set_location_assignment PIN_129 -to jed[3]
set_location_assignment PIN_132 -to jed[4]
set_location_assignment PIN_124 -to jed[6]
set_location_assignment PIN_126 -to jed[5]
set_location_assignment PIN_127 -to jed[7]
set_location_assignment PIN_133 -to cyfry[0]
set_location_assignment PIN_135 -to cyfry[1]
set_location_assignment PIN_136 -to cyfry[2]
set_location_assignment PIN_137 -to cyfry[3]
set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE lpm_counter0.qip
set_global_assignment -name QIP_FILE lpm_decode0.qip
set_global_assignment -name VHDL_FILE DekHotOne4Bin2.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE simulation/Waveform.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name BDF_FILE p06.bdf
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "C:/Users/user/kod/projekty_quartus/p06_easyfpga/simulation/qsim/" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE lpm_counter2.qip
set_global_assignment -name QIP_FILE lpm_constant0.qip
set_location_assignment PIN_23 -to CLK
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name VHDL_FILE znak_u.vhd
set_global_assignment -name CDF_FILE Chain2.cdf
set_global_assignment -name VHDL_FILE znak_c.vhd
set_global_assignment -name VHDL_FILE znak_d.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top