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rtw8822c.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2018-2019 Realtek Corporation
*/
#include <linux/module.h>
#include "main.h"
#include "coex.h"
#include "fw.h"
#include "tx.h"
#include "rx.h"
#include "phy.h"
#include "rtw8822c.h"
#include "rtw8822c_table.h"
#include "mac.h"
#include "reg.h"
#include "debug.h"
#include "util.h"
#include "bf.h"
#include "efuse.h"
#define IQK_DONE_8822C 0xaa
static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
u8 rx_path, bool is_tx2_path);
static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse,
struct rtw8822c_efuse *map)
{
ether_addr_copy(efuse->addr, map->e.mac_addr);
}
static void rtw8822cu_efuse_parsing(struct rtw_efuse *efuse,
struct rtw8822c_efuse *map)
{
ether_addr_copy(efuse->addr, map->u.mac_addr);
}
static void rtw8822cs_efuse_parsing(struct rtw_efuse *efuse,
struct rtw8822c_efuse *map)
{
ether_addr_copy(efuse->addr, map->s.mac_addr);
}
static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
struct rtw8822c_efuse *map;
int i;
map = (struct rtw8822c_efuse *)log_map;
efuse->rfe_option = map->rfe_option;
efuse->rf_board_option = map->rf_board_option;
efuse->crystal_cap = map->xtal_k & XCAP_MASK;
efuse->channel_plan = map->channel_plan;
efuse->country_code[0] = map->country_code[0];
efuse->country_code[1] = map->country_code[1];
efuse->bt_setting = map->rf_bt_setting;
efuse->regd = map->rf_board_option & 0x7;
efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal;
efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal;
efuse->thermal_meter_k =
(map->path_a_thermal + map->path_b_thermal) >> 1;
efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
for (i = 0; i < 4; i++)
efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
switch (rtw_hci_type(rtwdev)) {
case RTW_HCI_TYPE_PCIE:
rtw8822ce_efuse_parsing(efuse, map);
break;
case RTW_HCI_TYPE_USB:
rtw8822cu_efuse_parsing(efuse, map);
break;
case RTW_HCI_TYPE_SDIO:
rtw8822cs_efuse_parsing(efuse, map);
break;
default:
/* unsupported now */
return -ENOTSUPP;
}
return 0;
}
static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
{
rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
if (pre)
rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
else
rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
}
static void rtw8822c_bb_reset(struct rtw_dev *rtwdev)
{
rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
rtw_write16_clr(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
}
static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
struct rtw_backup_info *backup,
struct rtw_backup_info *backup_rf)
{
u32 path, i;
u32 val;
u32 reg;
u32 rf_addr[DACK_RF_8822C] = {0x8f};
u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
0x1c3c, 0x1c24, 0x1d70, 0x9b4,
0x1a00, 0x1a14, 0x1d58, 0x1c38,
0x1e24, 0x1e28, 0x1860, 0x4160};
for (i = 0; i < DACK_REG_8822C; i++) {
backup[i].len = 4;
backup[i].reg = addrs[i];
backup[i].val = rtw_read32(rtwdev, addrs[i]);
}
for (path = 0; path < DACK_PATH_8822C; path++) {
for (i = 0; i < DACK_RF_8822C; i++) {
reg = rf_addr[i];
val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
backup_rf[path * i + i].reg = reg;
backup_rf[path * i + i].val = val;
}
}
}
static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
struct rtw_backup_info *backup,
struct rtw_backup_info *backup_rf)
{
u32 path, i;
u32 val;
u32 reg;
rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
for (path = 0; path < DACK_PATH_8822C; path++) {
for (i = 0; i < DACK_RF_8822C; i++) {
val = backup_rf[path * i + i].val;
reg = backup_rf[path * i + i].reg;
rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
}
}
}
static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
u32 *min, u32 *max)
{
if (value >= 0x200) {
if (*min >= 0x200) {
if (*min > value)
*min = value;
} else {
*min = value;
}
if (*max >= 0x200) {
if (*max < value)
*max = value;
}
} else {
if (*min < 0x200) {
if (*min > value)
*min = value;
}
if (*max >= 0x200) {
*max = value;
} else {
if (*max < value)
*max = value;
}
}
}
static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
{
if (*v1 >= 0x200 && *v2 >= 0x200) {
if (*v1 > *v2)
swap(*v1, *v2);
} else if (*v1 < 0x200 && *v2 < 0x200) {
if (*v1 > *v2)
swap(*v1, *v2);
} else if (*v1 < 0x200 && *v2 >= 0x200) {
swap(*v1, *v2);
}
}
static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
{
u32 i, j;
for (i = 0; i < DACK_SN_8822C - 1; i++) {
for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
__rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
__rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
}
}
}
static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
{
u32 p, m, t, i;
m = 0;
p = 0;
for (i = 10; i < DACK_SN_8822C - 10; i++) {
if (vec[i] > 0x200)
m = (0x400 - vec[i]) + m;
else
p = vec[i] + p;
}
if (p > m) {
t = p - m;
t = t / (DACK_SN_8822C - 20);
} else {
t = m - p;
t = t / (DACK_SN_8822C - 20);
if (t != 0x0)
t = 0x400 - t;
}
*val = t;
}
static u32 rtw8822c_get_path_write_addr(u8 path)
{
u32 base_addr;
switch (path) {
case RF_PATH_A:
base_addr = 0x1800;
break;
case RF_PATH_B:
base_addr = 0x4100;
break;
default:
WARN_ON(1);
return -1;
}
return base_addr;
}
static u32 rtw8822c_get_path_read_addr(u8 path)
{
u32 base_addr;
switch (path) {
case RF_PATH_A:
base_addr = 0x2800;
break;
case RF_PATH_B:
base_addr = 0x4500;
break;
default:
WARN_ON(1);
return -1;
}
return base_addr;
}
static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
{
bool ret = true;
if ((value >= 0x200 && (0x400 - value) > 0x64) ||
(value < 0x200 && value > 0x64)) {
ret = false;
rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
}
return ret;
}
static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
{
u32 temp;
int i = 0, cnt = 0;
while (i < DACK_SN_8822C && cnt < 10000) {
cnt++;
temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
iv[i] = (temp & 0x3ff000) >> 12;
qv[i] = temp & 0x3ff;
if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
rtw8822c_dac_iq_check(rtwdev, qv[i]))
i++;
}
}
static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
u32 *iv, u32 *qv,
u32 *i_value, u32 *q_value)
{
u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
u32 i_delta, q_delta;
u32 temp;
int i, cnt = 0;
do {
i_min = iv[0];
i_max = iv[0];
q_min = qv[0];
q_max = qv[0];
for (i = 0; i < DACK_SN_8822C; i++) {
rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
}
if (i_max < 0x200 && i_min < 0x200)
i_delta = i_max - i_min;
else if (i_max >= 0x200 && i_min >= 0x200)
i_delta = i_max - i_min;
else
i_delta = i_max + (0x400 - i_min);
if (q_max < 0x200 && q_min < 0x200)
q_delta = q_max - q_min;
else if (q_max >= 0x200 && q_min >= 0x200)
q_delta = q_max - q_min;
else
q_delta = q_max + (0x400 - q_min);
rtw_dbg(rtwdev, RTW_DBG_RFK,
"[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
i_min, i_max, i_delta);
rtw_dbg(rtwdev, RTW_DBG_RFK,
"[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
q_min, q_max, q_delta);
rtw8822c_dac_iq_sort(rtwdev, iv, qv);
if (i_delta > 5 || q_delta > 5) {
temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
iv[0] = (temp & 0x3ff000) >> 12;
qv[0] = temp & 0x3ff;
temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
qv[DACK_SN_8822C - 1] = temp & 0x3ff;
} else {
break;
}
} while (cnt++ < 100);
rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
}
static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
u32 *i_value, u32 *q_value)
{
u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C];
u32 rf_a, rf_b;
rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
}
static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
{
rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
rtw_write32(rtwdev, 0x1b00, 0x00000008);
rtw_write8(rtwdev, 0x1bcc, 0x3f);
rtw_write32(rtwdev, 0x1b00, 0x0000000a);
rtw_write8(rtwdev, 0x1bcc, 0x3f);
rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
}
static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
u8 path, u32 *adc_ic, u32 *adc_qc)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 ic = 0, qc = 0, temp = 0;
u32 base_addr;
u32 path_sel;
int i;
rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
base_addr = rtw8822c_get_path_write_addr(path);
switch (path) {
case RF_PATH_A:
path_sel = 0xa0000;
break;
case RF_PATH_B:
path_sel = 0x80000;
break;
default:
WARN_ON(1);
return;
}
/* ADCK step1 */
rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
if (path == RF_PATH_B)
rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
for (i = 0; i < 10; i++) {
rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
rtw_write32(rtwdev, 0x1c24, 0x00010002);
rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
rtw_dbg(rtwdev, RTW_DBG_RFK,
"[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
/* compensation value */
if (ic != 0x0) {
ic = 0x400 - ic;
*adc_ic = ic;
}
if (qc != 0x0) {
qc = 0x400 - qc;
*adc_qc = qc;
}
temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
rtw_write32(rtwdev, base_addr + 0x68, temp);
dm_info->dack_adck[path] = temp;
rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
base_addr + 0x68, temp);
/* check ADC DC offset */
rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
rtw_dbg(rtwdev, RTW_DBG_RFK,
"[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc);
if (ic >= 0x200)
ic = 0x400 - ic;
if (qc >= 0x200)
qc = 0x400 - qc;
if (ic < 5 && qc < 5)
break;
}
/* ADCK step2 */
rtw_write32(rtwdev, 0x1c3c, 0x00000003);
rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
/* release pull low switch on IQ path */
rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
}
static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 base_addr;
u32 read_addr;
base_addr = rtw8822c_get_path_write_addr(path);
read_addr = rtw8822c_get_path_read_addr(path);
rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
if (path == RF_PATH_A) {
rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
rtw_write32(rtwdev, 0x1c38, 0xffffffff);
}
rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
mdelay(2);
rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
mdelay(2);
rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
mdelay(1);
rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
mdelay(20);
if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
!check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
rtw_err(rtwdev, "failed to wait for dack ready\n");
rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
mdelay(1);
rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
}
static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
u8 path, u32 *ic_out, u32 *qc_out)
{
u32 base_addr;
u32 ic, qc, ic_in, qc_in;
base_addr = rtw8822c_get_path_write_addr(path);
rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
rtw_write32(rtwdev, 0x1b00, 0x00000008);
rtw_write8(rtwdev, 0x1bcc, 0x03f);
rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
rtw_write32(rtwdev, 0x1c3c, 0x00088103);
rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
ic = ic_in;
qc = qc_in;
/* compensation value */
if (ic != 0x0)
ic = 0x400 - ic;
if (qc != 0x0)
qc = 0x400 - qc;
if (ic < 0x300) {
ic = ic * 2 * 6 / 5;
ic = ic + 0x80;
} else {
ic = (0x400 - ic) * 2 * 6 / 5;
ic = 0x7f - ic;
}
if (qc < 0x300) {
qc = qc * 2 * 6 / 5;
qc = qc + 0x80;
} else {
qc = (0x400 - qc) * 2 * 6 / 5;
qc = 0x7f - qc;
}
*ic_out = ic;
*qc_out = qc;
rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
}
static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
u32 adc_ic, u32 adc_qc,
u32 *ic_in, u32 *qc_in,
u32 *i_out, u32 *q_out)
{
u32 base_addr;
u32 read_addr;
u32 ic, qc;
u32 temp;
base_addr = rtw8822c_get_path_write_addr(path);
read_addr = rtw8822c_get_path_read_addr(path);
ic = *ic_in;
qc = *qc_in;
rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
mdelay(2);
rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
mdelay(2);
rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
mdelay(1);
rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
mdelay(20);
if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
!check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
mdelay(1);
rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
/* check DAC DC offset */
temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
rtw_write32(rtwdev, base_addr + 0x68, temp);
rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
if (ic >= 0x10)
ic = ic - 0x10;
else
ic = 0x400 - (0x10 - ic);
if (qc >= 0x10)
qc = qc - 0x10;
else
qc = 0x400 - (0x10 - qc);
*i_out = ic;
*q_out = qc;
if (ic >= 0x200)
ic = 0x400 - ic;
if (qc >= 0x200)
qc = 0x400 - qc;
*ic_in = ic;
*qc_in = qc;
rtw_dbg(rtwdev, RTW_DBG_RFK,
"[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
}
static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
{
u32 base_addr = rtw8822c_get_path_write_addr(path);
rtw_write32(rtwdev, base_addr + 0x68, 0x0);
rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
}
static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
u8 path, u8 vec, u32 w_addr, u32 r_addr)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u16 val;
u32 i;
if (WARN_ON(vec >= 2))
return;
for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
dm_info->dack_msbk[path][vec][i] = val;
}
}
static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
{
u32 w_off = 0x1c;
u32 r_off = 0x2c;
u32 w_addr, r_addr;
if (WARN_ON(path >= 2))
return;
/* backup I vector */
w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
/* backup Q vector */
w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
}
static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 val;
val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
dm_info->dack_dck[RF_PATH_A][0][0] = val;
val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
dm_info->dack_dck[RF_PATH_A][0][1] = val;
val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
dm_info->dack_dck[RF_PATH_A][1][0] = val;
val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
dm_info->dack_dck[RF_PATH_A][1][1] = val;
val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
dm_info->dack_dck[RF_PATH_B][0][0] = val;
val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
dm_info->dack_dck[RF_PATH_B][1][0] = val;
val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
dm_info->dack_dck[RF_PATH_B][0][1] = val;
val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
dm_info->dack_dck[RF_PATH_B][1][1] = val;
}
static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
{
u32 temp[3];
temp[0] = rtw_read32(rtwdev, 0x1860);
temp[1] = rtw_read32(rtwdev, 0x4160);
temp[2] = rtw_read32(rtwdev, 0x9b4);
/* set clock */
rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
/* backup path-A I/Q */
rtw_write32_clr(rtwdev, 0x1830, BIT(30));
rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
/* backup path-B I/Q */
rtw_write32_clr(rtwdev, 0x4130, BIT(30));
rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
rtw8822c_dac_cal_backup_dck(rtwdev);
rtw_write32_set(rtwdev, 0x1830, BIT(30));
rtw_write32_set(rtwdev, 0x4130, BIT(30));
rtw_write32(rtwdev, 0x1860, temp[0]);
rtw_write32(rtwdev, 0x4160, temp[1]);
rtw_write32(rtwdev, 0x9b4, temp[2]);
}
static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 val;
rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
val = dm_info->dack_dck[RF_PATH_A][0][0];
rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
val = dm_info->dack_dck[RF_PATH_A][0][1];
rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
val = dm_info->dack_dck[RF_PATH_A][1][0];
rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
val = dm_info->dack_dck[RF_PATH_A][1][1];
rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
val = dm_info->dack_dck[RF_PATH_B][0][0];
rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
val = dm_info->dack_dck[RF_PATH_B][0][1];
rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
val = dm_info->dack_dck[RF_PATH_B][1][0];
rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
val = dm_info->dack_dck[RF_PATH_B][1][1];
rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
}
static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
{
rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
rtw8822c_dac_cal_restore_dck(rtwdev);
rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
}
static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
u32 target_addr, u32 toggle_addr)
{
u32 cnt = 0;
do {
rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
return true;
} while (cnt++ < 100);
return false;
}
static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 w_off = 0x1c;
u32 r_off = 0x2c;
u32 w_i, r_i, w_q, r_q;
u32 value;
u32 i;
w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
r_i = rtw8822c_get_path_read_addr(path) + 0x08;
w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
return false;
for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
value = dm_info->dack_msbk[path][0][i];
rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
}
rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
return false;
for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
value = dm_info->dack_msbk[path][1][i];
rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
}
rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
return true;
}
static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
{
if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
return false;
if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
return false;
return true;
}
static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u32 temp[3];
/* sample the first element for both path's IQ vector */
if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
return false;
temp[0] = rtw_read32(rtwdev, 0x1860);
temp[1] = rtw_read32(rtwdev, 0x4160);
temp[2] = rtw_read32(rtwdev, 0x9b4);
rtw8822c_dac_cal_restore_prepare(rtwdev);
if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
!check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
!check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
!check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
return false;
if (!__rtw8822c_dac_cal_restore(rtwdev)) {
rtw_err(rtwdev, "failed to restore dack vectors\n");
return false;
}
rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
rtw_write32(rtwdev, 0x1860, temp[0]);
rtw_write32(rtwdev, 0x4160, temp[1]);
rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
rtw_write32(rtwdev, 0x9b4, temp[2]);
return true;
}
static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
{
struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C];
struct rtw_backup_info backup[DACK_REG_8822C];
u32 ic = 0, qc = 0, i;
u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
if (rtw8822c_dac_cal_restore(rtwdev))
return;
/* not able to restore, do it */
rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
rtw8822c_dac_bb_setting(rtwdev);
/* path-A */
rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
for (i = 0; i < 10; i++) {
rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
ic_a = ic;
qc_a = qc;
rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
&ic, &qc, &i_a, &q_a);
if (ic < 5 && qc < 5)
break;
}
rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
/* path-B */
rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
for (i = 0; i < 10; i++) {
rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
ic_b = ic;
qc_b = qc;
rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
&ic, &qc, &i_b, &q_b);
if (ic < 5 && qc < 5)
break;
}
rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
rtw_write32(rtwdev, 0x1b00, 0x00000008);
rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
rtw_write8(rtwdev, 0x1bcc, 0x0);
rtw_write32(rtwdev, 0x1b00, 0x0000000a);
rtw_write8(rtwdev, 0x1bcc, 0x0);
rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
/* backup results to restore, saving a lot of time */