Update in sync with submodule: prga.py

Author: angl-dev

.readthedocs.yaml

@@ -17,7 +17,8 @@ formats: all
 python:
   version: 3.7
   install:
-    - method: setuptools
+    - requirements: docs/source/requirements.txt
+    - method: pip
       path: prga.py
 
 # include submoduls for building the docs

docs/source/build_your_custom_fpga.rst

@@ -53,8 +53,8 @@ hierarchical description of CLB/IOB structures. Use
 
 .. code-block:: python
     
-    # create IOB
-    iob = context.create_io_block('iob')
+    # create IOB:                 block name, capacity (#blocks per tile)
+    iob = context.create_io_block('iob',      8)
 
     # create ports of the IOB
     clkport = iob.create_global(clk)
@@ -93,7 +93,6 @@ of tile encapsulates an IOB/CLB and the connection boxes around it.
         iotiles[orientation] = context.create_tile(
                 'io_tile_{}'.format(orientation.name),  # name of the tile
                 iob,            # IOB/CLB in the tile
-                8,              # number of IOBs in the tile
                 orientation)    # on which side of the FPGA the tile can be placed
 
 `Orientation` is an enum with 5 values: `Orientation.north`, `Orientation.east`,

docs/source/conf.py

@@ -9,11 +9,10 @@
 # If extensions (or modules to document with autodoc) are in another directory,
 # add these directories to sys.path here. If the directory is relative to the
 # documentation root, use os.path.abspath to make it absolute, like shown here.
-#
+
 # import os
 # import sys
-# sys.path.insert(0, os.path.abspath('.'))
-
+# sys.path.insert(0, os.path.abspath('../../prga.py'))
 
 # -- Project information -----------------------------------------------------
 
@@ -24,7 +23,6 @@
 # The full version, including alpha/beta/rc tags
 release = 'Alpha 0.3'
 
-
 # -- General configuration ---------------------------------------------------
 
 # Add any Sphinx extension module names here, as strings. They can be
@@ -52,14 +50,20 @@
 # The theme to use for HTML and HTML Help pages.  See the documentation for
 # a list of builtin themes.
 #
-html_theme = 'alabaster'
-
+html_theme = 'sphinx_materialdesign_theme'
+html_logo = '_static/images/logo.png'
 html_theme_options = {
-        'logo': 'images/logo.png',
-        'github_user': 'PrincetonUniversity',
-        'github_repo': 'prga',
-        'fixed_sidebar': True,
-        'page_width': "75%",
+        'header_links' : [
+            ('Home', 'index', False, 'home'),
+            ('Github', "https://github.com/PrincetonUniversity/prga", True, 'link'),
+            ], 
+        'fixed_drawer': True,
+        'fixed_header': True,
+        'header_waterfall': True,
+        'header_scroll': False,
+        'show_header_title': False,
+        'show_drawer_title': True,
+        'show_footer': True,
         }
 
 # Add any paths that contain custom static files (such as style sheets) here,

docs/source/index.rst

@@ -10,6 +10,9 @@ Princeton Reconfigurable Gate Array (PRGA) is a customizable, scalable,
 versatile, extensible open-source framework for building and using custom
 FPGAs.
 
+Visit PRGA's github repo: `github.com/PrincetonUniversity/prga
+<https://github.com/PrincetonUniversity/prga>`_
+
 Features
 --------
 * Highly customizable FPGA structures: bring your own IP cores, design your

docs/source/requirements.txt

@@ -0,0 +1 @@
+sphinx-materialdesign-theme==0.1.11

envscr/settings.sh

@@ -1,7 +1,7 @@
 function find_binary() {
     binary="$1"
     shift
-    $binary -h 2>&1 >/dev/null
+    /usr/bin/env $binary -h 2>&1 >/dev/null
     if [ "$?" != 0 ]; then
         echo "[Error] Binary not found: $binary"
         echo $@
@@ -10,24 +10,54 @@ function find_binary() {
     return 0
 }
 
+DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )"/.. >/dev/null && pwd )"
+CWD=$PWD
+cd $DIR/envscr
+
+echo "[INFO] Checking the presence of Python Interpreter"
+find_binary python "Check out Python from https://www.python.org/"
+retval=$?
+if [ "$retval" != 0 ]; then return $retval 2>/dev/null; exit $retval; fi
+
+echo "[INFO] Checking the presence of PIP"
+python -m pip 2>&1 >/dev/null
+retval=$?
+if [ "$?" != 0 ]; then
+    echo "[Error] Python module not found: pip"
+    echo "Checkout PIP from: https://pypi.org/project/pip/"
+    return $retval 2>/dev/null
+    exit $retval
+fi
+
+echo "[INFO] Checking if prga.py is installed"
+python -c "from __future__ import absolute_import; import prga" 2>&1 >/dev/null
+retval=$?
+if [ "$retval" != 0 ]; then
+    echo "[INFO] Installing prga.py"
+    python -m pip install -e $DIR/prga.py --user
+fi
+
+echo "[INFO] Checking the presence of VPR"
 find_binary vpr "Check out VPR from " \
     "https://github.com/verilog-to-routing/vtr-verilog-to-routing, " \
     "compile it and find 'vpr' under \$VTR_ROOT/vpr/"
-if [ "$?" != 0 ]; then exit 1; fi
+retval=$?
+if [ "$retval" != 0 ]; then return $retval 2>/dev/null; exit $retval; fi
 
+echo "[INFO] Checking the presence of VPR utility: genfasm"
 find_binary genfasm "Check out VPR from " \
     "https://github.com/verilog-to-routing/vtr-verilog-to-routing, " \
     "compile it and find 'genfasm' under \$VTR_ROOT/build/utils/fasm/"
-if [ "$?" != 0 ]; then exit 1; fi
+retval=$?
+if [ "$retval" != 0 ]; then return $retval 2>/dev/null; exit $retval; fi
 
-find_binary "yosys" "Check out Yosys from " \
+echo "[INFO] Checking the presence of yosys"
+find_binary yosys "Check out Yosys from " \
     "http://www.clifford.at/yosys/, compile and install it"
-if [ "$?" != 0 ]; then exit 1; fi
+retval=$?
+if [ "$retval" != 0 ]; then return $retval 2>/dev/null; exit $retval; fi
 
 rm vpr_stdout.log
+cd $CWD
 
-DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )"/.. >/dev/null && pwd )"
-export PRGA_ROOT=$DIR
-if [[ ":$PYTHONPATH:" != *":$DIR/prga.py:"* ]]; then
-    export PYTHONPATH="$DIR/prga.py${PYTHONPATH:+":$PYTHONPATH"}"
-fi
+echo "[INFO] Environmental setup succeeded!"

examples/fpga/medium/frac_k6_N4_mem8K_42x34/build.py

@@ -17,22 +17,13 @@ def run():
     context.create_segment('L4', 8, 4)
 
     # 2. create IOB
-    iob = context.create_io_block('iob')
+    iob = context.create_io_block('iob', 8)
     while True:
-        clkport = iob.create_global(clk)
         outpad = iob.create_input('outpad', 1)
         inpad = iob.create_output('inpad', 1)
         ioinst = iob.instances['io']
-        iff = iob.instantiate(context.primitives['flipflop'], 'iff')
-        off = iob.instantiate(context.primitives['flipflop'], 'off')
-        iob.connect(clkport, iff.pins['clk'])
-        iob.connect(ioinst.pins['inpad'], iff.pins['D'])
-        iob.connect(iff.pins['Q'], inpad)
         iob.connect(ioinst.pins['inpad'], inpad)
-        iob.connect(clkport, off.pins['clk'])
-        iob.connect(off.pins['Q'], ioinst.pins['outpad'])
         iob.connect(outpad, ioinst.pins['outpad'])
-        iob.connect(outpad, off.pins['D'])
         break
 
     # 3. create tile
@@ -41,7 +32,7 @@ def run():
         if orientation.is_auto:
             continue
         iotiles[orientation] = context.create_tile(
-                'io_tile_{}'.format(orientation.name), iob, 8, orientation)
+                'io_tile_{}'.format(orientation.name), iob, orientation)
 
     # 5. create CLB
     clb = context.create_logic_block('clb')

examples/fpga/tiny/frac_k6_N2_8x8/build.py

@@ -13,22 +13,13 @@ def run():
     context.create_segment('L2', 4, 2)
 
     # 2. create IOB
-    iob = context.create_io_block('iob')
+    iob = context.create_io_block('iob', 4)
     while True:
-        clkport = iob.create_global(clk)
         outpad = iob.create_input('outpad', 1)
         inpad = iob.create_output('inpad', 1)
         ioinst = iob.instances['io']
-        iff = iob.instantiate(context.primitives['flipflop'], 'iff')
-        off = iob.instantiate(context.primitives['flipflop'], 'off')
-        iob.connect(clkport, iff.pins['clk'])
-        iob.connect(ioinst.pins['inpad'], iff.pins['D'])
-        iob.connect(iff.pins['Q'], inpad)
         iob.connect(ioinst.pins['inpad'], inpad)
-        iob.connect(clkport, off.pins['clk'])
-        iob.connect(off.pins['Q'], ioinst.pins['outpad'])
         iob.connect(outpad, ioinst.pins['outpad'])
-        iob.connect(outpad, off.pins['D'])
         break
 
     # 3. create tile
@@ -37,7 +28,7 @@ def run():
         if orientation.is_auto:
             continue
         iotiles[orientation] = context.create_tile(
-                'io_tile_{}'.format(orientation.name), iob, 4, orientation)
+                'io_tile_{}'.format(orientation.name), iob, orientation)
 
     # 5. create CLB
     clb = context.create_logic_block('clb')

examples/fpga/tiny/frac_k6_N2_mem8K_8x8/build.py

@@ -13,22 +13,13 @@ def run():
     context.create_segment('L2', 4, 2)
 
     # 2. create IOB
-    iob = context.create_io_block('iob')
+    iob = context.create_io_block('iob', 4)
     while True:
-        clkport = iob.create_global(clk)
         outpad = iob.create_input('outpad', 1)
         inpad = iob.create_output('inpad', 1)
         ioinst = iob.instances['io']
-        iff = iob.instantiate(context.primitives['flipflop'], 'iff')
-        off = iob.instantiate(context.primitives['flipflop'], 'off')
-        iob.connect(clkport, iff.pins['clk'])
-        iob.connect(ioinst.pins['inpad'], iff.pins['D'])
-        iob.connect(iff.pins['Q'], inpad)
         iob.connect(ioinst.pins['inpad'], inpad)
-        iob.connect(clkport, off.pins['clk'])
-        iob.connect(off.pins['Q'], ioinst.pins['outpad'])
         iob.connect(outpad, ioinst.pins['outpad'])
-        iob.connect(outpad, off.pins['D'])
         break
 
     # 3. create tile
@@ -37,7 +28,7 @@ def run():
         if orientation.is_auto:
             continue
         iotiles[orientation] = context.create_tile(
-                'io_tile_{}'.format(orientation.name), iob, 4, orientation)
+                'io_tile_{}'.format(orientation.name), iob, orientation)
 
     # 5. create CLB
     clb = context.create_logic_block('clb')

examples/fpga/tiny/k4_N2_8x8/build.py

@@ -14,7 +14,7 @@ def run():
     context.create_segment('L1', 12, 1)
 
     # 2. create IOB
-    iob = context.create_io_block('iob')
+    iob = context.create_io_block('iob', 4)
     while True:
         outpad = iob.create_input('outpad', 1)
         inpad = iob.create_output('inpad', 1)
@@ -29,7 +29,7 @@ def run():
         if orientation.is_auto:
             continue
         iotiles[orientation] = context.create_tile(
-                'io_tile_{}'.format(orientation.name), iob, 4, orientation)
+                'io_tile_{}'.format(orientation.name), iob, orientation)
 
     # 4. create cluster
     cluster = context.create_cluster('cluster')