cmd/internal/obj/riscv: add support for vector unit-stride fault-only-first load instructions

Add support for vector unit-stride fault-only-first load instructions to the RISC-V
assembler. This includes vle8ff, vle16ff, vle32ff and vle64ff.

Change-Id: I5575a1ea155663852f92194fb79f08b5d52203de
Reviewed-on: https://go-review.googlesource.com/c/go/+/690115
Reviewed-by: Junyang Shao <[email protected]>
Reviewed-by: Meng Zhuo <[email protected]>
Reviewed-by: Cherry Mui <[email protected]>
Reviewed-by: Joel Sing <[email protected]>
LUCI-TryBot-Result: Go LUCI <[email protected]>

Author: BoyaoWang430

src/cmd/asm/internal/asm/testdata/riscv64.s

@@ -549,6 +549,16 @@ start:
 	VSOXEI64V	V3, V2, (X10)			// a771250e
 	VSOXEI64V	V3, V2, V0, (X10)		// a771250c
 
+	// 31.7.7: Unit-stride Fault-Only-First Loads
+	VLE8FFV		(X10), V8			// 07040503
+	VLE16FFV	(X10), V8			// 07540503
+	VLE32FFV	(X10), V8			// 07640503
+	VLE64FFV	(X10), V8			// 07740503
+	VLE8FFV		(X10), V0, V8			// 07040501
+	VLE16FFV	(X10), V0, V8			// 07540501
+	VLE32FFV	(X10), V0, V8			// 07640501
+	VLE64FFV	(X10), V0, V8			// 07740501
+
 	// 31.7.8: Vector Load/Store Segment Instructions
 
 	// 31.7.8.1: Vector Unit-Stride Segment Loads and Stores

src/cmd/asm/internal/asm/testdata/riscv64error.s

@@ -73,6 +73,7 @@ TEXT errors(SB),$0
 	//
 	VSETIVLI	X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
 	VLE8V		(X10), V1, V3			// ERROR "invalid vector mask register"
+	VLE8FFV		(X10), V1, V3			// ERROR "invalid vector mask register"
 	VSE8V		V3, V1, (X10)			// ERROR "invalid vector mask register"
 	VLSE8V		(X10), X10, V1, V3		// ERROR "invalid vector mask register"
 	VSSE8V		V3, X11, V1, (X10)		// ERROR "invalid vector mask register"

src/cmd/asm/internal/asm/testdata/riscv64validation.s

@@ -20,6 +20,8 @@ TEXT validation(SB),$0
 	VSETVL		X10, X11			// ERROR "expected integer register in rs1 position"
 	VLE8V		(X10), X10			// ERROR "expected vector register in vd position"
 	VLE8V		(V1), V3			// ERROR "expected integer register in rs1 position"
+	VLE8FFV		(X10), X10			// ERROR "expected vector register in vd position"
+	VLE8FFV		(V1), V3			// ERROR "expected integer register in rs1 position"
 	VSE8V		X10, (X10)			// ERROR "expected vector register in vs1 position"
 	VSE8V		V3, (V1)			// ERROR "expected integer register in rd position"
 	VLSE8V		(X10), V3			// ERROR "expected integer register in rs2 position"

src/cmd/internal/obj/riscv/obj.go

@@ -2176,6 +2176,12 @@ var instructions = [ALAST & obj.AMask]instructionData{
 	AVSOXEI32V & obj.AMask: {enc: sVIVEncoding},
 	AVSOXEI64V & obj.AMask: {enc: sVIVEncoding},
 
+	// 31.7.7: Unit-stride Fault-Only-First Loads
+	AVLE8FFV & obj.AMask:  {enc: iVEncoding},
+	AVLE16FFV & obj.AMask: {enc: iVEncoding},
+	AVLE32FFV & obj.AMask: {enc: iVEncoding},
+	AVLE64FFV & obj.AMask: {enc: iVEncoding},
+
 	// 31.7.8: Vector Load/Store Segment Instructions
 	AVLSEG2E8V & obj.AMask:     {enc: iVEncoding},
 	AVLSEG3E8V & obj.AMask:     {enc: iVEncoding},
@@ -3839,7 +3845,7 @@ func instructionsForProg(p *obj.Prog) []*instruction {
 			ins.rs1 = uint32(p.From.Offset)
 		}
 
-	case AVLE8V, AVLE16V, AVLE32V, AVLE64V, AVSE8V, AVSE16V, AVSE32V, AVSE64V, AVLMV, AVSMV,
+	case AVLE8V, AVLE16V, AVLE32V, AVLE64V, AVSE8V, AVSE16V, AVSE32V, AVSE64V, AVLE8FFV, AVLE16FFV, AVLE32FFV, AVLE64FFV, AVLMV, AVSMV,
 		AVLSEG2E8V, AVLSEG3E8V, AVLSEG4E8V, AVLSEG5E8V, AVLSEG6E8V, AVLSEG7E8V, AVLSEG8E8V,
 		AVLSEG2E16V, AVLSEG3E16V, AVLSEG4E16V, AVLSEG5E16V, AVLSEG6E16V, AVLSEG7E16V, AVLSEG8E16V,
 		AVLSEG2E32V, AVLSEG3E32V, AVLSEG4E32V, AVLSEG5E32V, AVLSEG6E32V, AVLSEG7E32V, AVLSEG8E32V,