Parsing Error for integer memories

[kwmartin]

The following code parses fine using iverilog and seems to run. However, it gets a syntax error for the declaration of array3 when using pyverilog to compile. Section 3.10.2 of the IEEE Verilog standard indicates that integer memories should be supported.
module fixedsize_array; //declaration of array’s reg array1[0:5]; //single dimension array reg array2[2:0][3:0]; //multi dimension array integer array3[5:0]; //single dimension array initial begin //array initialization array1[0] = 1; array2[0][1] = 0; array3[5] = 117; end endmodule