From 9a49dcd4790633967d585f716c6274dd406d5c85 Mon Sep 17 00:00:00 2001
From: Gunar Schorcht <gunar@schorcht.net>
Date: Mon, 2 Oct 2023 01:44:12 +0200
Subject: [PATCH] cpu/esp32: fix RISC-V ISA for ESP32-C3 with GCC 12.2

---
 cpu/esp32/Makefile.include | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/cpu/esp32/Makefile.include b/cpu/esp32/Makefile.include
index 9d084eca1efe..a0a62d24fcd4 100644
--- a/cpu/esp32/Makefile.include
+++ b/cpu/esp32/Makefile.include
@@ -241,7 +241,8 @@ CFLAGS += -D_CONST=const
 
 # TODO no relaxation yet
 ifneq (,$(filter riscv%,$(TARGET_ARCH)))
-  CFLAGS += -mno-relax -march=rv32imc -mabi=ilp32 -DRISCV_NO_RELAX
+  CFLAGS += -mno-relax -march=rv32imc_zicsr_zifencei -mabi=ilp32 -DRISCV_NO_RELAX
+  LINKFLAGS += -mno-relax -march=rv32imc_zicsr_zifencei -mabi=ilp32
   GCC_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | \
                                $(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 \
                                                   -misa-spec=2.2 -E - > /dev/null 2>&1 && \