diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h index 119d3da9a77..610e3f5b2e5 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h @@ -21,7 +21,16 @@ extern "C" { #ifndef DAC1_INIT_PARAMS #define DAC1_INIT_PARAMS \ { \ - .name = "dac1", \ + .name = "dac1", \ + .vref = 3300, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/settings/project.dni b/bsp/hc32/ev_hc32f448_lqfp80/settings/project.dni new file mode 100644 index 00000000000..7941e713931 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/settings/project.dni @@ -0,0 +1,46 @@ +[PlDriver] +MemConfigValue=$PROJ_DIR$/../libraries/hc32f448_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd +[PlCacheRanges] +CustomRanges0=0 0 262144 1 2048 +CustomRangesText0=Flash +CustomRanges1=0 50334720 1024 1 2048 +CustomRangesText1=OTP +CustomRanges2=0 536838144 65536 0 2048 +CustomRangesText2=SRAM +CustomRanges3=0 537853952 4096 0 2048 +CustomRangesText3=SRAMB +CustomRanges4=0 1073741824 536870912 2 0 +CustomRangesText4=Peripheral +CustomRanges5=0 1610612736 536870912 0 2048 +CustomRangesText5=EXMC SRAM +CustomRanges6=0 2281701376 1024 2 1024 +CustomRangesText6=EXMC SRAM_REG +CustomRanges7=0 2550136832 67108864 1 2048 +CustomRangesText7=QSPI +CustomRanges8=0 2617245696 67108864 2 67108864 +CustomRangesText8=QSPI_REG +CustomRanges9=0 3758096384 536870912 2 0 +CustomRangesText9=Private peripheral +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Disassemble mode] +mode=0 +[Breakpoints2] +Count=0 +[Aliases] +Count=0 +SuppressDialog=0 +[Jet] +DisableInterrupts=0 +LeaveRunning=0 +MultiCoreRunAll=0 +[ArmDriver] +EnableCache=0 diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h index be50c03aa51..f942e7ef72c 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h @@ -109,6 +109,27 @@ #define DAC1_CH2_PIN (GPIO_PIN_05) #endif +#if defined(BSP_USING_DAC2) + #define DAC2_CH1_PORT (GPIO_PORT_A) + #define DAC2_CH1_PIN (GPIO_PIN_06) + #define DAC2_CH2_PORT (GPIO_PORT_A) + #define DAC2_CH2_PIN (GPIO_PIN_07) +#endif + +#if defined(BSP_USING_DAC3) + #define DAC3_CH1_PORT (GPIO_PORT_C) + #define DAC3_CH1_PIN (GPIO_PIN_04) + #define DAC3_CH2_PORT (GPIO_PORT_C) + #define DAC3_CH2_PIN (GPIO_PIN_05) +#endif + +#if defined(BSP_USING_DAC4) + #define DAC4_CH1_PORT (GPIO_PORT_E) + #define DAC4_CH1_PIN (GPIO_PIN_07) + #define DAC4_CH2_PORT (GPIO_PORT_E) + #define DAC4_CH2_PIN (GPIO_PIN_08) +#endif + /*********** CAN configure *********/ #if defined(BSP_USING_CAN1) #define CAN1_TX_PORT (GPIO_PORT_D) diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h index 3c4c2c70108..fb01e4061eb 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h @@ -22,7 +22,17 @@ extern "C" { #ifndef DAC1_INIT_PARAMS #define DAC1_INIT_PARAMS \ { \ - .name = "dac1", \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + .ch1_amp_gain = DAC_AMP_GAIN_1, \ + .ch2_amp_gain = DAC_AMP_GAIN_1, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ @@ -31,7 +41,17 @@ extern "C" { #ifndef DAC2_INIT_PARAMS #define DAC2_INIT_PARAMS \ { \ - .name = "dac2", \ + .name = "dac2", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + .ch1_amp_gain = DAC_AMP_GAIN_1, \ + .ch2_amp_gain = DAC_AMP_GAIN_1, \ } #endif /* DAC2_INIT_PARAMS */ #endif /* BSP_USING_DAC2 */ @@ -40,7 +60,17 @@ extern "C" { #ifndef DAC3_INIT_PARAMS #define DAC3_INIT_PARAMS \ { \ - .name = "dac3", \ + .name = "dac3", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + .ch1_amp_gain = DAC_AMP_GAIN_1, \ + .ch2_amp_gain = DAC_AMP_GAIN_1, \ } #endif /* DAC3_INIT_PARAMS */ #endif /* BSP_USING_DAC3 */ @@ -49,7 +79,17 @@ extern "C" { #ifndef DAC4_INIT_PARAMS #define DAC4_INIT_PARAMS \ { \ - .name = "dac4", \ + .name = "dac4", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + .ch1_amp_gain = DAC_AMP_GAIN_1, \ + .ch2_amp_gain = DAC_AMP_GAIN_1, \ } #endif /* DAC4_INIT_PARAMS */ #endif /* BSP_USING_DAC4 */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c index e73f77883a8..5e05d061786 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c @@ -105,6 +105,13 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) #endif #if defined(RT_USING_DAC) +#if defined(BSP_USING_DAC2) +void EthPhyDisable(void) +{ + TCA9539_WritePin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_DIR_OUT); +} +#endif rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) { rt_err_t result = RT_EOK; diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h index f697eba881d..c4e155dc9a2 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h @@ -21,7 +21,17 @@ extern "C" { #ifndef DAC1_INIT_PARAMS #define DAC1_INIT_PARAMS \ { \ - .name = "dac1", \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ @@ -30,7 +40,17 @@ extern "C" { #ifndef DAC2_INIT_PARAMS #define DAC2_INIT_PARAMS \ { \ - .name = "dac2", \ + .name = "dac2", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC2_INIT_PARAMS */ #endif /* BSP_USING_DAC2 */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h index bcd6657ade0..74efa2c51eb 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h @@ -61,5 +61,13 @@ /** * @} */ - +/** + * @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition + * @{ + */ +#define ETH_RST_PORT (TCA9539_IO_PORT1) +#define ETH_RST_PIN (EIO_ETH_RST) +/** + * @} + */ #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c index f89e5656dc4..11df23379ba 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c @@ -19,6 +19,7 @@ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) #define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM1) /** * @brief This thread is used to monitor whether XTAL32 is stable. @@ -42,22 +43,22 @@ void xtal32_fcm_thread_entry(void *parameter) stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); - (void)FCM_Init(&stcFcmInit); + (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); /* Enable FCM, to ensure xtal32 stable */ - FCM_Cmd(ENABLE); + FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); while (1) { - if (SET == FCM_GetStatus(FCM_FLAG_END)) + if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END)) { - FCM_ClearStatus(FCM_FLAG_END); - if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF))) + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END); + if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF))) { - FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF); + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF); } else { - (void)FCM_DeInit(); + (void)FCM_DeInit(XTAL32_FCM_UNIT); FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); /* XTAL32 stabled */ break; @@ -66,7 +67,7 @@ void xtal32_fcm_thread_entry(void *parameter) u32TimeOut++; if (u32TimeOut > u32Time) { - (void)FCM_DeInit(); + (void)FCM_DeInit(XTAL32_FCM_UNIT); FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); rt_kprintf("Error: XTAL32 still unstable, timeout.\n"); break; diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig index 9aa6c2cbef3..b9ef6f7c099 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig @@ -53,16 +53,6 @@ menu "Onboard Peripheral Drivers" config ETH_INTERFACE_USING_RMII bool "ETH Communication USING RMII" endchoice - - menuconfig ETH_PHY_USING_INTERRUPT_MODE - bool "Enable ETH PHY interrupt mode" - default n - if ETH_PHY_USING_INTERRUPT_MODE - config ETH_PHY_INTERRUPT_PIN - int "ETH PHY Interrupt pin number" - range 1 176 - default 16 - endif endif config BSP_USING_EXMC @@ -142,6 +132,12 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 64 endif menuconfig BSP_USING_UART2 @@ -169,6 +165,12 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 256 + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 64 endif menuconfig BSP_USING_UART3 @@ -247,6 +249,12 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 256 + + config BSP_UART6_DMA_PING_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 64 endif menuconfig BSP_USING_UART7 @@ -274,8 +282,13 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 256 - endif + config BSP_UART7_DMA_PING_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 64 + endif menuconfig BSP_USING_UART8 bool "Enable UART8" @@ -600,7 +613,7 @@ menu "On-chip Peripheral Drivers" endif menuconfig RT_USING_CAN_MCAN - bool "Enable CAN/MAN" + bool "Enable CAN/MCAN" select RT_USING_CAN select RT_CAN_USING_HDR select BSP_USING_TCA9539 @@ -664,6 +677,9 @@ menu "On-chip Peripheral Drivers" config BSP_RTC_USING_LRC bool "RTC USING LRC" + + config BSP_RTC_USING_XTAL_DIV + bool "RTC Using XTAL Division" endchoice endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c index 78e1e3c37d1..85514577772 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c @@ -105,6 +105,13 @@ rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) #endif #if defined(RT_USING_DAC) +#if defined(BSP_USING_DAC2) +void EthPhyDisable(void) +{ + TCA9539_WritePin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_DIR_OUT); +} +#endif rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) { rt_err_t result = RT_EOK; diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dac_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dac_config.h index f697eba881d..c4e155dc9a2 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dac_config.h @@ -21,7 +21,17 @@ extern "C" { #ifndef DAC1_INIT_PARAMS #define DAC1_INIT_PARAMS \ { \ - .name = "dac1", \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ @@ -30,7 +40,17 @@ extern "C" { #ifndef DAC2_INIT_PARAMS #define DAC2_INIT_PARAMS \ { \ - .name = "dac2", \ + .name = "dac2", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC2_INIT_PARAMS */ #endif /* BSP_USING_DAC2 */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/hc32f4xx_conf.h index 77cd14ec33b..7227ae289f0 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/hc32f4xx_conf.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/hc32f4xx_conf.h @@ -146,44 +146,14 @@ extern "C" #define ETH_MAC_ADDR4 (0x00U) #define ETH_MAC_ADDR5 (0x00U) -/* Common PHY Registers */ -#define PHY_BCR (0x00U) /*!< Basic Control Register */ -#define PHY_BSR (0x01U) /*!< Basic Status Register */ - -#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */ -#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */ -#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */ - -#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */ -#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */ -#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */ -#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */ -#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */ - #if defined (ETH_PHY_USING_RTL8201F) /* PHY(RTL8201F) Address*/ -#define ETH_PHY_ADDR (0x00U) - -/* PHY Configuration delay(ms) */ -#define ETH_PHY_RST_DELAY (0x0080UL) -#define ETH_PHY_CONFIG_DELAY (0x0800UL) -#define ETH_PHY_RD_TIMEOUT (0x0005UL) -#define ETH_PHY_WR_TIMEOUT (0x0005UL) +#define ETH_PHY_ADDR (0x01U) /* PHY Status Register */ -#define PHY_SR (PHY_BCR) /*!< PHY status register */ - -#define PHY_DUPLEX_STATUS (PHY_FULLDUPLEX_10M) /*!< PHY Duplex mask */ -#define PHY_SPEED_STATUS (PHY_HALFDUPLEX_100M) /*!< PHY Speed mask */ +#define PHY_SR (0x00U) /*!< PHY status register */ +#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/tca9539_port.h index 50a11b412bd..b5761c43c9e 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/tca9539_port.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/tca9539_port.h @@ -63,5 +63,13 @@ /** * @} */ - +/** + * @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition + * @{ + */ +#define ETH_RST_PORT (TCA9539_IO_PORT1) +#define ETH_RST_PIN (EIO_ETH_RST) +/** + * @} + */ #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dac.c b/bsp/hc32/libraries/hc32_drivers/drv_dac.c index 34e18c9eb0f..afc1b4bd9c9 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_dac.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_dac.c @@ -17,6 +17,7 @@ #include "rtdevice.h" #include "hc32_ll.h" #include +#include "board_config.h" /* DAC features */ #define DAC_CHANNEL_ID_MAX (DAC_CH2 + 1U) @@ -36,7 +37,7 @@ static dac_device _g_dac_dev_array[] = #ifdef BSP_USING_DAC1 { {0}, -#if defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) CM_DAC1, #elif defined (HC32F448) CM_DAC, @@ -147,7 +148,7 @@ static const struct rt_dac_ops g_dac_ops = static void _dac_clock_enable(void) { #if defined(BSP_USING_DAC1) -#if defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DAC1, ENABLE); #elif defined (HC32F448) FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DAC, ENABLE); @@ -170,12 +171,42 @@ int rt_hw_dac_init(void) int result = RT_EOK; rt_err_t ret; int i = 0; + stc_dac_init_t stcDacInit = {0}; + int32_t ll_ret = 0; _dac_clock_enable(); uint32_t dev_cnt = sizeof(_g_dac_dev_array) / sizeof(_g_dac_dev_array[0]); for (; i < dev_cnt; i++) { DAC_DeInit(_g_dac_dev_array[i].instance); + stcDacInit.enOutput = _g_dac_dev_array[i].init.ch1_output_enable; +#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) + stcDacInit.u16Src = _g_dac_dev_array[i].init.ch1_data_src; +#endif + ll_ret = DAC_Init((void *)_g_dac_dev_array[i].instance, DAC_CH1, &stcDacInit); +#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) + stcDacInit.u16Src = _g_dac_dev_array[i].init.ch2_data_src; +#endif + stcDacInit.enOutput = _g_dac_dev_array[i].init.ch2_output_enable; + ll_ret = DAC_Init((void *)_g_dac_dev_array[i].instance, DAC_CH2, &stcDacInit); + DAC_DataRegAlignConfig(_g_dac_dev_array[i].instance, _g_dac_dev_array[i].init.data_align); + + if (ll_ret != LL_OK) + { + ret = -RT_ERROR; + break; + } + + DAC_ADCPrioConfig(_g_dac_dev_array[i].instance, _g_dac_dev_array[i].init.dac_adp_sel, ENABLE); + DAC_ADCPrioCmd(_g_dac_dev_array[i].instance, _g_dac_dev_array[i].init.dac_adp_enable); + +#if defined (HC32F472) + DAC_SetAmpGain(_g_dac_dev_array[i].instance, DAC_CH1, _g_dac_dev_array[i].init.ch1_amp_gain); + DAC_SetAmpGain(_g_dac_dev_array[i].instance, DAC_CH2, _g_dac_dev_array[i].init.ch2_amp_gain); +#endif + DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH1, _g_dac_dev_array[i].init.ch1_amp_enable); + DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH2, _g_dac_dev_array[i].init.ch2_amp_enable); + rt_hw_board_dac_init(_g_dac_dev_array[i].instance); ret = rt_hw_dac_register(&_g_dac_dev_array[i].rt_dac, \ (const char *)_g_dac_dev_array[i].init.name, \ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dac.h b/bsp/hc32/libraries/hc32_drivers/drv_dac.h index 7eb221dd049..8918b63fd27 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_dac.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_dac.h @@ -28,6 +28,24 @@ extern "C" struct dac_dev_init_params { char name[8]; + uint16_t vref; /*!< Specifies the ADC reference voltage, unit is mv */ + uint16_t data_align; /*!can_device; CM_MCAN_TypeDef *MCANx = driver->mcan.instance; @@ -869,7 +869,7 @@ rt_inline void mcan_isr(hc32_mcan_driver_t *driver) uint32_t ndat2 = MCANx->NDAT2; int rx_buf_index; - MCAN_ClearStatus(MCANx, ir_status); + MCAN_ClearStatus(MCANx, ir_status & int_sel); /* Check normal status flag */ /* Transmission completed */ @@ -974,7 +974,7 @@ void MCAN1_INT0_Handler(void) /* enter interrupt */ rt_interrupt_enter(); - mcan_isr(&m_mcan_driver_list[MCAN1_INDEX]); + mcan_isr(&m_mcan_driver_list[MCAN1_INDEX], m_mcan_driver_list[MCAN1_INDEX].mcan.int0_sel); /* leave interrupt */ rt_interrupt_leave(); @@ -985,7 +985,7 @@ void MCAN1_INT1_Handler(void) /* enter interrupt */ rt_interrupt_enter(); - mcan_isr(&m_mcan_driver_list[MCAN1_INDEX]); + mcan_isr(&m_mcan_driver_list[MCAN1_INDEX], m_mcan_driver_list[MCAN1_INDEX].mcan.int1_sel); /* leave interrupt */ rt_interrupt_leave(); @@ -998,7 +998,7 @@ void MCAN2_INT0_Handler(void) /* enter interrupt */ rt_interrupt_enter(); - mcan_isr(&m_mcan_driver_list[MCAN2_INDEX]); + mcan_isr(&m_mcan_driver_list[MCAN2_INDEX], m_mcan_driver_list[MCAN2_INDEX].mcan.int0_sel); /* leave interrupt */ rt_interrupt_leave(); @@ -1009,7 +1009,7 @@ void MCAN2_INT1_Handler(void) /* enter interrupt */ rt_interrupt_enter(); - mcan_isr(&m_mcan_driver_list[MCAN2_INDEX]); + mcan_isr(&m_mcan_driver_list[MCAN2_INDEX], m_mcan_driver_list[MCAN2_INDEX].mcan.int1_sel); /* leave interrupt */ rt_interrupt_leave(); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.c b/bsp/hc32/libraries/hc32_drivers/drv_pm.c index b9013b109d5..7d5a3308ac4 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.c @@ -108,7 +108,7 @@ static void _sleep_enter_deep(void) (void)PWC_STOP_Config(&sleep_deep_cfg.cfg); -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) +#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) if (PWC_PWRC2_DVS == (READ_REG8(CM_PWC->PWRC2) & PWC_PWRC2_DVS)) { CLR_REG8_BIT(CM_PWC->PWRC1, PWC_PWRC1_STPDAS); @@ -164,7 +164,7 @@ static void _run_switch_high_to_low(void) st_run_mode_cfg.sys_clk_cfg(PM_RUN_MODE_LOW_SPEED); -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) +#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) PWC_HighSpeedToLowSpeed(); #endif } @@ -173,7 +173,7 @@ static void _run_switch_low_to_high(void) { struct pm_run_mode_config st_run_mode_cfg = PM_RUN_MODE_CFG; -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) +#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) PWC_LowSpeedToHighSpeed(); #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.h b/bsp/hc32/libraries/hc32_drivers/drv_pm.h index 40c10041894..6ef620b1a83 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.h @@ -89,7 +89,7 @@ struct pm_sleep_mode_shutdown_config /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ -#if defined(HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A8) #define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET) && (EFM_GetStatus(EFM_FLAG_RDY1) == SET)) #elif defined(HC32F460) || defined (HC32F448) || defined (HC32F472) #define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET)) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c index 007cd8f03f3..179333ce30d 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c @@ -22,7 +22,7 @@ #define LOG_TAG "drv.rtc" #include -#if defined(HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A8) /* BACKUP REG: 96~127 for RTC used */ #define RTC_BACKUP_DATA_SIZE (32U) #define RTC_BACKUP_REG_OFFSET (128U - RTC_BACKUP_DATA_SIZE) @@ -60,7 +60,7 @@ static struct stc_hc32_alarm_irq hc32_alarm_irq = }; #endif -#if defined(HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A8) static void _bakup_reg_write(void) { uint8_t u8Num; @@ -178,7 +178,7 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) #else #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) #endif -#elif defined(HC32F448) +#elif defined(HC32F448) || defined(HC32F4A8) #if defined(BSP_RTC_USING_XTAL32) #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) #elif defined(BSP_RTC_USING_XTAL_DIV) @@ -198,11 +198,26 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) #endif #endif +#if defined(HC32F4A8) +static en_flag_status_t VBAT_PowerDownCheck(void) +{ + en_flag_status_t ret; + ret = PWC_VBAT_GetStatus(PWC_FLAG_VBAT_POR); + if (SET == ret) + { + PWC_VBAT_ClearStatus(PWC_FLAG_VBAT_POR); + } + return ret; +} +#endif + static rt_err_t _rtc_init(void) { stc_rtc_init_t stcRtcInit; -#if defined(HC32F4A0) +#if defined(HC32F4A8) + if ((SET == VBAT_PowerDownCheck()) || (LL_OK != _bakup_reg_check()) || (LL_OK != _hc32_rtc_rw_check())) +#elif defined(HC32F4A0) if ((LL_OK != _bakup_reg_check()) || (LL_OK != _hc32_rtc_rw_check())) #elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) if (DISABLE == RTC_GetCounterState()) @@ -231,7 +246,7 @@ static rt_err_t _rtc_init(void) /* Startup RTC count */ RTC_Cmd(ENABLE); -#if defined(HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A8) /* Write sequence flag to backup register */ _bakup_reg_write(); #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c index 58eb5da6d1d..549b698c63e 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c @@ -28,7 +28,7 @@ #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_64HZ) #define PWC_WKT_COUNT_FRQ (64U) #else - #if defined(HC32F4A0) + #if defined(HC32F4A0) || defined(HC32F4A8) #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_RTCLRC) #elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_LRC) @@ -119,7 +119,7 @@ int rt_hw_wktm_init(void) /* WKTM init */ PWC_WKT_Config(PWC_WKT_CLK_SRC, CMPVAL_MAX); -#if defined(HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A8) /* F4A0 if select RTCLRC clock need open the LRCEN by RTC->CR3 register */ #if (PWC_WKT_CLK_SRC == PWC_WKT_CLK_SRC_RTCLRC) MODIFY_REG8(CM_RTC->CR3, RTC_CR3_LRCEN, 0x01U << RTC_CR3_LRCEN_POS); diff --git a/bsp/hc32/tests/test_can.c b/bsp/hc32/tests/test_can.c index d927bc6e310..4424c265276 100644 --- a/bsp/hc32/tests/test_can.c +++ b/bsp/hc32/tests/test_can.c @@ -115,7 +115,7 @@ static void can_rx_thread(void *parameter) rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg)); /* 打印数据 ID 及内容 */ rt_kprintf("ID:%x Data:", rxmsg.id); - for (int i = 0; i < 8; i++) + for (int i = 0; i < rxmsg.len; i++) { rt_kprintf("%2x ", rxmsg.data[i]); } diff --git a/bsp/hc32/tests/test_dac.c b/bsp/hc32/tests/test_dac.c index a80db59fe0d..36e3e134bff 100644 --- a/bsp/hc32/tests/test_dac.c +++ b/bsp/hc32/tests/test_dac.c @@ -24,6 +24,10 @@ #define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ #define DAC_MAX_OUTPUT_VALUE 4095 +#if (defined (HC32F4A8) || defined (HC32F4A0)) && defined (BSP_USING_DAC2) + extern void EthPhyDisable(void); +#endif /* HC32F4A8 && BSP_USING_DAC2 */ + static int dac_vol_sample(int argc, char *argv[]) { char dac_device_name[] = "dac1"; @@ -41,7 +45,7 @@ static int dac_vol_sample(int argc, char *argv[]) { rt_strcpy(dac_device_name, "dac1"); } -#if defined (HC32F4A0) || defined (HC32F472) +#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) else if (0 == rt_strcmp(argv[1], "dac2")) { rt_strcpy(dac_device_name, "dac2"); @@ -63,7 +67,9 @@ static int dac_vol_sample(int argc, char *argv[]) return -RT_ERROR; } } - +#if (defined (HC32F4A8) || defined (HC32F4A0)) && defined (BSP_USING_DAC2) + EthPhyDisable(); +#endif /* 查找设备 */ dac_dev = (rt_dac_device_t)rt_device_find(dac_device_name); if (dac_dev == RT_NULL) diff --git a/bsp/hc32/tests/test_pm.c b/bsp/hc32/tests/test_pm.c index bf463fa5dd0..8b41616363f 100644 --- a/bsp/hc32/tests/test_pm.c +++ b/bsp/hc32/tests/test_pm.c @@ -25,8 +25,8 @@ * PM_SLEEP_MODE_SHUTDOWN | 掉电模式3或4（可配，默认配置是模式3） * * 操作步骤1： -* 1）按下按键K10： MCU进入休眠模式 -* 2）再按下按键K10：MCU退出休眠模式 +* 1）按下WKUP按键： MCU进入休眠模式 +* 2）再按下WKUP按键：MCU退出休眠模式 * 3）重复上述按键操作，MCU循环进入休眠模式(deep、standby、shutdown、idle)和退出对应的休眠模式。 * 每次进入休眠模式前，MCU打印 "sleep:" + 休眠模式名称 * 每次退出休眠模式后，MCU打印 "wake from sleep:" + 休眠模式名称 @@ -41,9 +41,9 @@ #if defined(BSP_USING_PM) -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A8) #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) - #define BSP_KEY_PORT (GPIO_PORT_A) /* Key10 */ + #define BSP_KEY_PORT (GPIO_PORT_A) #define BSP_KEY_PIN (GPIO_PIN_00) #define BSP_KEY_EXTINT (EXTINT_CH00) #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ0) @@ -53,6 +53,9 @@ #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP0) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP00) + #define LED_GREEN_PORT (GPIO_PORT_C) + #define LED_GREEN_PIN (GPIO_PIN_09) + #define MCO_PORT (GPIO_PORT_A) #define MCO_PIN (GPIO_PIN_08) #define MCO_GPIO_FUNC (GPIO_FUNC_1) @@ -69,6 +72,9 @@ #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP01) + #define LED_GREEN_PORT (GPIO_PORT_D) + #define LED_GREEN_PIN (GPIO_PIN_04) + #define MCO_PORT (GPIO_PORT_A) #define MCO_PIN (GPIO_PIN_08) #define MCO_GPIO_FUNC (GPIO_FUNC_1) @@ -85,6 +91,9 @@ #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP12) + #define LED_GREEN_PORT (GPIO_PORT_A) + #define LED_GREEN_PIN (GPIO_PIN_02) + #define MCO_PORT (GPIO_PORT_A) #define MCO_PIN (GPIO_PIN_08) #define MCO_GPIO_FUNC (GPIO_FUNC_1) @@ -100,6 +109,10 @@ #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ5) #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP11) + + #define LED_GREEN_PORT (GPIO_PORT_C) + #define LED_GREEN_PIN (GPIO_PIN_09) + #endif #define KEYCNT_BACKUP_ADDR (uint32_t *)(0x200F0010) @@ -205,7 +218,7 @@ static void _sleep_enter_event_deep(void) static void _sleep_enter_event_standby(void) { _wkup_cfg_sleep_standby(); -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A8) PWC_BKR_Write(0, g_keycnt_cmd & 0xFF); #endif *KEYCNT_BACKUP_ADDR = g_keycnt_cmd; @@ -268,6 +281,7 @@ static void _notify_func(uint8_t event, uint8_t mode, void *data) { return; } + GPIO_ResetPins(LED_GREEN_PORT, LED_GREEN_PIN); sleep_enter_func[mode](); } else @@ -322,7 +336,7 @@ static void pm_cmd_handler(void *parameter) } } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) +#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) static void pm_run_main(void *parameter) { static rt_uint8_t run_index = 0; @@ -355,7 +369,7 @@ static void pm_run_main(void *parameter) static void _keycnt_cmd_init_after_power_on(void) { en_flag_status_t wkup_from_ptwk = PWC_PD_GetWakeupStatus(PWC_PD_WKUP_FLAG_WKUP0); -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A8) en_flag_status_t bakram_pd = PWC_BKR_GetStatus(PWC_BACKUP_RAM_FLAG_RAMPDF); uint8_t bkr0 = PWC_BKR_Read(0); @@ -393,7 +407,7 @@ static void _keycnt_cmd_init_after_power_on(void) pm_dbg("KEYCNT_BACKUP_ADDR addr =0x%p,value = %d\n", KEYCNT_BACKUP_ADDR, *KEYCNT_BACKUP_ADDR); pm_dbg("wkup_from_ptwk = %d\n", wkup_from_ptwk); -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A8) pm_dbg("bakram_pd = %d\n", bakram_pd); pm_dbg("bkr0 = %d\n", bkr0); #endif @@ -401,7 +415,7 @@ static void _keycnt_cmd_init_after_power_on(void) static void _vbat_init(void) { -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F4A8) while (PWC_BKR_GetStatus(PWC_BACKUP_RAM_FLAG_RAMVALID) == RESET) { rt_thread_delay(10); @@ -437,7 +451,7 @@ int pm_sample_init(void) rt_kprintf("create pm sample thread failed!\n"); } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) +#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) thread = rt_thread_create("pm_run_main", pm_run_main, RT_NULL, 1024, 25, 10); if (thread != RT_NULL) {