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OpenNAS is an open source VHDL-based Neuromorphic Auditory Sensor (NAS) code generator capable of automatically generating the necessary files to create a VHDL project for FPGA. OpenNAS guides designers with a friendly interface and allows NAS specification using a five-steps wizard for later code generation. It includes several audio input interfaces (AC'97 audio codec, I2S ADC and PDM microphones), different processing architectures (cascade and parallel filter banks), and a set of neuromorphic output interfaces (parallel AER and Spinnaker). After NAS generation, designers have everything prepared for building and synthesizing the VHDL project for a target FPGA using manufacturer's tools.
OpenNAS generated files are currently compatible from VHDL93 in advance, also support Verilog 95 and Verilog 2001.
OpenNAS has been tested with Xilinx ISE 14.1, Xilinx Vivado 2020.1 in several editions (WebPack, Systems Edition, HLS...), and Intel Quartus Prime is also supported. OpenNAS can be simulated using ModelSim PE 9.2b.
As OpenNAS is concieved to be synthetised in any FPGA, has been tested in our labs with the next FPGAs:
