From 1f974c5c41a46e3ff77ceda20acd2c448c2fd597 Mon Sep 17 00:00:00 2001 From: Christophe Roullier Date: Fri, 6 Sep 2019 08:48:54 +0200 Subject: [PATCH] net: stmmac: increase delay of SWR for specific PHY with lots of latency During suspend/resume sequence, in resume we performed software reset (SWR). Just before SWR we performed phy_start, and sometimes phy is not completely start when we perform it. Need to increase delay of SWR sequence to be sure that phy start is complete. Signed-off-by: Christophe Roullier Change-Id: I756065bc875bacc7e3900e218b6deacc5c3448da Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/linux-stm32/+/142222 Reviewed-by: CITOOLS Reviewed-by: CIBUILD Reviewed-by: Alexandre TORGUE --- drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c index 49f5687879df24..5b3507100a5059 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c @@ -22,7 +22,7 @@ int dwmac4_dma_reset(void __iomem *ioaddr) /* DMA SW reset */ value |= DMA_BUS_MODE_SFT_RESET; writel(value, ioaddr + DMA_BUS_MODE); - limit = 10; + limit = 100; while (limit--) { if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) break;