interconnect.h

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#ifndef __INTERCONNECT_H__
#define __INTERCONNECT_H__

#include "assert.h"
#include "basic_components.h"
#include "cacti/basic_circuit.h"
#include "cacti/cacti_interface.h"
#include "cacti/component.h"
#include "cacti/parameter.h"
#include "cacti/subarray.h"
#include "cacti/wire.h"

// leakge power includes entire htree in a bank (when uca_tree == false)
// leakge power includes only part to one bank when uca_tree == true
using namespace cacti;

class interconnect : public Component {
 public:
  interconnect(string name_, enum Device_ty device_ty_, double base_w,
               double base_h, int data_w, double len,
               const InputParameter *configure_interface,
               int start_wiring_level_, bool pipelinable_ = false,
               double route_over_perc_ = 0.5, bool opt_local_ = true,
               enum Core_type core_ty_ = Inorder,
               enum Wire_type wire_model = Global, double width_s = 1.0,
               double space_s = 1.0,
               TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));

  ~interconnect(){};

  void compute();
  string name;
  enum Device_ty device_ty;
  double in_rise_time, out_rise_time;
  InputParameter l_ip;
  uca_org_t local_result;
  Area no_device_under_wire_area;
  void set_in_rise_time(double rt) { in_rise_time = rt; }

  void leakage_feedback(double temperature);
  double max_unpipelined_link_delay;
  powerDef power_bit;

  double wire_bw;
  double init_wire_bw;  // bus width at root
  double base_width;
  double base_height;
  int data_width;
  enum Wire_type wt;
  double width_scaling, space_scaling;
  int start_wiring_level;
  double length;
  double min_w_nmos;
  double min_w_pmos;
  double latency, throughput;
  bool latency_overflow;
  bool throughput_overflow;
  double interconnect_latency;
  double interconnect_throughput;
  bool opt_local;
  enum Core_type core_ty;
  bool pipelinable;
  double route_over_perc;
  int num_pipe_stages;

 private:
  TechnologyParameter::DeviceType *deviceType;
};

#endif