From 7c27775691d656569691423041ad4618cac4d3a4 Mon Sep 17 00:00:00 2001
From: mikee47 <mike@silyhouse.net>
Date: Mon, 8 Jan 2024 23:57:05 +0000
Subject: [PATCH] Fix floating point issues with esp32c3

Missing compiler and link flags
Probably since 5.0
---
 Sming/Arch/Esp32/app.mk   |  6 ++++++
 Sming/Arch/Esp32/build.mk | 11 ++++++++++-
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/Sming/Arch/Esp32/app.mk b/Sming/Arch/Esp32/app.mk
index 42271785d1..8fc7a3c151 100644
--- a/Sming/Arch/Esp32/app.mk
+++ b/Sming/Arch/Esp32/app.mk
@@ -9,6 +9,12 @@ LDFLAGS	+= \
 	-nostdlib \
 	-Wl,-static
 
+ifdef IDF_TARGET_ARCH_RISCV
+	LDFLAGS += \
+		-nostartfiles \
+		-march=$(ESP32_RISCV_ARCH) \
+		--specs=nosys.specs
+endif
 
 .PHONY: application
 application: $(TARGET_BIN)
diff --git a/Sming/Arch/Esp32/build.mk b/Sming/Arch/Esp32/build.mk
index 2c615737e9..4db95bf8c7 100644
--- a/Sming/Arch/Esp32/build.mk
+++ b/Sming/Arch/Esp32/build.mk
@@ -41,6 +41,12 @@ ESP32_COMPILER_PREFIX := xtensa-$(ESP_VARIANT)-elf
 else
 ESP32_COMPILER_PREFIX := riscv32-esp-elf
 IDF_TARGET_ARCH_RISCV := 1
+# This is important as no hardware FPU is available on these SOCs
+ifeq ($(IDF_VERSION),v5.2)
+ESP32_RISCV_ARCH := rv32imc_zicsr_zifencei
+else
+ESP32_RISCV_ARCH := rv32imc
+endif
 endif
 
 # $1 => Tool sub-path/name
@@ -153,7 +159,10 @@ export PROJECT_VER
 # Flags which control code generation and dependency generation, both for C and C++
 CPPFLAGS += -Wno-frame-address
 
-ifndef IDF_TARGET_ARCH_RISCV
+ifdef IDF_TARGET_ARCH_RISCV
+CPPFLAGS += \
+	-march=$(ESP32_RISCV_ARCH)
+else
 CPPFLAGS += \
 	-mlongcalls \
 	-mtext-section-literals