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simd_test.mdl
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CustomSymbolStrBlkIO "rtb_$N$M"
CustomSymbolStrTmpVar "$N$M"
CustomSymbolStrMacro "$R$N$M"
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
InsertPolySpaceComments off
SimulinkBlockComments on
MATLABSourceComments off
EnableCustomComments off
InternalIdentifier "Classic"
InlinedPrmAccess "Literals"
ReqsInCode off
UseSimReservedNames off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 17
Version "1.12.1"
Array {
Type "Cell"
Dimension 15
Cell "GeneratePreprocessorConditionals"
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "GenerateTestInterfaces"
Cell "ModelStepFunctionPrototypeControlCompliant"
Cell "CPPClassGenCompliant"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
}
TargetFcnLib "ansi_tfl_table_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
CodeReplacementLibrary "ANSI_C"
UtilityFuncGeneration "Auto"
ERTMultiwordTypeDef "System defined"
ERTMultiwordLength 256
MultiwordLength 2048
GenerateFullHeader on
GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
ParMdlRefBuildCompliant on
CompOptLevelCompliant on
ConcurrentExecutionCompliant on
IncludeMdlTerminateFcn on
GeneratePreprocessorConditionals "Disable all"
CombineOutputUpdateFcns on
CombineSignalStateStructs off
SuppressErrorStatus off
ERTFirstTimeCompliant off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
SupportVariableSizeSignals off
EnableShiftOperators on
ParenthesesLevel "Nominal"
ModelStepFunctionPrototypeControlCompliant off
CPPClassGenCompliant off
AutosarCompliant off
GRTInterface off
UseMalloc off
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
ExtModeIntrfLevel "Level1"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
RTWCAPIRootIO off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
CurrentDlgPage "Solver"
ConfigPrmDlgPosition [ 360, 135, 1240, 765 ]
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 7
}
Object {
$PropName "DataTransfer"
$ObjectID 18
$ClassName "Simulink.GlobalDataTransfer"
DefaultTransitionBetweenSyncTasks "Ensure deterministic transfer (maximum delay)"
DefaultTransitionBetweenAsyncTasks "Ensure data integrity only"
DefaultTransitionBetweenContTasks "Ensure deterministic transfer (minimum delay)"
DefaultExtrapolationMethodBetweenContTasks "None"
AutoInsertRateTranBlk [0]
}
ExplicitPartitioning off
BlockDefaults {
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
BlockRotation 0
BlockMirror off
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
MaskDefaults {
SelfModifiable "off"
IconFrame "on"
IconOpaque "on"
RunInitForIconRedraw "off"
IconRotate "none"
PortRotate "default"
IconUnits "autoscale"
}
MaskParameterDefaults {
Evaluate "on"
Tunable "on"
NeverSave "off"
Internal "off"
ReadOnly "off"
Enabled "on"
Visible "on"
ToolTip "on"
}
BlockParameterDefaults {
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
}
Block {
BlockType Inport
Port "1"
OutputFunctionCall off
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchInputForFeedbackSignals off
Interpolate on
}
Block {
BlockType Outport
Port "1"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
SignalType "auto"
SamplingMode "auto"
SourceOfInitialOutputValue "Dialog"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
CheckFcnCallInpInsideContextMsg off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
DataTypeOverrideAppliesTo "AllNumericTypes"
MinMaxOverflowLogging "UseLocalSettings"
SFBlockType "NONE"
Variant off
GeneratePreprocessorConditionals off
}
Block {
BlockType Terminator
}
}
System {
Name "simd_test"
Location [143, 111, 1556, 829]
Open on
ModelBrowserVisibility on
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
SIDHighWatermark "108"
Block {
BlockType Reference
Name " System Generator"
SID "1"
Tag "genX"
Ports []
Position [131, 28, 181, 78]
ZOrder 1
ShowName off
AttributesFormatString "System\\nGenerator"
LibraryVersion "1.2"
UserDataPersistent on
UserData "DataTag0"
SourceBlock "xbsIndex_r4/ System Generator"
SourceType "Xilinx System Generator Block"
infoedit " System Generator"
xilinxfamily "virtex6"
part "xc6vsx475t"
speed "-1"
package "ff1759"
synthesis_tool "XST"
clock_wrapper "Clock Enables"
directory "./ngc_netlist"
proj_type "Project Navigator"
Synth_file "XST Defaults"
Impl_file "ISE Defaults"
testbench off
simulink_period "1"
sysclk_period "10"
dcm_input_clock_period "10"
incr_netlist off
trim_vbits "Everywhere in SubSystem"
dbl_ovrd "According to Block Masks"
core_generation "According to Block Masks"
run_coregen off
deprecated_control off
eval_field "0"
has_advanced_control "0"
sggui_pos "326,241,464,470"
block_type "sysgen"
sg_icon_stat "50,50,0,0,token,white,0,58c5b5770fe5f7c311f53dbc6e73f0f6,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 50 50 0 0 ],[0 0 50 50 0 ],[1 1 1 ]"
");\npatch([1.6375 16.81 27.31 37.81 48.31 27.31 12.1375 1.6375 ],[36.655 36.655 47.155 36.655 47.155 47.155 47.1"
"55 36.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 27.31 16.81 1.6375 12.1375 ],[26.155 26.155 36.655 3"
"6.655 26.155 ],[0.698039 0.0313725 0.219608 ]);\npatch([1.6375 16.81 27.31 12.1375 1.6375 ],[15.655 15.655 26.15"
"5 26.155 15.655 ],[0.933333 0.203922 0.141176 ]);\npatch([12.1375 48.31 37.81 27.31 16.81 1.6375 12.1375 ],[5.15"
"5 5.155 15.655 5.155 15.655 15.655 5.155 ],[0.698039 0.0313725 0.219608 ]);\nfprintf('','COMMENT: end icon graph"
"ics');\nfprintf('','COMMENT: begin icon text');\nfprintf('','COMMENT: end icon text');"
}
Block {
BlockType Reference
Name "BitBasher"
SID "50"
Ports [4, 1]
Position [260, 226, 300, 304]
ZOrder 5274
ShowName off
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/BitBasher"
SourceType "Xilinx BitBasher Block"
infoedit "Allows extraction, concatenation and augmentation of bits"
bitexpr "<!DOCTYPE HTML PUBLIC \"-//W3C//DTD HTML 4.0//EN\" \"http://www.w3.org/TR/REC-html40/strict.dtd\""
">\n<html><head><meta name=\"qrichtext\" content=\"1\" /><style type=\"text/css\">\np, li { white-space: pre-wrap"
"; }\n</style></head><body style=\" font-family:'Sans'; font-size:10pt; font-weight:400; font-style:normal;\">\n<"
"p style=\" margin-top:12px; margin-bottom:12px; margin-left:0px; margin-right:0px; -qt-block-indent:0; text-inde"
"nt:0px;\"><span style=\" font-family:'MS Shell Dlg'; font-size:8pt;\">in={w,x,y,z}</span></p></body></html>"
display_expr off
sr_1 "1"
arith_type1 "Unsigned"
bin_pt1 "0"
sr_2 "2"
arith_type2 "Unsigned"
bin_pt2 "0"
sr_3 "3"
arith_type3 "Unsigned"
bin_pt3 "0"
sr_4 "4"
arith_type4 "Unsigned"
bin_pt4 "0"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "15,25,368,329"
block_type "bitbasher"
sg_icon_stat "40,78,4,1,white,blue,0,8e7ad5eb,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 40 40 0 0 ],[0 0 78 78 0 ],[0.77 0."
"82 0.91 ]);\nplot([0 40 40 0 0 ],[0 0 78 78 0 ]);\npatch([8.875 16.1 21.1 26.1 31.1 21.1 13.875 8.875 ],[44.55 4"
"4.55 49.55 44.55 49.55 49.55 49.55 44.55 ],[1 1 1 ]);\npatch([13.875 21.1 16.1 8.875 13.875 ],[39.55 39.55 44.55"
" 44.55 39.55 ],[0.931 0.946 0.973 ]);\npatch([8.875 16.1 21.1 13.875 8.875 ],[34.55 34.55 39.55 39.55 34.55 ],[1"
" 1 1 ]);\npatch([13.875 31.1 26.1 21.1 16.1 8.875 13.875 ],[29.55 29.55 34.55 29.55 34.55 34.55 29.55 ],[0.931 0"
".946 0.973 ]);\nfprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black"
"');port_label('input',1,'w');\ncolor('black');port_label('input',2,'x');\ncolor('black');port_label('input',3,'y"
"');\ncolor('black');port_label('input',4,'z');\ncolor('black');port_label('output',1,'in');\nfprintf('','COMMENT"
": end icon text');"
}
Block {
BlockType Reference
Name "Constant1"
SID "24"
Ports [0, 1]
Position [130, 228, 185, 242]
ZOrder 5256
ShowName off
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Constant"
SourceType "Xilinx Constant Block Block"
const "0"
gui_display_data_type "Fixed-point"
arith_type "Signed (2's comp)"
n_bits "4"
bin_pt "0"
preci_type "Single"
exp_width "8"
frac_width "24"
explicit_period on
period "1"
dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block."
equ "P=C"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "constant"
sg_icon_stat "55,14,0,1,white,blue,0,bf4ddd8b,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 14 14 0 ],[0.77 0."
"82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 14 14 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[9.2"
"2 9.22 11.22 9.22 11.22 11.22 11.22 9.22 ],[1 1 1 ]);\npatch([24.55 27.44 25.44 22.55 24.55 ],[7.22 7.22 9.22 9."
"22 7.22 ],[0.931 0.946 0.973 ]);\npatch([22.55 25.44 27.44 24.55 22.55 ],[5.22 5.22 7.22 7.22 5.22 ],[1 1 1 ]);\n"
"patch([24.55 31.44 29.44 27.44 25.44 22.55 24.55 ],[3.22 3.22 5.22 3.22 5.22 5.22 3.22 ],[0.931 0.946 0.973 ]);\n"
"fprintf('','COMMENT: end icon graphics');\nfprintf('','COMMENT: begin icon text');\ncolor('black');port_label('o"
"utput',1,'0');\nfprintf('','COMMENT: end icon text');"
}
Block {
BlockType Reference
Name "Constant2"
SID "108"
Ports [0, 1]
Position [130, 328, 185, 342]
ZOrder 5281
ShowName off
LibraryVersion "1.2"
SourceBlock "xbsIndex_r4/Constant"
SourceType "Xilinx Constant Block Block"
const "127"
gui_display_data_type "Fixed-point"
arith_type "Unsigned"
n_bits "8"
bin_pt "0"
preci_type "Single"
exp_width "8"
frac_width "24"
explicit_period on
period "1"
dsp48_infoedit "The use of this block for DSP48 instructions is deprecated. Please use the Opmode block."
equ "P=C"
opselect "C"
inp2 "PCIN>>17"
opr "+"
inp1 "P"
carry "CIN"
dbl_ovrd off
has_advanced_control "0"
sggui_pos "-1,-1,-1,-1"
block_type "constant"
sg_icon_stat "55,14,0,1,white,blue,0,a8544230,right,,[ ],[ ]"
sg_mask_display "fprintf('','COMMENT: begin icon graphics');\npatch([0 55 55 0 0 ],[0 0 14 14 0 ],[0.77 0."
"82 0.91 ]);\nplot([0 55 55 0 0 ],[0 0 14 14 0 ]);\npatch([22.55 25.44 27.44 29.44 31.44 27.44 24.55 22.55 ],[9.2"