In power electronics, pulse width modulation is a proven effective technique that is used to control semiconductor devices. Pulse width modulation or PWM is a commonly used control technique that generates analog signals from digital devices such as microcontrollers. The signal thus produced will have a train of pulses, and these pulses will be in the form of square waves. Thus, at any given time, the wave will either be high or low.
Pulse width modulation reduces the average power delivered by an electrical signal by converting the signal into discrete parts. In the PWM technique, the signal’s energy is distributed through a series of pulses rather than a continuously varying (analog) signal.
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A pulse width modulating signal is generated using a comparator. The modulating signal forms one part of the input to the comparator, while the non-sinusoidal wave or sawtooth wave forms the other part of the input. The comparator compares two signals and generates a PWM signal as its output waveform.
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If the sawtooth signal is more than the modulating signal, then the output signal is in a “High” state. The value of the magnitude determines the comparator output which defines the width of the pulse generated at the output.
- As we know, a PWM signal stays ON for a given time and stays OFF for a certain time. The percentage of time for which the signal remains ON is known as the duty cycle. If the signal is always ON, then the signal must have a 100 % duty cycle. The formula to calculate the duty cycle is given as follows:
- The average value of the voltage depends on the duty cycle. As a result, the average value can be varied by controlling the width of the ON of a pulse.
- This PWM generator generates 10Mhz signal. We can control duty cycles in steps of 10%. The default duty cycle is 50%. Along with clock signal we provide another two external signals to increase and decrease the duty cycle.
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The key components we need for this particular circuit are an n-bit counter and comparator. The duty passed to the comparator is compared to the counter's current value. If the counter's current value is less than the required value, the comparator produces a high output. Similar to this, if the counter's current value is higher than its duty, the comparator's output will be low. Since the counter starts at zero, the comparator initially produces a large output, which decreases as the counter approaches its duty. Therefore, we can manage duty cycle by managing duty.
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Since the counter is sequential and the comparator is a combinational circuit, there may be an intermediate state like 111 that is higher or lower than duty when counting from 011 to 100 as a result of inappropriate delays. A glitch might result from this. The output of the comparator is routed through a D flipflop in order to prevent these errors.
- It prevents overheating of LED while maintaining its brightness.
- It is accurate and has a fast response time.
- It provides a high input power factor.
- It helps motors generate maximum torque even when they run at lower speeds.
- As the PWM frequency is high, switching losses are considerably high.
- It induces Radio Frequency Interference (RFI).
- Used in telecommunication for encoding purposes.
- Helps in voltage regulation and therefore is used to control the speed of motors.
- Controls the fan inside a CPU of the computer, thereby successfully dissipating the heat.
- Used in Audio/Video Amplifiers.
For installation and more details regarding iverilog, yosys and gtkwave, refer to :
https://github.com/Syedhasan7/pes_asic_class
iverilog pes_pwm.v pes_pwm_tb.v./a.outgtkwave pwm.vcd
- Invoke
yosys read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.libread_verilog pes_pwm.vsynth -top pes_pwmdfflibmap -liberty lib/sky130_fd_sc_hd__tt_025C_1v80.libabc -liberty lib/sky130_fd_sc_hd__tt_025C_1v80.libflattenwrite_verilog pes_pwm_netlist.vshow pes_pwm
iverilog ../my_lib/verilog_model/primitives.v ../my_lib/verilog_model/sky130_fd_sc_hd.v pes_pwm_netlist.v pes_pwm_tb.v./a.outgtkwave pwm.vcd
We can observe that output of functional simulation is matching with the output of gate level simulation, this means that the netlist generated by yosys is correct.
We can observe that output of functional simulation is matching with the output of gate level simulation, this means that the netlist generated by yosys is correct.
Physical design is process of transforming netlist into layout which is manufacture-able [GDS]. Physical design process is often referred as PnR (Place and Route). Main steps in physical design are placement of all logical cells, clock tree synthesis & routing. During this process of physical design timing, power, design & technology constraints have to be met. Further design might require being optimized w.r.t power, performance and area.
OpenLANE is an opensource tool or flow used for opensource tape-outs. The OpenLANE flow comprises a variety of tools such as Yosys, ABC, OpenSTA, Fault, OpenROAD app, Netgen and Magic which are used to harden chips and macros, i.e. generate final GDSII from the design RTL. The primary goal of OpenLANE is to produce clean GDSII with no human intervention. OpenLANE has been tuned to function for the Google-Skywater130 Opensource Process Design Kit.
https://openlane.readthedocs.io/en/latest/
- Navigate to the openlane folder and run the following commands:
$ cd designs
$ mkdir pes_pwm
$ cd pes_pwm
$ mkdir src
$ vim config.tcl
$ cd src
$ vim pes_pwm.v
- Include
sky130_fd_sc_hd__fast.lib,sky130_fd_sc_hd__slow.lib,sky130_fd_sc_hd__typical.libinto thesrcfolder. - The contents of
srcfolder is shown below:
- The contents of
config.tclis shown below:
- Navigate to the openlane folder in terminal:
$ make mount
$ ./flow.tcl -interactive
- In the tcl console:
% package require openlane 0.9
% prep -design pes_pwm
% run_synthesis
- Synthesis results
- Flop ratio:
Flop ratio = Number of D Flip flops / Total number of cells - Flop ratio for my design is 0.3125
In the VLSI physical design, floorplanning is an essential design step, as it determines the size, shape, and locations of modules in a chip and as such it estimates the total chip area, the interconnects, and, delay.
% run_floorplan
- Floorplan results
Core Area
Die Area
- Post the floorplan run, a .def file will have been created within the results/floorplan directory.
- Navigate to that directory and open in terminal and type:
magic -T /home/syedhasan/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.lef def read pes_pwm.floorplan.def &
- Floorplan View
Placement is the process of placing the standard cells inside the core boundary in an optimal location.
% run_placement
- Post the placement run, a .def file will have been created within the results/placement directory.
- Navigate to that directory and open in terminal and type:
magic -T /home/syedhasan/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.lef def read pes_pwm.placement.def &
- Placement View
Clock Tree Synthesis is a technique for distributing the clock equally among all sequential parts of a VLSI design. The purpose of Clock Tree Synthesis is to reduce skew and delay. Clock Tree Synthesis is provided the placement data as well as the clock tree limitations as input.
% run_cts
Implements the interconnect system between standard cells using the remaining available metal layers after CTS and PDN generation. The routing is performed on routing grids to ensure minimal DRC errors.
% run_routing
- Post the routing run, a .def file will have been created within the results/routing directory.
- Navigate to that directory and open in terminal and type:
magic -T /home/syedhasan/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech read lef ../../tmp/merged.lef def read pes_pwm.def &
- Area Report
- Here we are generating the layout in the non-interactive mode or the automatic mode. In this we cant interact with the flow in the middle of each stage of the flow.The flow completes all the stages starting from synthesis until you obtain the final layout and the reports of various stages which specify the violations and problems if present during the flow.
- Navigate to the openlane folder:
$ make mount
$ ./flow.tcl -design pes_pwm -tag RUN
- All the steps will be automated and all the files will be generated.
- After running all the steps, the flow complete message will appear as shown below:
- Number of cells = 128
- Area = 4723.994 um^2
- Performance = 1/(clock period-slack) = 1/(10-1.13)ps = 112.74GHz
- Flop ratio = 40/128 = 0.3125