Investigate FPGA interchange BEL validity checking improvements

[litghost]

The current FPGA interchange BEL validity checks are slow and have some potential robustness issues. The robustness issues will hopefully be flushed out once #234 is stood up and test cases are added. This issue primarily is covering the performance issues in the current BEL validity checks.

Current status

The BEL validity checks (isBelLocationValid) implement the following checks:

• Constraint testing (here)
• Fabric specific connection wiring (in DedicatedInterconnect)
• Site routing (in SiteRouter)
• LUT equation checking (in LutMapper)

This covers most of the validity checks required for doing P&R on 7-series fabrics, but further testing is required to ensure that the current set of implementations is complete enough to implement the 7-series placement rules (see #234).

Current problems

The performance of the BEL validity checks is fairly poor. For example, Murax HeAP time is currently:

Info: HeAP Placer Time: 87.79s                                                                                                               
Info:   of which solving equations: 1.62s                                                                                                    
Info:   of which spreading cells: 0.57s                                                                                                      
Info:   of which strict legalisation: 83.49s 

Approximately 40% of the 83 seconds spent in strict legalisation is solely in the LUT equation handling. There is also significant wasted time in the cell BEL pin mapping logic that should be fixable.

Potential solutions

• The current cell BEL pin cache check doesn't properly detect when cells are placed on a different BEL with a site, but otherwise has the same pin mapping. See here. (cell->cell_mapping != mapping) is basically a cache hit detection, and the mapping index is BEL specific within a site, rather than mapping specific. As a result, time is being spent re-mapping Cell to BEL pins even though the mapping will be identical
• The LUT equation logic is currently taking 40% of the strict legalization time. This seems too high. Consider rewriting after testing from Need site routing test framework #234 is in place. Expectation is that a better chip-db pre-compute or caching should enable LUT equation logic code to be faster and simpler.
• Profile more placements of circuits (e.g. run with --no-route) and see if other parts of the strict legalization check can be improved.