From ab89e917d8ead1697b904c9710a1471c738fb5ab Mon Sep 17 00:00:00 2001
From: Lalit Narain Sharma <61820431+lnsharma@users.noreply.github.com>
Date: Tue, 2 Mar 2021 15:27:56 +0530
Subject: [PATCH] Incorporating review comment on using common logic.v

---
 tests/arch/quicklogic/logic.ys  |  2 +-
 tests/arch/quicklogic/v/logic.v | 16 ----------------
 2 files changed, 1 insertion(+), 17 deletions(-)
 delete mode 100644 tests/arch/quicklogic/v/logic.v

diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys
index c6534d2e175..ae40af153b1 100644
--- a/tests/arch/quicklogic/logic.ys
+++ b/tests/arch/quicklogic/logic.ys
@@ -1,4 +1,4 @@
-read_verilog v/logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/quicklogic/qlf_k4n8_cells_sim.v synth_quicklogic
diff --git a/tests/arch/quicklogic/v/logic.v b/tests/arch/quicklogic/v/logic.v
deleted file mode 100644
index 62a2aa02772..00000000000
--- a/tests/arch/quicklogic/v/logic.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module top
-(
-    input  I0,I1,I2,I3,
-    output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
-);
-    assign B1 =   I0 &  I1;
-    assign B2 =   I0 |  I1;
-    assign B3 =   I0 ~& I1;
-    assign B4 =   I0 ~| I1;
-    assign B5 =   I0 ^  I1;
-    assign B6 =   I0 ~^ I1;
-    assign B7 =  ~I0;
-    assign B8 =   I0;
-    assign B9 =   {I1,I0} && {I3,I3};
-    assign B10 =  {I1,I0} || {I3,I2};
-endmodule