[FEATURE] Creation of automated CSR test for RISC-V, based on RDL register definition

[chili-chips-ba]

Given that PeakRDL already outputs UVM register views, which are typically used for automation of CSR test sequences, what it make sense to also automatically generate a 'C' program for execution of those test from an on-chip CPU?!

The same question is posed here, as our project is writing own post-processing script for adaptation of PeakRDL register structures to our RISC-V ISS, as well as avoidance of expensive Read-Modify-Write sequences.