JSON --> RDL conversion and regfile registers overlapping after elaboration

[anjpar]

Hello, heads up/apologies for a long issue. I have a script that converts register definition in JSON format to RDL format. I updated the script to support multireg, parameters and named groups of registers. I see that on elaboration, regfile registers are overlapping. I don't see the overlap issue in my debug prints, however. Essentially, every multireg block seems to be allocated more address space that required. Please let me know if I am missing something in the script that is causing this behavior.

#!/usr/bin/env python3

import json
import re

from systemrdl import RDLListener
from systemrdl import component as comp
from systemrdl.importer import RDLImporter
from systemrdl.node import FieldNode
from systemrdl.rdltypes import AccessType
from systemrdl.rdltypes import OnReadType
from systemrdl.rdltypes import OnWriteType


class JsonImporter(RDLImporter):

  def __init__(self, rdlc):
    super().__init__(rdlc)  # Initialize the parent class if necessary
    self.param_dict = dict()

  def update_param_dict(self, key, value):
    # Update dictionary value for a given key
    self.param_dict[key] = value
  
  def get_param_value(self, key):
    # Retrieve the value for a given key
    return self.param_dict.get(key, "Key not found")
  
  def key_exists(self, key):
    # Check if the key is present in the dictionary
    return key in self.param_dict

  def import_file(self, path: str) -> None:
    super().import_file(path)

    # Load the JSON from a file and convert it to primitive Python objects
    with open(path, 'r', encoding='utf-8') as f:
      json_obj = json.load(f)

    # Decode param_list as this is used by decode_field
    if 'param_list' in json_obj:
      self.decode_param_list(json_obj['param_list'])

    # Decode the JSON object
    # Set is_top=True so that decode returns a definition rather than an instance
    top_addrmap_def = self.decode_addrmap(json_obj, is_top=True)

    # Register the top definition in the root namespace
    self.register_root_component(top_addrmap_def)

  def decode_param_list(self, json_obj):
    #print(json_obj)
    for param in json_obj:
      self.decode_param(param)
    #DEbug
    print(self.param_dict)
      
  def decode_param(self, param_obj):
    #print(param_obj)
    if 'name' not in param_obj:
      self.msg.fatal(
        "'name' not found in '%s'" % param_obj, self.default_src_ref
      )
    if 'default' not in param_obj:
      self.msg.info(
        "'default' not found in '%s'" % param_obj
      )
      return "Skipping %s as it does not have a default value" % param_obj['name']
    self.update_param_dict(param_obj['name'], param_obj['default'])


  def parse_digits(self, digits):
    # return lsb, msb for a given string input
    # Have: 4:3
    # Want: msb = 4, lsb = 3
    # Have: 4
    # Want: msb = 4, lsb = 3

    msb = digits
    lsb = digits
    msb_temp1 = digits
    msb_temp2 = digits
    if ':' in digits:
      pattern1 = re.compile(r'(\d+):(\d+)')
      pattern2 = re.compile(r'(\w+)-(1):(0)')
      match1 = pattern1.match(digits)
      match2 = pattern2.match(digits)
      if match1:
        msb = match1.group(1)
        lsb = match1.group(2)
      elif match2:
        msb_temp1 = match2.group(1)
        msb_temp2 = match2.group(2)
        lsb = match2.group(3)
        msb = int(self.get_param_value(msb_temp1)) - int(msb_temp2)
      else:
        self.msg.fatal(
            "invalid bits found in '%s'" % bits, self.default_src_ref
        )

    return msb, lsb

  def decode_field(self, reg_obj, field_obj: dict) -> comp.Field:
    #print("***************************************DEBUG: IN decode_field*************")
    #print(reg_obj)
    #print(field_obj)
    # Apply parent name if it is not set
    name = reg_obj['name']
    if 'name' in field_obj:
      name = field_obj['name']

    # validate that this json object contains all the required fields
    if 'bits' not in field_obj:
      self.msg.fatal(
          "'%s' object is missing 'bits'" % name, self.default_src_ref
      )
    if 'desc' not in field_obj:
      field_obj['desc'] = reg_obj['desc']

    # Create an RDL field definition
    comp_def = self.create_field_definition()

    msb, lsb = self.parse_digits(field_obj['bits'])

    # Apply reset property if it was set
    if 'resval' in field_obj:
      resval = str(field_obj['resval'])
      if 'False' in resval:
        resval = 9
      elif 'True' in resval:
        resval = 6
      else:
        resval = int(resval, 16)
      self.assign_property(comp_def, 'reset', resval)

    self.assign_property(comp_def, 'desc', field_obj['desc'])

    # decode and apply the sw access property.
    # All fields in a register have the same access type
    access_type = reg_obj['swaccess']
    if access_type == 'rw0c':
      self.assign_property(comp_def, 'sw', AccessType['rw'])
      self.assign_property(comp_def, 'onwrite', OnWriteType['wzc'])
    if access_type == 'rw0c':
      self.assign_property(comp_def, 'sw', AccessType['rw'])
      self.assign_property(comp_def, 'onwrite', OnWriteType['woclr'])
    elif access_type == 'rw':
      self.assign_property(comp_def, 'sw', AccessType['rw'])
    elif access_type == 'ro':
      self.assign_property(comp_def, 'sw', AccessType['r'])
    elif access_type == 'wo':
      self.assign_property(comp_def, 'sw', AccessType['w'])
    elif access_type == 'r0w1c':
      self.assign_property(comp_def, 'sw', AccessType['rw'])
      self.assign_property(comp_def, 'onwrite', OnWriteType['woclr'])
    else:
      self.msg.fatal(
          'Undefined access_type: %s' % access_type, self.default_src_ref
      )

    # Instantiate the component definition
    inst = self.instantiate_field(
        comp_def, name, int(lsb), int(msb) - int(lsb) + 1
    )
    return inst
  
  def decode_multireg(self, multireg_obj: dict, addr: int) -> tuple[comp.Regfile, int]:
    #print(multireg_obj, addr)
    #print(multireg_obj['multireg'])  
    start_addr = addr  
    print("DEBUG: MULTIREG")
    print(f"Address offset = {start_addr:X}")

    if 'name' not in multireg_obj['multireg']:
      self.msg.fatal("JSON 'multireg' object is missing 'name'", self.default_src_ref)
    if 'desc' not in multireg_obj['multireg']:
      self.msg.fatal("JSON 'multireg' object is missing 'desc", self.default_src_ref)
    if 'swaccess' not in multireg_obj['multireg']:
      self.msg.fatal("JSON 'multireg' object is missing 'swaccess'", self.default_src_ref)
    if 'hwaccess' not in multireg_obj['multireg']:
      self.msg.fatal("JSON 'multireg' object is missing 'hwaccess'", self.default_src_ref)
    if 'fields' not in multireg_obj['multireg']:
      self.msg.fatal("JSON 'multireg' object is missing 'fields'", self.default_src_ref)
    if 'count' not in multireg_obj['multireg']:
      self.msg.fatal("JSON 'multireg' object is missing 'count'", self.default_src_ref)

    comp_def = self.create_regfile_definition()

    # Collect children
    if self.key_exists(multireg_obj['multireg']['count']):
      num_multireg = int(self.get_param_value(multireg_obj['multireg']['count']))
    else:
      num_multireg = int(multireg_obj['multireg']['count'])

    for num in range(num_multireg):
      # Convert each child componenet and add it to our regfile definition
      child_inst = self.decode_reg(multireg_obj['multireg'], addr, num)
      addr += 4
      #print(child_inst)

      # Add the child component to this
      self.add_child(comp_def, child_inst)

    inst = self.instantiate_regfile(comp_def=comp_def,
                                     inst_name=multireg_obj['multireg']['name'], 
                                     addr_offset=start_addr) 
    
    print(f"Instance name: {inst.inst_name}")
    print(f"Array Stride: {inst.array_stride}")
    print(f"Addr Offset: 0x{inst.addr_offset:X}")
    print(f"Is Array: {inst.is_array}")
    print(f"Num Array Elements: {inst.n_elements}")


    #print(inst)
    return inst, num_multireg

  def decode_reg(self, reg_obj: dict, addr: int, num_reg:int=None) -> comp.Reg:
    # validate that this json object contains all the required fields
    if 'name' not in reg_obj:
      self.msg.fatal("JSON object is missing 'name'", self.default_src_ref)
    if 'desc' not in reg_obj:
      self.msg.fatal(
          "'%s' is missing 'desc'", reg_obj['name'], self.default_src_ref
      )
    if 'swaccess' not in reg_obj:
      print(self.default_src_ref)
      print(reg_obj['name'], self.default_src_ref)
      self.msg.fatal(
          "'%s' is missing 'swaccess'", reg_obj['name'], self.default_src_ref
      )
    if 'hwaccess' not in reg_obj:
      self.msg.fatal(
          "'%s' is missing 'hwaccess'", reg_obj['name'], self.default_src_ref
      )
    if 'fields' not in reg_obj:
      self.msg.fatal(
          "'%s' is missing 'fields'", reg_obj['name'], self.default_src_ref
      )

    comp_def = self.create_reg_definition()

    # Collect children
    for field in reg_obj['fields']:
      # Convert each child component and add it to our reg definition
      child_inst = self.decode_field(reg_obj, field)
      self.add_child(comp_def, child_inst)

    # Convert the definition into an instance
    if num_reg is not None:
      inst = self.instantiate_reg(comp_def, f"{reg_obj['name']}_{num_reg}", addr)
      #Debug
      print(f"Register: {reg_obj['name']}_{num_reg}\t\tAddress: 0x{addr:X}")
    else:
      inst = self.instantiate_reg(comp_def, reg_obj['name'], addr)
      #Debug
      print(f"Register: {reg_obj['name']}\t\tAddress: 0x{addr:X}")
    return inst

  def decode_addrmap(
      self, json_obj: dict, is_top: bool = False
  ) -> comp.Addrmap:
    # validate that this json object contains all the required fields
    if 'name' not in json_obj:
      self.msg.fatal("JSON object is missing 'name'", self.default_src_ref)
    if 'registers' not in json_obj:
      self.msg.fatal(
          "'%s' is missing 'registers'" % json_obj['name'], self.default_src_ref
      )

    if is_top:
      # if this is the top node, then instantiation is skipped, and the
      # definition inherits the inst name as its type name

      # For everything else, convert the definition into an instance
      comp_def = self.create_addrmap_definition(json_obj['name'])
    else:
      # otherwise, create an anonymous definition
      comp_def = self.create_addrmap_definition()

    addr = 0
    for index in range(4):
      child_inst = self.add_common_reg(json_obj, index * 4)
      self.add_child(comp_def, child_inst)
      addr += 4
      print(f"Next Address coming up: 0x{addr:X} ")

    # Collect child registers
    if (reg_groups == True):
      for reg_group_name in args.group_names:
        print("Number of registers is ", len(json_obj['registers'][reg_group_name]))
        print (reg_group_name)
        for reg_no in range(len(json_obj['registers'][reg_group_name])):
          if ('multireg' in json_obj['registers'][reg_group_name][reg_no]):
            print(f"In decode_addrmap, calling decode_multireg. Addr = 0x{addr:X}")
            child_inst, num_multireg = self.decode_multireg(json_obj['registers'][reg_group_name][reg_no], addr)
            addr += (4 * num_multireg)
            # Add the child component to this
            self.add_child(comp_def, child_inst)
          else:
            child_inst = self.decode_reg(json_obj['registers'][reg_group_name][reg_no], addr)
            addr += 4
            # Add the child component to this
            self.add_child(comp_def, child_inst)
          print(f"Next Address coming up: 0x{addr:X} ")
    else:
      for register in json_obj['registers']:
        if ('multireg' in json_obj['registers'][reg_group_name][reg_no]):
          child_inst, num_multireg = self.decode_multireg(json_obj['registers'][reg_group_name][reg_no], addr)
          addr += (4 * num_multireg)
          # Add the child component to this
          self.add_child(comp_def, child_inst)
        else:
          child_inst = self.decode_reg(register, addr)
          addr += 4
          # Add the child component to this
          self.add_child(comp_def, child_inst)
        print(f"Next Address coming up: 0x{addr:X} ")

    if is_top:
      # keep top-level addrmap as a definition. Skip instantiation
      return comp_def

    inst = self.instantiate_addrmap(
        comp_def, addrmap_name, json_obj['addr_offset']
    )
    return inst

  def add_common_reg(self, reg_obj: dict, addr: int) -> comp.Reg:
    # OpenTitan defines interrupts and alerts in the 'interrupt_list'
    # and 'alert_list'properties in the json. 
    # parameters are defined in 'param_list' (optional)
    # register definitions.
    # 0x0 - Interrupt State Register
    # 0x4 - Interrupt Enable Register
    # 0x8 - Interrupt Test Register
    # 0xC - Alert Test Register

    # validate that this json object contains all the required fields
    if 'interrupt_list' not in reg_obj:
      self.msg.fatal(
          "JSON object is missing 'interrupt_list'", self.default_src_ref
      )
    if 'alert_list' not in reg_obj:
      self.msg.fatal(
          "JSON object is missing 'alert_list'", self.default_src_ref
      )
    #if 'param_list' not in reg_obj:
    #  self.msg.fatal(
    #      "JSON object is missing 'param_list'", self.default_src_ref
    #  )
    

    comp_def = self.create_reg_definition()

    if addr == 0x0:
      reg_name = 'interrupt_state'
    elif addr == 0x4:
      reg_name = 'interrupt_enable'
    elif addr == 0x8:
      reg_name = 'interrupt_test'
    elif addr == 0xC:
      reg_name = 'alert_test'
    else:
      self.msg.fatal(
          'addr: %d is not supported in add_common_reg ' % addr,
          self.default_src_ref,
      )
    # Collect children
    fields = reg_obj['interrupt_list']
    if addr == 0xC:
      fields = reg_obj['alert_list']
    
    for index, field in enumerate(fields):
      if 'name' not in field:
        self.msg.fatal("field object is missing 'name'", self.default_src_ref)
      if 'desc' not in field:
        self.msg.fatal(
            "'%s' object is missing 'desc'" % name, self.default_src_ref
        )

      field_def = self.create_field_definition()

      field_name = field['name']
      field_desc = field['desc']

      if addr == 0x0:
        self.assign_property(field_def, 'sw', AccessType['rw'])
        self.assign_property(field_def, 'onwrite', OnWriteType['woclr'])
      elif addr == 0x4:
        field_desc = 'Enable interrupt when %s is set.' % field_name
        self.assign_property(field_def, 'sw', AccessType['rw'])
        self.assign_property(field_def, 'onwrite', OnWriteType['woclr'])
      elif addr == 0x8:
        field_desc = 'Write 1 to force %s to 1.' % field_name
        self.assign_property(field_def, 'sw', AccessType['w'])
      elif addr == 0xC:
        field_desc = 'Write 1 to trigger one alert event of this kind.'
        self.assign_property(field_def, 'sw', AccessType['w'])

      self.assign_property(field_def, 'desc', field_desc)

      # Instantiate the component definition
      bit_offset = index
      bit_width = 1
      field_inst = self.instantiate_field(
          field_def, field_name.upper(), bit_offset, bit_width
      )

      # Convert each child component and add it to our reg definition
      self.add_child(comp_def, field_inst)

    # Convert the definition into an instance
    inst = self.instantiate_reg(comp_def, reg_name.upper(), addr)

    print(f"Register: {reg_name.upper()}\t\tAddress: 0x{addr:X}")

    return inst


# -------------------------------------------------------------------------------


# Define a listener that will print out the register model hierarchy
class MyModelPrintingListener(RDLListener):

  def __init__(self):
    self.indent = 0

  def enter_Component(self, node):
    if not isinstance(node, FieldNode):
      print('\t' * self.indent, node.get_path_segment())
      self.indent += 1

  def enter_Field(self, node):
    # Print some stuff about the field
    bit_range_str = '[%d:%d]' % (node.high, node.low)
    sw_access_str = 'sw=%s' % node.get_property('sw').name
    print(
        '\t' * self.indent,
        bit_range_str,
        node.get_path_segment(),
        sw_access_str,
    )

  def exit_Component(self, node):
    if not isinstance(node, FieldNode):
      self.indent -= 1


# -------------------------------------------------------------------------------

if __name__ == '__main__':
  import sys
  import os
  import argparse

  from systemrdl import RDLCompiler, RDLCompileError, RDLWalker
  from systemrdl.messages import FileSourceRef
  from peakrdl_systemrdl import SystemRDLExporter

  # Create a compiler session, and an importer attached to it
  rdlc = RDLCompiler()
  json_importer = JsonImporter(rdlc)

  # import each JSON file provided from the command line
  # Create the parser
  parser = argparse.ArgumentParser(description='Process some input files.')

  # Add a named parameter for input files
  parser.add_argument('--files', nargs='+', help='List of input files', required=True)

  # Add a boolean argument to indicate register groups
  parser.add_argument('--reg-groups', action='store_true', help='Enable verbose output')

  # Add a named parameter for reg groups
  parser.add_argument('--group-names', nargs='+', help='List of register group names', required=False)

  # Add a boolean argument to indicate multireg
  parser.add_argument('--multireg', action='store_true', help='Multireg present')

  # Parse the arguments
  args = parser.parse_args()

  # Check if reg-groups is True and group-names are not provided
  if args.reg_groups and args.group_names is None:
    parser.error("The --group-names parameter is required when --reg-groups is enabled.")

  reg_groups = args.reg_groups

  try:
    for input_file in args.files:
      print(input_file)
      # compile or import based on the file extension
      ext = os.path.splitext(input_file)[1]
      if ext == '.rdl':
        rdlc.compile_file(input_file)
      elif ext == '.json':
        json_importer.import_file(input_file)
      else:
        rdlc.msg.fatal(
            'Unknown file extension: %s' % ext, FileSourceRef(input_file)
        )
    # Elaborate when done
    root = rdlc.elaborate()
  except RDLCompileError as  e:
    print(f"Compilation or elaboration error: {e}")
    sys.exit(1)

  # Export SystemRDL
  print(sys.argv[1])
  #rdl_output_dir = os.path.abspath(os.path.dirname(sys.argv[1]))
  #rdl_output_file = os.path.splitext(os.path.basename(sys.argv[1]))[0] + '.rdl'
  rdl_output_dir = os.path.abspath(os.path.dirname(args.files[0]))
  rdl_output_file = os.path.splitext(os.path.basename(args.files[0]))[0] + '.rdl'
  exporter = SystemRDLExporter()
  exporter.export(root, os.path.join(rdl_output_dir, rdl_output_file))

  # Display the imported model
  walker = RDLWalker()
  listener = MyModelPrintingListener()
  walker.walk(root, listener)

Here is debug output listing the registers and addresses:

otp_ctrl.json
{'MemInitFile': '""', 'NumSramKeyReqSlots': '4', 'OtpByteAddrWidth': '12', 'NumErrorEntries': '9', 'NumDaiWords': '2', 'NumDigestWords': '2', 'NumSwCfgWindowWords': '1024', 'NumPart': '7', 'NumPartUnbuf': '2', 'NumPartBuf': '5', 'VendorTestOffset': '0', 'VendorTestSize': '64', 'ScratchOffset': '0', 'ScratchSize': '56', 'VendorTestDigestOffset': '56', 'VendorTestDigestSize': '8', 'NonSecretFusesOffset': '64', 'NonSecretFusesSize': '3736', 'FmcKeyManifestSvnOffset': '64', 'FmcKeyManifestSvnSize': '4', 'RuntimeSvnOffset': '68', 'RuntimeSvnSize': '16', 'LmsVerifyOffset': '84', 'LmsVerifySize': '4', 'LmsRevocationOffset': '88', 'LmsRevocationSize': '4', 'KeyManifestPkHashMaskOffset': '92', 'KeyManifestPkHashMaskSize': '4', 'OwnerPkHashOffset': '96', 'OwnerPkHashSize': '48', 'IdevidCertAttrOffset': '144', 'IdevidCertAttrSize': '96', 'IdevidManufHsmIdOffset': '240', 'IdevidManufHsmIdSize': '16', 'SocSteppingIdOffset': '256', 'SocSteppingIdSize': '4', 'NonSecretFusesDigestOffset': '3792', 'NonSecretFusesDigestSize': '8', 'Secret0Offset': '3800', 'Secret0Size': '40', 'TestUnlockTokenOffset': '3800', 'TestUnlockTokenSize': '16', 'TestExitTokenOffset': '3816', 'TestExitTokenSize': '16', 'Secret0DigestOffset': '3832', 'Secret0DigestSize': '8', 'Secret1Offset': '3840', 'Secret1Size': '56', 'UdsSeedOffset': '3840', 'UdsSeedSize': '48', 'Secret1DigestOffset': '3888', 'Secret1DigestSize': '8', 'Secret2Offset': '3896', 'Secret2Size': '40', 'FieldEntropyOffset': '3896', 'FieldEntropySize': '32', 'Secret2DigestOffset': '3928', 'Secret2DigestSize': '8', 'Secret3Offset': '3936', 'Secret3Size': '72', 'KeyManifestPkHashOffset': '3936', 'KeyManifestPkHashSize': '48', 'RmaTokenOffset': '3984', 'RmaTokenSize': '16', 'Secret3DigestOffset': '4000', 'Secret3DigestSize': '8', 'LifeCycleOffset': '4008', 'LifeCycleSize': '88', 'LcTransitionCntOffset': '4008', 'LcTransitionCntSize': '48', 'LcStateOffset': '4056', 'LcStateSize': '40'}
Register: INTERRUPT_STATE Address: 0x0
Next Address coming up: 0x4
Register: INTERRUPT_ENABLE Address: 0x4
Next Address coming up: 0x8
Register: INTERRUPT_TEST Address: 0x8
Next Address coming up: 0xC
Register: ALERT_TEST Address: 0xC
Next Address coming up: 0x10
Number of registers is 21
core
Register: STATUS Address: 0x10
Next Address coming up: 0x14
In decode_addrmap, calling decode_multireg. Addr = 0x14
DEBUG: MULTIREG
Address offset = 14
Register: ERR_CODE_0 Address: 0x14
Register: ERR_CODE_1 Address: 0x18
Register: ERR_CODE_2 Address: 0x1C
Register: ERR_CODE_3 Address: 0x20
Register: ERR_CODE_4 Address: 0x24
Register: ERR_CODE_5 Address: 0x28
Register: ERR_CODE_6 Address: 0x2C
Register: ERR_CODE_7 Address: 0x30
Register: ERR_CODE_8 Address: 0x34
Instance name: ERR_CODE
Array Stride: None
Addr Offset: 0x14
Is Array: False
Num Array Elements: 1
Next Address coming up: 0x38
Register: DIRECT_ACCESS_REGWEN Address: 0x38
Next Address coming up: 0x3C
Register: DIRECT_ACCESS_CMD Address: 0x3C
Next Address coming up: 0x40
Register: DIRECT_ACCESS_ADDRESS Address: 0x40
Next Address coming up: 0x44
In decode_addrmap, calling decode_multireg. Addr = 0x44
DEBUG: MULTIREG
Address offset = 44
Register: DIRECT_ACCESS_WDATA_0 Address: 0x44
Register: DIRECT_ACCESS_WDATA_1 Address: 0x48
Instance name: DIRECT_ACCESS_WDATA
Array Stride: None
Addr Offset: 0x44
Is Array: False
Num Array Elements: 1
Next Address coming up: 0x4C
In decode_addrmap, calling decode_multireg. Addr = 0x4C
DEBUG: MULTIREG
Address offset = 4C
Register: DIRECT_ACCESS_RDATA_0 Address: 0x4C
Register: DIRECT_ACCESS_RDATA_1 Address: 0x50
Instance name: DIRECT_ACCESS_RDATA
Array Stride: None
Addr Offset: 0x4C
Is Array: False
Num Array Elements: 1
Next Address coming up: 0x54
Register: CHECK_TRIGGER_REGWEN Address: 0x54
Next Address coming up: 0x58
Register: CHECK_TRIGGER Address: 0x58
Next Address coming up: 0x5C
Register: CHECK_REGWEN Address: 0x5C
Next Address coming up: 0x60
Register: CHECK_TIMEOUT Address: 0x60
Next Address coming up: 0x64
Register: INTEGRITY_CHECK_PERIOD Address: 0x64
Next Address coming up: 0x68
Register: CONSISTENCY_CHECK_PERIOD Address: 0x68
Next Address coming up: 0x6C
Register: VENDOR_TEST_READ_LOCK Address: 0x6C
Next Address coming up: 0x70
Register: NON_SECRET_FUSES_READ_LOCK Address: 0x70
Next Address coming up: 0x74
In decode_addrmap, calling decode_multireg. Addr = 0x74
DEBUG: MULTIREG
Address offset = 74
Register: VENDOR_TEST_DIGEST_0 Address: 0x74
Register: VENDOR_TEST_DIGEST_1 Address: 0x78
Instance name: VENDOR_TEST_DIGEST
Array Stride: None
Addr Offset: 0x74
Is Array: False
Num Array Elements: 1
Next Address coming up: 0x7C
In decode_addrmap, calling decode_multireg. Addr = 0x7C
DEBUG: MULTIREG
Address offset = 7C
Register: NON_SECRET_FUSES_DIGEST_0 Address: 0x7C
Register: NON_SECRET_FUSES_DIGEST_1 Address: 0x80
Instance name: NON_SECRET_FUSES_DIGEST
Array Stride: None
Addr Offset: 0x7C
Is Array: False
Num Array Elements: 1
Next Address coming up: 0x84
In decode_addrmap, calling decode_multireg. Addr = 0x84
DEBUG: MULTIREG
Address offset = 84
Register: SECRET0_DIGEST_0 Address: 0x84
Register: SECRET0_DIGEST_1 Address: 0x88
Instance name: SECRET0_DIGEST
Array Stride: None
Addr Offset: 0x84
Is Array: False
Num Array Elements: 1
Next Address coming up: 0x8C
In decode_addrmap, calling decode_multireg. Addr = 0x8C
DEBUG: MULTIREG
Address offset = 8C
Register: SECRET1_DIGEST_0 Address: 0x8C
Register: SECRET1_DIGEST_1 Address: 0x90
Instance name: SECRET1_DIGEST
Array Stride: None
Addr Offset: 0x8C
Is Array: False
Num Array Elements: 1
Next Address coming up: 0x94
In decode_addrmap, calling decode_multireg. Addr = 0x94
DEBUG: MULTIREG
Address offset = 94
Register: SECRET2_DIGEST_0 Address: 0x94
Register: SECRET2_DIGEST_1 Address: 0x98
Instance name: SECRET2_DIGEST
Array Stride: None
Addr Offset: 0x94
Is Array: False
Num Array Elements: 1
Next Address coming up: 0x9C
In decode_addrmap, calling decode_multireg. Addr = 0x9C
DEBUG: MULTIREG
Address offset = 9C
Register: SECRET3_DIGEST_0 Address: 0x9C
Register: SECRET3_DIGEST_1 Address: 0xA0
Instance name: SECRET3_DIGEST
Array Stride: None
Addr Offset: 0x9C
Is Array: False
Num Array Elements: 1
Next Address coming up: 0xA4
Number of registers is 8
prim
Register: CSR0 Address: 0xA4
Next Address coming up: 0xA8
Register: CSR1 Address: 0xA8
Next Address coming up: 0xAC
Register: CSR2 Address: 0xAC
Next Address coming up: 0xB0
Register: CSR3 Address: 0xB0
Next Address coming up: 0xB4
Register: CSR4 Address: 0xB4
Next Address coming up: 0xB8
Register: CSR5 Address: 0xB8
Next Address coming up: 0xBC
Register: CSR6 Address: 0xBC
Next Address coming up: 0xC0
Register: CSR7 Address: 0xC0
Next Address coming up: 0xC4
Compilation or elaboration error: Elaborate aborted due to previous errors

Overlap errors (including just a subset of errors):

otp_ctrl.json: error: Instance 'DIRECT_ACCESS_REGWEN' at offset +0x38:0x3B overlaps with 'ERR_CODE' at offset +0x14:0x4B
otp_ctrl.json: error: Instance 'DIRECT_ACCESS_CMD' at offset +0x3C:0x3F overlaps with 'ERR_CODE' at offset +0x14:0x4B
otp_ctrl.json: error: Instance 'DIRECT_ACCESS_ADDRESS' at offset +0x40:0x43 overlaps with 'ERR_CODE' at offset +0x14:0x4B
otp_ctrl.json: error: Instance 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F overlaps with 'ERR_CODE' at offset +0x14:0x4B
otp_ctrl.json: error: Instance 'DIRECT_ACCESS_RDATA' at offset +0x4C:0x9F overlaps with 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F
otp_ctrl.json: error: Instance 'CHECK_TRIGGER_REGWEN' at offset +0x54:0x57 overlaps with 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F
otp_ctrl.json: error: Instance 'CHECK_TRIGGER_REGWEN' at offset +0x54:0x57 overlaps with 'DIRECT_ACCESS_RDATA' at offset +0x4C:0x9F
otp_ctrl.json: error: Instance 'CHECK_TRIGGER' at offset +0x58:0x5B overlaps with 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F
otp_ctrl.json: error: Instance 'CHECK_TRIGGER' at offset +0x58:0x5B overlaps with 'DIRECT_ACCESS_RDATA' at offset +0x4C:0x9F
otp_ctrl.json: error: Instance 'CHECK_REGWEN' at offset +0x5C:0x5F overlaps with 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F
otp_ctrl.json: error: Instance 'CHECK_REGWEN' at offset +0x5C:0x5F overlaps with 'DIRECT_ACCESS_RDATA' at offset +0x4C:0x9F
otp_ctrl.json: error: Instance 'CHECK_TIMEOUT' at offset +0x60:0x63 overlaps with 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F
otp_ctrl.json: error: Instance 'CHECK_TIMEOUT' at offset +0x60:0x63 overlaps with 'DIRECT_ACCESS_RDATA' at offset +0x4C:0x9F
otp_ctrl.json: error: Instance 'INTEGRITY_CHECK_PERIOD' at offset +0x64:0x67 overlaps with 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F
otp_ctrl.json: error: Instance 'INTEGRITY_CHECK_PERIOD' at offset +0x64:0x67 overlaps with 'DIRECT_ACCESS_RDATA' at offset +0x4C:0x9F
otp_ctrl.json: error: Instance 'CONSISTENCY_CHECK_PERIOD' at offset +0x68:0x6B overlaps with 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F
otp_ctrl.json: error: Instance 'CONSISTENCY_CHECK_PERIOD' at offset +0x68:0x6B overlaps with 'DIRECT_ACCESS_RDATA' at offset +0x4C:0x9F
otp_ctrl.json: error: Instance 'VENDOR_TEST_READ_LOCK' at offset +0x6C:0x6F overlaps with 'DIRECT_ACCESS_WDATA' at offset +0x44:0x8F
otp_ctrl.json: error: Instance 'VENDOR_TEST_READ_LOCK' at offset +0x6C:0x6F overlaps with 'DIRECT_ACCESS_RDATA' at offset +0x4C:0x9F