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pipeflow_lib.tlv
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\m4_TLV_version 1d: tl-x.org
\SV
/*
Copyright (c) 2014, Intel Corporation
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// =====================================================
// A TLV M4 library file for transaction flow components
// =====================================================
// This library relies on macros defined in generic_tlv.m4 and rw_tlv.m4.
// See comments in rw_tlv.m4 describing conventions for TLV M4 library files.
// Macros defined in this file provide a few standard interfaces so that macros
// plug together with minimal stitching logic.
// The Backpressure Interface
//
// Flow control between flow components, is generally supported through a "ready/valid" interface (though using
// signal names ("blocked" and "avail", which are more explicit in TL-Verilog context).
// o $avail ("valid") is an indication from the upstream component that it has a transaction to pass along.
// o $blocked (inverse of "ready") is an indication from the downstream component that it is unable (or unwilling)
// to accept an available transaction, if there is one.
// So, a transaction is $accepted if $avail && ! $blocked. $accepted is generated by the downstream component.
// (In TL-Verilog, $accepted would generally be named "$valid" for downstream logic, but we wish to avoid confusion
// with the industry-accepted "ready/valid" terminology, where "valid" is with respect to the upstream component.)
//
// These three signals exist in the same pipestage, which we'll refer to here as |_pipe@_stage.
//
// Additionally, flow components propagate reset. By convention, components provide downstream a
// |_out_pipe@_out_stage$reset connected directly to the input reset. The input reset is, by default
// |_in_pipe@_in_stage@reset from the first of the inputs. An alternate input reset can be provided
// (as a reference from |_in_pipe@_in_stage).
//
// So, more explicitly, the "ready/valid" interface typically use by connected flow components in
// this library is:
//
// From upstream:
// |_pipe
// @_stage
// $avail // A transaction is available for consumption.
// ?$avail // (though downstream should consume on ?$accepted)
// $ANY // input transaction
// $reset // The reset, unless an alternate is provided.
// From downstream:
// |_pipe
// @_stage
// $blocked // Unable to accept a transaction. (Typically provided in the previous stage, for
// // consumption in this stage.)
// $accepted = $avail && ! $blocked;
//
//
// Timing Conventions:
//
// Flow macros supporting the $avail/$blocked interface at |_pipe@_stage perform logic with the following
// timing by default:
//
// |_pipe
// @_stage
// // Upstream:
// // o provides $avail (probably from the previous stage)
// // o provides $ANY
// // Downstream:
// // o provides $blocked (probably from the previous stage, unless $blocked propagates from
// // next stage, like stall)
// // o provides $accepted (as a courtesy, = $avail & ! $blocked)
//
// Component macros that support a $blocked interface at their input take arguments:
// |_in_pipe, and @_in_stage.
//
// Component macros that support a $avail interface at their output take arguments:
// |_out_pipe, and @_out_stage.
//===============================
//
// Flow Component Helpers
//
// Common code for "avail/blocked"-protocol inputs.
// Defines $accepted (for optional upstream use) and $reset_in (for optional internal use) for
// each input. ($reset_in of the first input should be propagated to $reset of outputs).
// Args:
// /_top: Top scope.
// _ins: List of inputs: |pipe, @stage, ...
// _outs: List of outputs: |pipe, @stage, ...
// $_reset1: (opt) The reference to use for the reset signal relative to the first input |pipe, @stage,
// if not $reset.
\TLV flow_interface(/_top, _ins, _outs, $_reset1)
m4+flow_inputs(/_top, ['_ins'], $_reset1)
m4+flow_outputs(/_top, ['_outs'])
// Helpers for the above macro.
\TLV flow_inputs(/_top, _ins, $_reset)
m4_ifelse(['_ins'], [''], [''],
['// Avail/Blocked Input:
m4_argn(1, _ins)
m4_argn(2, _ins)
$accepted = $avail && ! $blocked; // provided for optional upstream use.
$reset_in = m4_ifelse($_reset, [''], ['$reset'], [' $_reset']);
`BOGUS_USE($accepted $reset_in)
m4+flow_inputs(/_top, m4_quote(m4_shift(m4_shift(_ins))), m4_quote(m4_shift(_resets)))
'])
\TLV flow_outputs(/_top, _outs)
m4_ifelse(['_outs'], [''], [''],
['// Avail/Blocked Output:
m4_argn(1, _outs)
m4_argn(2, _outs)
`BOGUS_USE($reset) // Output pipes must provide $reset.
m4+flow_outputs(/_top, m4_quote(m4_shift(m4_shift(_outs))))
'])
// VIZ Helpers
// -----------
// A transaction flow is constructed visually as a graph of line segments with vertices
// ("steering points") that may be flip-flops, represented by dots. Each transaction is
// represented by a Fabric.Object (generally a Fabric.Group). This Fabric.Object will generally
// have originX/Y = "center" and this center moves from point to point along the flow, each
// cycle from on dot (flip-flop) to the next along the flow (or staying put).
//
// Segments in the flow correspond to transaction scopes in the logical design hierarchy.
// Flow macros connect scopes and own the steering points.
//
// Transactions, lines, and dots are created withing VizElements as follows:
// - Transactions are held in a JavaScript object within the VizElement of the top-level scope of
// the transaction--the scope within which the transaction remains contained, and they are
// rendered in this element's overlay.
// - Fabric.Line's are created by their corresponding VizElement by the macro whose output
// is the segment scope, but in the common ancestor scope of the macro instantiations
// providing their input and output (so the segment will be contained within its component's
// box).
// - Fabric.Circles for flops are created by their macros in and by the scope of the macro
// instantiation.
//
// Each flow macro is, therefore, responsible for:
// - creating dots for its flip-flops and defining its steering points (in its own scope)
// - creating segments between its own steering points
// - informing its input scopes of their output segment destination points (by assigning its
// VizElement's getOutputPoint() to return {point: {left: ..., top: ...}, scope: ...})
// - defining the \viz_js block of their output scopes to create segments (in the common
// ancestor scope of the macro instantiations providing their input and output (as specified
// by a macro parameter))
// - animating the movement of transactions that terminate at internal flops from their
// upstream flip-flops or points of origin
// _trans_top_scope_js: JS expression for the top-level scope of the transaction. This scope's
// VizJSContext holds the transaction and segment Fabric.Objects.
//...
// Instantiate a \viz_js block for transaction scope that creates a segment.
// Args:
// _segment_scope_js: JS expression for the VizElement to hold the segment Fabric.Object.
// _from_scope_js: JS expression for the transaction ($ANY) scope from which the transaction
// comes.
\TLV segment_viz(_segment_scope_js, _from_scope_js)
\viz_js
init() {
let segment_scope = _trans_top_scope_js
let from_scope = _from_scope_js
if (!trans_scope.trans_segments) {
trans_scope.trans_segments = []
}
let makeSegment = () => {
new fabric.Line(
[],
{}
)
}
trans_scope.trans_segments.push()
//===============================
//
// Combinational Flow Components
//
// Arbitration MUX with 2 inputs.
//
// Inputs and output implement the "avail/blocked" protocol.
// Input 1 has priority over input 2.
// There is no storage.
\TLV arb2(/_top, |_in1, @_in1, |_in2, @_in2, |_out, @_out, /_trans, $_reset1)
m4+flow_interface(/_top, [' |_in1, @_in1, |_in2, @_in2'], [' |_out, @_out'], $_reset1)
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
// In1 is blocked if output is blocked.
|_in1
@_in1
$blocked = /_top|_out>>m4_align(@_out, @_in1)$blocked;
// In2 is blocked if output is blocked or in1 is available.
|_in2
@_in2
$blocked = /_top|_out>>m4_align(@_out, @_in2)$blocked ||
/_top|_in1>>m4_align(@_in1, @_in2)$avail;
// Output comes from in1 if available, otherwise, in2.
|_out
@_out
$reset = /_top|_in1>>m4_align(@_in1, @_out)$reset_in;
// Output is available if either input is available.
$avail = /_top|_in1>>m4_align(@_in1, @_out)$avail ||
/_top|_in2>>m4_align(@_in2, @_out)$avail;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_in1>>m4_align(@_in1, @_out)$avail ? /_top|_in1/_trans>>m4_align(@_in1, @_out)$ANY :
/_top|_in2/_trans>>m4_align(@_in2, @_out)$ANY;
m4_popdef(['m4_trans_ind'])
// A 2-way-forked flow to an "opportunistic" path (could be a bypass) and a "safe" path. An available transaction
// at the input will follow the opportunistic path if not blocked and the "ok" condition is true.
// Otherwise, the transaction will be allowed to follow the "safe" path (if not blocked).
// |_opp_out@_opp_out and |_safe_out@_safe_out are aligned with |_in@_in.
\TLV opportunistic_flow(/_top, |_in, @_in, |_opp_out, @_opp_out, $_opp_ok, |_safe_out, @_safe_out, /_trans, $_reset)
m4+flow_interface(/_top, [' |_in, @_in'], [' |_opp_out, @_opp_out, |_safe_out, @_safe_out'], $_reset)
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
|_opp_out
@_opp_out
$avail = /_top|_in>>m4_align(@_in, @_opp_out)$avail &&
/_top|_in>>m4_align(@_in, @_opp_out)$_opp_ok;
$reset = /_top|_in>>m4_align(@_in, @_opp_out)$reset_in;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_in/_trans>>m4_align(@_in, @_opp_out)$ANY;
|_safe_out
@_safe_out
$avail = /_top|_in>>m4_align(@_in, @_safe_out)$avail &&
(! /_top|_in>>m4_align(@_in, @_safe_out)$_opp_ok ||
/_top|_opp_out>>m4_align(@_opp_out, @_safe_out)$blocked);
$reset = /_top|_in>>m4_align(@_in, @_safe_out)$reset_in;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_in/_trans>>m4_align(@_in, @_safe_out)$ANY;
|_in
@_in
$blocked = (/_top|_safe_out>>m4_align(@_opp_out, @_in)$blocked ||
! $_opp_ok) &&
/_top|_opp_out>>m4_align(@_opp_out, @_in)$blocked;
m4_popdef(['m4_trans_ind'])
// A 1-in 1-out "avail/blocked" combinational flow component whose output is simply the input
// with the transaction unconditioned.
// This is useful for phase-based logic which isn't fully ironed-out yet, and currently
// requires clock enables to be driven a cycle before they the consuming clock edge.
// This macro can be used to uncondition the input transaction to phase-based flow logic.
\TLV uncondition_flow(/_top, |_in, @_in, |_out, @_out, /_trans, $_reset)
m4+flow_interface(/_top, [' |_in, @_in'], [' |_out, @_out'], $_reset)
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
|_in
@_in
$blocked = /_top|_out>>m4_align(@_out, @_in)$blocked;
|_out
@_out
$avail = /_top|_in>>m4_align(@_in, @_out)$avail;
$reset = /_top|_in>>m4_align(@_in, @_out)$reset_in;
/_trans
m4_trans_ind $ANY = /_top|_in/_trans>>m4_align(@_in, @_out)$ANY;
// A 1-in 1-out "avail/blocked" combinational flow component that, in default usage, does nothing but rename pipeline/stage.
// It can also:
// o cuts backpressure connection
// o add extra backpressure
// Args (non-standard ones):
// $_block_expr: An expression in |_in@_in to:
// ['']: default behavior (input and output are identical with identical backpressure)
// ['&& 1'b0']: cut downstream backpressure because it must be 1'b0. (Use this exact string to enable assertion.)
// ['|| ! $ready']: to introduce backpressure.
// ['&& 1'b0) || (! $ready']: to do both
\TLV connect(/_top, |_in, @_in, |_out, @_out, /_trans, $_reset, $_block_expr)
m4+flow_interface(/_top, [' |_in, @_in'], [' |_out, @_out'], $_reset)
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
|_in
@_in
$blocked = (/_top|_out>>m4_align(@_out, @_in)$blocked $_block_expr);
$out_avail = $avail && ! ((1'b0 $_block_expr));
|_out
@_out
m4_ifelse($_block_expr, ['&& 1'b0'], ['m4_assert(! $blocked, ['"Expected no backpressure from .../_top|_out@_out$blocked."'])'])
$avail = /_top|_in>>m4_align(@_in, @_out)$out_avail;
$reset = /_top|_in>>m4_align(@_in, @_out)$reset_in;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_in/_trans>>m4_align(@_in, @_out)$ANY;
// A 2-way-forked flow macro. Two control input signals $_out0/1_ok (in |_in@0) specify which paths
// may be taken. Any values are legal and are dont-care for an invalid input transaction.
// |_out0 is favored if both are permitted. $blocked propagates appropriately.
\TLV fork(/_top, |_in, @_in, $_out0_ok, |_out0, @_out0, $_out1_ok, |_out1, @_out1, /_trans, $_reset)
m4+flow_interface(/_top, [' |_in, @_in'], [' |_out0, @_out0, |_out1, @_out1'], $_reset)
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
|_out0
@_out0
$avail = /_top|_in>>m4_align(@_in, @_out0)$avail &&
/_top|_in>>m4_align(@_in, @_out0)$_out0_ok;
$reset = /_top|_in>>m4_align(@_in, @_out0)$reset_in;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_in/_trans>>m4_align(@_in, @_out0)$ANY;
|_out1
@_out1
$avail = /_top|_in>>m4_align(@_in, @_out1)$avail &&
/_top|_in>>m4_align(@_in, @_out1)$_out1_ok &&
! /_top|_out0>>m4_align(@_out0, @_out1)$avail;
$reset = /_top|_in>>m4_align(@_in, @_out1)$reset_in;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_in/_trans>>m4_align(@_in, @_out1)$ANY;
|_in
@_in
$blocked = (/_top|_out0>>m4_align(@_out0, @_in)$blocked || ! $_out0_ok) &&
(/_top|_out1>>m4_align(@_out1, @_in)$blocked || ! $_out1_ok);
m4_popdef(['m4_trans_ind'])
// A 1-in 1-out "avail/blocked" combinational flow component that is able to drop transactions.
// |_in@_in$drop must be provided to do so (?$avail). ($drop = 1'b0 is equivalent to m4+connect macro.)
// If $drop, |_in@_in$blocked == 0 and |_out@_out$avail == 0.
\TLV drop_flow(/_top, |_in, @_in, |_out, @_out, /_trans, $_reset)
m4+flow_interface(/_top, [' |_in, @_in'], [' |_out, @_out'], $_reset)
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
|_in
@_in
$blocked = /_top|_out>>m4_align(@_out, @_in)$blocked && ! $drop;
|_out
@_out
$avail = /_top|_in>>m4_align(@_in, @_out)$avail &&
! /_top|_in>>m4_align(@_in, @_out)$dropped;
$reset = /_top|_in>>m4_align(@_in, @_out)$reset_in;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_in/_trans>>m4_align(@_in, @_out)$ANY;
//========================================
//
// 1-In 1-Out Flow Components
//
// A backpressured flop or latch stage.
//
// This provides a backpressure interfaces for one upstream and one downstream component.
//
// For flop-based usage:
//
// |in_pipe@in_stage$ANY
// -----+
// |
// =======|===========================
// |
// | |\ +--+
// +--| | | |
// | |-| |-+
// +--| | |/\| |
// | |/ +--+ |
// | | |out_pipe@out_stage$ANY
// +-----------+----
//
// Input interface:
// |_in_pipe
// @_in_stage (minus a phase for SELF)
// $avail // A transaction is available for consumption.
// ?$avail
// $ANY // input transaction
// |_out_pipe
// @_out_stage
// $blocked // The corresponding output transaction, if valid, cannot be consumed
// // and will recirculate.
// Output signals:
// |_in_pipe
// @_in_stage
// $blocked // The corresponding input transaction, if valid, cannot be consumed
// // and must recirculate.
// $accepted = $avail && ! $blocked
// |_out_pipe
// @_out_stage - 1 // Generally for use in @_out_stage.
// $avail // A transaction is available for consumption.
// // (Actually, @out_stage-1, but expect consumption in @out_stage.)
// @_out_stage - 1 + #_data_delay // Generally for use in @_out_stage + #_data_delay.
// ?$avail
// $ANY // Output transaction
//
// This macro also supports SELF (Synchronous ELastic Flow) pipelines that are latch-based pipelines
// with backpressure at every phase.
// In this case, the input stage is the cycle feeding the recirculation, and the output stage is
// the cycle of the recirculation + 1. Input and output stages are L for B-phase stages.
// These additional optional parameters exist to support it:
// b_latch: 1 for a SELF stage that is recirculating across a B-latch (0 default).
// a_latch: 1 for a SELF stage that is recirculating across an A-latch (0 default).
// Internals:
// pre_latch_phase: 'L' for A-latch stage.
// post_latch_phase: 'L' for B-latch stage.
\TLV bp_stage(/_top, |_in_pipe, @_in_stage, |_out_pipe, @_out_stage, /_trans, #_b_latch, #_a_latch, $_reset, #_data_delay)
m4_pushdef(['m4_b_latch'], m4_ifelse(#_b_latch, 1, 1, 0))
m4_pushdef(['m4_a_latch'], m4_ifelse(#_a_latch, 1, 1, 0))
m4_pushdef(['m4_pre_latch_phase'], m4_ifelse(m4_a_latch, 1, L,))
m4_pushdef(['m4_post_latch_phase'], m4_ifelse(m4_b_latch, 1, L,))
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
m4_pushdef(['m4_data_delay'], m4_ifelse(#_data_delay, [''], 0, #_data_delay))
m4+flow_interface(/_top, [' |_in_pipe, @_in_stage'], [' |_out_pipe, @_out_stage'], $_reset)
|_out_pipe
@m4_stage_eval(@_out_stage - m4_b_latch <<1)['']m4_post_latch_phase
$reset = /_top|_in_pipe>>m4_align(@_in_stage, @_out_stage <<1)$reset_in;
$avail = $reset ? 1'b0 :
(>>1$avail && >>1$blocked) || // Recirc'ed or
// Above is recomputation of $recirc to avoid a flop.
// For SELF, its in the same stage, and is redundant computation.
/_top|_in_pipe>>m4_align(@_in_stage, @_out_stage<<1)$avail; // Incoming available
//$first_avail = $avail && ! >>1$blocked; // Transaction is newly available.
@m4_stage_eval(@_out_stage<<1>>m4_data_delay)m4_pre_latch_phase
?$avail // Physically, $first_avail && *reset_b for functional gating in
// place of recirculation.
/_trans
m4_trans_ind $ANY =
m4_trans_ind |_out_pipe>>1$recirc ? >>1$ANY
m4_trans_ind : /_top|_in_pipe/_trans>>m4_align(@_in_stage, @_out_stage - 1)$ANY;
@m4_stage_eval(@_out_stage - m4_b_latch)['']m4_post_latch_phase
$recirc = $avail && $blocked; // Available transaction that is blocked; must recirc.
|_in_pipe
@m4_stage_eval(@_in_stage - m4_b_latch)['']m4_post_latch_phase
$blocked = /_top|_out_pipe>>m4_align(@_out_stage, @_in_stage)$recirc;
// This trans is blocked (whether valid or not) if the next stage is recirculating.
m4_popdef(['m4_b_latch'])
m4_popdef(['m4_a_latch'])
m4_popdef(['m4_pre_latch_phase'])
m4_popdef(['m4_post_latch_phase'])
m4_popdef(['m4_trans_ind'])
m4_popdef(['m4_data_delay'])
// A backpressured pipeline, chaining N bp_stage's.
// This is an older version of bp_pipeline_v2 where stage names, including input and output
// stages, are all based on the same root name.
\TLV bp_pipeline(/_top, |_name, #_first_stage, #_last_stage, /_trans, $_reset, #_data_delay)
m4_forloop(['m4_stage'], #_first_stage, #_last_stage, ['
m4+bp_stage(/_top, |_name['']m4_stage, @1, |_name['']m4_eval(m4_stage + 1), @1, /_trans, 0, 0, $_reset, #_data_delay)
'])
// -------------------------
// Stall Pipeline
//
// One cycle of a stall pipeline.
// /_top: eg: ['/top']
// |_in/out_pipe, @_in/out_stage: The pipeline and stage of the input (A-phase) stage
// and the output stage.
//
// This creates recirculation for a transaction going from |_in_pipe to |_out_pipe,
// where |_in_pipe@_in_stage is one cycle from |_out_pipe@_out_stage without backpressure.
//
// Currently, this uses recirculation, but it is intended to be modified to use flop enables
// to hold the transactions.
//
// Input interface:
// |_in_pipe
// @_in_stage
// $reset // A reset signal.
// $avail // A transaction is available for consumption.
// ?avail
// /_trans
// $ANY // input transaction
// |_out_pipe
// @_out_stage
// $blocked // The corresponding output transaction, if valid, cannot be consumed
// // and will recirculate.
// Output signals:
// |_in_pipe
// @_in_stage
// $blocked // The corresponding input transaction, if valid, cannot be consumed
// // and must recirculate.
// |_out_pipe
// @_out_stage
// $reset // The reset signal (from input pipeline).
// $avail // A transaction is available for consumption.
// ?avail
// /_trans
// $ANY // Output transaction
//
\TLV stall_stage(/_top, |_in_pipe, @_in_stage, |_out_pipe, @_out_stage, /_trans, $_reset)
m4+flow_interface(/_top, [' |_in_pipe, @_in_stage'], [' |_out_pipe, @_out_stage'], $_reset)
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
|_in_pipe
@_in_stage
$blocked = /_top|_out_pipe>>m4_align(@_out_stage, @_in_stage)$blocked;
|_out_pipe
@_out_stage
// Propagate $reset to next stage with no delay (may create timing pressure,
// but similar to reverse path for $blocked).
$reset = /_top|_in_pipe>>m4_align(@_in_stage, @_out_stage)$reset_in;
$avail = $reset ? 1'b0 :
>>1$blocked ? >>1$avail :
/_top|_in_pipe>>m4_align(@_in_stage >> 1, @_out_stage)$avail;
?$avail
/_trans
m4_trans_ind $ANY = |_out_pipe>>1$blocked ? >>1$ANY : /_top|_in_pipe/_trans>>m4_align(@_in_stage >> 1, @_out_stage)$ANY;
m4_popdef(['m4_trans_ind'])
// A Stall Pipeline.
//
// Input interface:
// |_name#_first_stage
// @0
// $reset // A reset signal.
// $avail // A transaction is available for consumption.
// ?trans_valid = $avail && ! $blocked
// /trans
// $ANY // input transaction.
// |_name#_last_stage
// @0
// $blocked // The stall signal.
// Output signals:
// |_in_pipe
// @0
// $blocked // Identical to the stall signal.
// |_name#_last_stage
// @0
// $reset // The reset signal from the input pipeline.
// $avail // A transaction is available for consumption.
// $trans_valid // The transaction is valid.
// ?$trans_valid
// /trans
// $ANY
//
\TLV stall_pipeline(/_top, |_name, #_first_stage, #_last_stage, /_trans, $_reset)
m4_forloop(['m4_stage'], #_first_stage, #_last_stage, ['
m4+stall_stage(/_top, |_name['']m4_stage, @1, |_name['']m4_eval(m4_stage + 1), @1, /_trans, $_reset)
'])
//
// -------------------------
// FIFOs
//
// A simple flop-based FIFO with entry-granular clock gating.
// Note: Simulation is less efficient due to the explicit clock gating.
//
// m4+flop_fifo_v2(top, in_pipe, in_stage, out_pipe, out_stage, #_depth, /_trans, #_high_water, $_reset)
//
// Input interface:
// |in_pipe
// @in_stage
// $reset // A reset signal.
// $avail // A transaction is available for consumption.
// $trans_valid // = $avail && ! $blocked;
// ?$trans_valid
// $ANY // Input transaction (under trans if non-empty)
// |out_pipe
// @out_stage
// $blocked // The corresponding output transaction, if valid, cannot be consumed
// // and will recirculate.
// Output interface:
// |in_pipe
// @in_stage
// $blocked // The corresponding input transaction, if valid, cannot be consumed
// // and must recirculate.
// |out_pipe
// @out_stage
// $avail // A transaction is available for consumption.
// $trans_valid = $avail && ! $blocked
// @out_stage
// ?$trans_valid
// $ANY // Output transaction (under trans if given)
//
// Three interfaces are available for backpressure. The interface above shows the $blocked interface, but
// any of the three may be used:
// 1) $blocked: Backpressure within a cycle.
// 2) $full or $ValidCount: Reflect a high-water mark that can be used as backpressure.
// Useful for sources that are not aware of other possible sources filling the FIFO.
// 3) |out_pipe$trans_valid: Can be used to track credits for the FIFO. See m4_credit_counter(..).
//
// The head and tail "pointers" are maintained in the following state. Below shows allocation of 4 entries
// followed by deallocation of 4 entries in a 4-entry FIFO. The valid mask for the entries is $state
// modified by $two_valid, which extends the $state mask by an entry. This technique uses n+(n log2) state bits (vs.
// (n log2)*2 for pointers or n*2 for decoded pointers). It does not require decoders for read/write.
//
// $ValidCount 012343210
// /0 011110000
// $state< 1 000111000
// |2 000011100
// \3 000000010
// $two_valid 001111100
// Computed:
// $empty 100000001
// $full 000010000 (Assuming default m4_high_water.)
//
// Fifo bypass goes through a mux with |in_pipe@in_at aligned to |out_pipe@out_at.
\TLV flop_fifo_v2(/_top,|_in_pipe,@_in_at,|_out_pipe,@_out_at,#_depth,/_trans,#_high_water, $_reset)
m4+flow_interface(/_top, [' |_in_pipe, @_in_at'], [' |_out_pipe, @_out_at'], $_reset)
m4_pushdef(['m4_ptr_width'], \$clog2(#_depth))
m4_pushdef(['m4_counter_width'], \$clog2((#_depth)+1))
m4_pushdef(['m4_bypass_align'], m4_align(@_out_at, @_in_at))
m4_pushdef(['m4_reverse_bypass_align'], m4_align(@_in_at,@_out_at))
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
// @0
\SV_plus
localparam bit [m4_counter_width-1:0] full_mark_['']m4_plus_inst_id = #_depth - m4_ifelse(#_high_water, [''], 0, ['#_high_water']);
// FIFO Instantiation
// Hierarchy declarations
|_in_pipe
/entry[m4_eval((#_depth)-1):0]
|_out_pipe
/entry[m4_eval((#_depth)-1):0]
|_in_pipe
@_in_at
$out_blocked = /_top|_out_pipe>>m4_bypass_align$blocked;
$blocked = >>1$full && $out_blocked;
`BOGUS_USE($blocked) // Not required to be consumed elsewhere.
$would_bypass = >>1$empty;
$bypass = $would_bypass && ! $out_blocked;
$push = $accepted && ! $bypass;
$grow = $accepted && $out_blocked;
$shrink = ! $avail && ! $out_blocked && ! >>1$empty;
$valid_count[m4_counter_width-1:0] = $reset ? '0
: >>1$valid_count + (
$grow ? { {(m4_counter_width-1){1'b0}}, 1'b1} :
$shrink ? '1
: '0
);
// At least 2 valid entries.
//$two_valid = | $ValidCount[m4_counter_width-1:1];
// but logic depth minimized by taking advantage of prev count >= 4.
$two_valid = | >>1$valid_count[m4_counter_width-1:2] || | $valid_count[2:1];
// These are an optimization of the commented block below to operate on vectors, rather than bits.
// TODO: Keep optimizing...
{/entry[*]$$prev_entry_was_tail} = {/entry[*]>>1$reconstructed_is_tail\[m4_eval(#_depth-2):0], /entry[m4_eval(#_depth-1)]>>1$reconstructed_is_tail} /* circular << */;
{/entry[*]$$push} = {#_depth{$push}} & /entry[*]$prev_entry_was_tail;
/entry[*]
// Replaced with optimized versions above:
// $prev_entry_was_tail = /entry[(entry+(m4_depth)-1)%(m4_depth)]>>1$reconstructed_is_tail;
// $push = |_in_pipe$push && $prev_entry_was_tail;
$valid = (>>1$reconstructed_valid && ! /_top|_out_pipe/entry>>m4_bypass_align$pop) || $push;
$is_tail = |_in_pipe$accepted ? $prev_entry_was_tail // shift tail
: >>1$reconstructed_is_tail; // retain tail
$state = |_in_pipe$reset ? 1'b0
: $valid && ! (|_in_pipe$two_valid && $is_tail);
@m4_stage_eval(@_in_at>>1)
$empty = ! $two_valid && ! $valid_count[0];
$full = ($valid_count == full_mark_['']m4_plus_inst_id); // Could optimize for power-of-two depth.
/entry[*]
@m4_stage_eval(@_in_at>>1)
$prev_entry_state = /entry[(entry+(#_depth)-1)%(#_depth)]$state;
$next_entry_state = /entry[(entry+1)%(#_depth)]$state;
$reconstructed_is_tail = ( /_top|_in_pipe$two_valid && (!$state && $prev_entry_state)) ||
(! /_top|_in_pipe$two_valid && (!$next_entry_state && $state)) ||
(|_in_pipe$empty && (entry == 0)); // need a tail when empty for push
$is_head = $state && ! $prev_entry_state;
$reconstructed_valid = $state || (/_top|_in_pipe$two_valid && $prev_entry_state);
// Write data
|_in_pipe
@_in_at
/entry[*]
//?$push
// $aNY = |m4_in_pipe['']m4_trans$ANY;
/_trans
m4_trans_ind $ANY = /entry$push ? /_top|_in_pipe['']/_trans$ANY : >>1$ANY /* RETAIN */;
// Read data
|_out_pipe
@_out_at
///$pop = ! /m4_top|m4_in_pipe>>m4_align(m4_in_at + 1, m4_out_at)$empty && ! $blocked;
/entry[*]
$is_head = /_top|_in_pipe/entry>>m4_align(@_in_at + 1, @_out_at)$is_head;
$pop = $is_head && ! |_out_pipe$blocked;
/read_masked
/_trans
m4_trans_ind $ANY = /entry$is_head ? /_top|_in_pipe/entry['']/_trans>>m4_align(@_in_at + 1, @_out_at)$ANY /* $aNY */ : '0;
/accum
/_trans
m4_trans_ind $ANY = ((entry == 0) ? '0 : /entry[(entry+(#_depth)-1)%(#_depth)]/accum['']/_trans$ANY) |
/entry/read_masked['']/_trans$ANY;
/head
$avail = |_out_pipe$avail;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_out_pipe/entry[(#_depth)-1]/accum['']/_trans$ANY;
// Bypass
|_out_pipe
@_out_at
// Available output. Sometimes it's necessary to know what would be coming to determined
// if it's blocked. This can be used externally in that case.
/fifo_head
$avail = |_out_pipe$avail;
?$avail
/_trans
m4_trans_ind $ANY = /_top|_in_pipe>>m4_reverse_bypass_align$would_bypass
m4_trans_ind ? /_top|_in_pipe['']/_trans>>m4_reverse_bypass_align$ANY
m4_trans_ind : |_out_pipe/head['']/_trans$ANY;
$avail = ! /_top|_in_pipe>>m4_reverse_bypass_align$would_bypass || /_top|_in_pipe>>m4_reverse_bypass_align$avail;
$trans_valid = $avail && ! $blocked;
?$trans_valid
/_trans
m4_trans_ind $ANY = |_out_pipe/fifo_head['']/_trans$ANY;
// Deliver reset.
$reset = /_top|_in_pipe>>m4_reverse_bypass_align$reset_in;
m4_popdef(['m4_ptr_width'])
m4_popdef(['m4_counter_width'])
m4_popdef(['m4_bypass_align'])
m4_popdef(['m4_reverse_bypass_align'])
m4_popdef(['m4_trans_ind'])
/** Alternate code for pointer indexing. Replaces $ANY expression above.
// Hierarchy
|m4_in_pipe
/entry2[(m4_depth)-1:0]
// Head/Tail ptrs.
|m4_in_pipe
@m4_in_at
>>1$WrPtr[m4_ptr_width-1:0] =
$reset ? '0 :
$trans_valid ? ($WrPtr == (m4_depth - 1))
? '0
: $WrPtr + {{(m4_ptr_width-1){1'b0}}, 1'b1} :
$RETAIN;
|m4_out_pipe
@m4_out_at
>>1$RdPtr[m4_ptr_width-1:0] =
/m4_top|m4_in_pipe>>m4_reverse_bypass_align$reset
? '0 :
$trans_valid ? ($RdPtr == (m4_depth - 1))
? '0
: $RdPtr + {{(m4_ptr_width-1){1'b0}}, 1'b1} :
$RETAIN;
// Write FIFO
|m4_in_pipe
@m4_in_at
$dummy = '0;
?$trans_valid
// This doesn't work because SV complains for FIFOs in replicated context that
// there are multiple procedures that assign the signals.
// Array writes can be done in an SV module.
// The only long-term resolutions are support for module generation and use
// signals declared within for loops with cross-hierarchy references in SV.
// TODO: To make a simulation-efficient FIFO, use DesignWare.
{/entry2[$WrPtr]$$ANY} = $ANY;
// Read FIFO
|m4_out_pipe
@m4_out_at
/read2
$trans_valid = |m4_out_pipe$trans_valid;
?$trans_valid
$ANY = /m4_top|m4_in_pipe/entry2[|m4_out_pipe$RdPtr]>>m4_reverse_bypass_align$ANY;
`BOGUS_USE($dummy)
?$trans_valid
$ANY = /read2$ANY;
**/
m4_unsupported(['m4_flop_fifo'], 1)
// A FIFO using simple_bypass_fifo.
// Requires include "simple_bypass_fifo.sv".
//
// The interface is identical to m4_flop_fifo, above, except that data width must be provided explicitly.
//
\TLV m4_old_simple_bypass_fifo_v2(/_top,|_in_pipe,@_in_at,|_out_pipe,@_out_at,#_depth,#_width,/_trans,#_high_water)
|_in_pipe
@_in_at
$out_blocked = /_top|_out_pipe>>m4_align(@_out_at, @_in_at)$blocked;
$blocked = (/_top/fifo>>m4_align(0, @_in_at)$cnt >= m4_eval(#_depth - m4_ifelse(#_high_water, [''], 0, ['#_high_water']))) && $out_blocked;
/fifo
simple_bypass_fifo #(.WIDTH(#_width), .DEPTH(#_depth))
fifo(.clk(clk), .reset(/_top|m4_in_pipe>>m4_align(@_in_at, 0)$reset),
.push(/_top|_in_pipe>>m4_align(@_in_at, 0)$trans_valid),
.data_in(/_top|_in_pipe['']/_trans>>m4_align(@_in_at, 0)$ANY),
.pop(/_top|_out_pipe>>m4_align(@_out_at, 0)$trans_valid),
.data_out(/_top|_out_pipe['']/_trans>>m4_align(@_out_at, 0)$$ANY),
.cnt($$cnt[2:0]));
|_out_pipe
@_out_at
$avail = /_top/fifo>>m4_align(0, @_out_at)$cnt != 3'b0 || /_top|_in_pipe>>m4_align(@_in_at, @m4_out_at)$avail;
$trans_valid = $avail && !$blocked;
// A FIFO using simple_bypass_fifo.
// Requires include "simple_bypass_fifo.sv".
//
// The interface is identical to m4_flop_fifo, above, except that data width must be provided explicitly.
//
// Args:
// /_top, |_in, @_in, |_out, @_out, #_depth, #_width: as one would expect.
// /_trans: hierarchy for transaction, eg: ['/flit'] or ['']
// #_high_water: Default to 0. Number of additional entries beyond full.
\TLV simple_bypass_fifo_v2(/_top, |_in, @_in, |_out, @_out, #_depth, #_width, /_trans, #_high_water, $_reset)
m4+flow_interface(/_top, [' |_in, @_in'], [' |_out, @_out'], $_reset)
|_in
/_trans
@_in
$out_blocked = /_top|_out>>m4_align(@_out, @_in)$blocked;
$blocked = (/_top|_in/fifo>>m4_align(@_out, @_in)$cnt >= m4_eval(#_depth - m4_ifelse(#_high_water, [''], 0, #_high_water))) && $out_blocked;
/fifo
simple_bypass_fifo #(.WIDTH(#_width), .DEPTH(#_depth))
fifo(.clk(clk), .reset(|_in$reset_in),
.push(|_in$accepted),
.data_in(|_in/_trans$ANY),
.pop(/_top|_out>>m4_align(@_out, @_in)$accepted),
.data_out(/_top|_out/_trans>>m4_align(@_out, @_in)$$ANY),
.cnt($$cnt[\$clog2(#_depth)-1:0]));
|_out
/_trans
@_out
$avail = /_top|_in/fifo>>m4_align(@_in, @_out)$cnt != '0 || /_top|_in>>m4_align(@_in, @_out)$avail;
$reset = /_top|_in>>m4_align(@_in, @_out)$reset_in;
// A FIFO with virtual channels.
// VC copies of m4+flop_fifo, which drain based on a priority assigned to each VC.
// Data should arrive early in |in_pipe@in_stage, or in the stage prior. It can be
// available on the output early in |out_pipe@out_stage or late the cycle before,
// determined by bypass_at.
// The FIFOs feed into a speculative pre-selected flit. The
// pre-selected flit remains in the corresponding m4+flop_fifo until it is accepted
// externally, so the selection is non-blocking. The pre-selected flit will be
// bumped by a higher-priority flit (but not an equal priority flit).
//
// Parameters begin as with m4_flop_fifo:
// m4+vc_flop_fifo_v2(top, in_pipe, in_at, out_pipe, out_at, depth, trans, vc_range, prio_range [, bypass_at [, high_water]])
// Input interface:
// |in_pipe
// @in_stage // (or cycle prior if bypass_stage requires it)
// $reset // A reset signal.
// ?$trans_valid // (| /vc[*]$vc_trans_valid)
// $ANY // Input transaction (under trans if non-empty)
// /vc[*]
// |in_pipe
// @in_stage
// $vc_trans_valid
// |out_pipe
// @out_stage-1
// $has_credit // Credit is available for this VC (or by other means, it is okay to output this VC).
// $Prio // (config) the prio of each VC
// Output interface:
// /vc[*]
// |in_pipe
// @in_stage
// $blocked // The corresponding input transaction, if valid, cannot be consumed
// // and must recirculate.
// |out_pipe
// @bypass_stage
// $vc_trans_valid// An indication of the outbound $vc (or use /top|out_pipe$trans_valid &&
// /top|out_pipe/trans$vc).
// |out_pipe
// @bypass_stage
// $trans_valid
// ?$trans_valid
// $ANY // Output transaction (under trans if given)
// Backpressure ($blocked, $full, $ValidCount) signals are per /vc; $trans_valid is a singleton
// for input and output and reflects per-VC backpressure; $avail is not produced on
// output and should not be assigned externally for input.
//
\TLV vc_flop_fifo_v2(/_top, |_in_pipe, @_in_at, |_out_pipe, @_out_at, #_depth, /_trans, _vc_range, _prio_range, @_bypass_at_opt, #_high_water, $_reset)
// TODO: m4+flow_interface(/_top, [' |_in_pipe, @_in_at'], [' |_out_pipe, @_out_at'], $_reset)
m4_define(['m4_bypass_at'], m4_ifelse(@_bypass_at_opt, [''], @_out_at, @_bypass_at_opt))
m4_pushdef(['m4_arb_at'], m4_stage_eval(@_out_at - 1)) // Arb and read VC FIFOs the stage before m4_out_at.
m4_pushdef(['m4_bypass_align'], m4_align(@_out_at, @_in_at))
m4_pushdef(['m4_reverse_bypass_align'], m4_align(@_in_at, @_out_at))
m4_pushdef(['m4_trans_ind'], m4_ifelse(/_trans, [''], [''], [' ']))
/vc[_vc_range]
|_in_pipe
@_in_at
// Apply inputs to the right VC FIFO.
//
$reset = /_top|_in_pipe$reset;
$trans_valid = $vc_trans_valid && ! /vc|_out_pipe>>m4_bypass_align$bypassed_fifos_for_this_vc;
$avail = $trans_valid;
?$trans_valid
/_trans
m4_trans_ind $ANY = /_top|_in_pipe['']/_trans$ANY;
// Instantiate FIFO. Output to stage (m4_out_at - 1) because bypass is m4_out_at.
m4+flop_fifo_v2(/vc, |_in_pipe, @_in_at, |_out_pipe, @m4_arb_at, #_depth, /_trans, #_high_water)
// FIFO select.
//
/vc[*]
|_out_pipe
@m4_arb_at
$arbing = $avail && $has_credit;
/prio[_prio_range]
// Decoded priority.
$Match <= #prio == |_out_pipe$Prio;
// Mask of same-prio VCs.
/other_vc[_vc_range]
$SamePrio <= |_out_pipe$Prio == /vc[#other_vc]|_out_pipe$Prio;
// Select among same-prio VCs.
$competing = $SamePrio && /vc[#other_vc]|_out_pipe$arbing;
// Select FIFO if selected within priority and this VC has the selected (max available) priority.
$fifo_sel = m4_am_max(/other_vc[*]$competing, vc) && | (/prio[*]$Match & /_top/prio[*]|_out_pipe$sel);
// TODO: Need to replace m4_am_max with round-robin within priority.
$blocked = ! $fifo_sel;
m4_bypass_at
// Can bypass FIFOs?
$can_bypass_fifos_for_this_vc = /vc|_in_pipe>>m4_reverse_bypass_align$vc_trans_valid &&
/vc|_in_pipe>>m4_align(@_in_at + 1, @_out_at)$empty &&
$has_credit;
// Indicate output VC as per-VC FIFO output $trans_valid or could bypass in this VC.
$bypassed_fifos_for_this_vc = $can_bypass_fifos_for_this_vc && ! /_top|_out_pipe$fifo_trans_avail;
$vc_trans_valid = $trans_valid || $bypassed_fifos_for_this_vc;
`BOGUS_USE($vc_trans_valid) // okay to not consume this
/prio[_prio_range]
|_out_pipe
@m4_arb_at
/vc[_vc_range]
// Trans available for this prio/VC?
$avail_within_prio = /_top/vc|_out_pipe$avail &&
/_top/vc|_out_pipe/prio$Match;
// Is this priority available in FIFOs.
$avail = | /vc[*]$avail_within_prio;
// Select this priority if its the max available.
$sel = m4_am_max(/prio[*]|_out_pipe$avail, prio);
|_out_pipe
@m4_arb_at
$fifo_trans_avail = | /_top/vc[*]|_out_pipe$arbing;
/fifos_out
$fifo_trans_avail = |_out_pipe$fifo_trans_avail;
/vc[_vc_range]
m4+select($ANY, /_top, /vc, |_out_pipe['']/_trans, |_out_pipe, $fifo_sel, $ANY, $fifo_trans_avail)
// Output transaction
//
m4_bypass_at
// Incorporate bypass
// Bypass if there's no transaction from the FIFOs, and the incoming transaction is okay for output.
$can_bypass_fifos = | /_top/vc[*]|_out_pipe$can_bypass_fifos_for_this_vc;
$trans_valid = $fifo_trans_avail || $can_bypass_fifos;
?$trans_valid
/_trans
m4_trans_ind $ANY = |_out_pipe$fifo_trans_avail ? |_out_pipe/fifos_out$ANY : /_top|_in_pipe['']/_trans>>m4_reverse_bypass_align$ANY;
m4_popdef(['m4_arb_at'])
m4_popdef(['m4_bypass_align'])
m4_popdef(['m4_reverse_bypass_align'])
m4_popdef(['m4_trans_ind'])
m4_unsupported(['m4_vc_flop_fifo'], 1)
// Flow from /_scope and /_top/no_bypass to /bypass#_cycles that provides a value that bypasses up-to #_cycles
// from previous stages of /_scope any contain a $_valid $_src_tag matching $_tag, or /_top/no_bypass$_value otherwise.
\TLV bypass(/_top, #_cycles, /_scope, $_valid, $_src_tag, $_src_value, $_tag)
/bypass#_cycles
$ANY =
// Bypass stages:
m4_ifexpr(#_cycles >= 1, (/_scope>>1$_valid && (/_scope>>1$_src_tag == /_top$_tag)) ? /_scope>>1$_src_value :)
m4_ifexpr(#_cycles >= 2, (/_scope>>2$_valid && (/_scope>>2$_src_tag == /_top$_tag)) ? /_scope>>2$_src_value :)
m4_ifexpr(#_cycles >= 3, (/_scope>>3$_valid && (/_scope>>3$_src_tag == /_top$_tag)) ? /_scope>>3$_src_value :)
/_top/no_bypass$ANY;
// A one-cycle skid buffer. This can be used to alleviate timing on backpressure ($blocked) between flow components.
// Backpressure is applied with a one-cycle delay, and if the downstream backpressures a valid transaction, the transaction
// is captured in the skid buffer which receives the packpressure immediately. The skid buffer does not add any latency
// to the flow.
// Args are typical flow component args (where /_trans is not optional out of laziness).
\TLV skid_buffer(/_top, |_in, @_in, |_out, @_out, /_trans, $_reset)