Bug: I2C lock up

[vthakur7f]

Product: (OC-SDR, OC-LTE, OC-LTE, OC-Power, others)

OC-SDR

Category: (Hardware, Software/stack, Firmware/bootloader, Documentation)

Firmware/OCWare
Describe the issue found
This is a hardware issue that we've seen on multiple boards that I'd like get to the bottom of. Firmware will need to be made robust enough to handle SCL being held low anyway , but on SDR 33, the bus locks up if we don't read from the EEPROM first. Very strange, and a bit worrying that the entire bus can be taken down but partially fixed with software if things are done in the correct order.

To repro, run latest Rev_C_Changes on SDR 33 - POST will stop shortly into SDR. To fix, simply add

char tmp_char;
eeprom_read(OC_SS_SDR, OC_SDR_INVEN_EEPROM, OC_SDR_BOARD_INFO, &tmp_char, 1);

in sdr_init() right before the call to sdr_fx3_reset();

Please provide all necessary steps to reproduce the issue
A clear and concise description of steps to reproduce the bug.

[vthakur7f]

[Originally commented by imgraham]
Seems that this is related to our EEPROM chip - I can get i2c7 to lock up simply by trying to write to one of the GBC's EEPROM while WP is asserted. By the data sheet, the IC doesn't ACK any of the data bytes in this scenario. This is easily reproducible, so I'd like to probe the lines to see what's up. It's really unfortunate if it's that easy to screw up Tiva - we might have to muck around with the TI drivers afterall.