Why does Resizer::wireClkResistance prioritize horizontal layers' resistance?

[donn]

https://github.com/The-OpenROAD-Project/OpenROAD/blame/9c3bac8a28f438fa77383fa2035a66c1863a660a/src/rsz/src/EstimateWireParasitics.cc#L211

This essentially makes it so set_wire_rc -clock on any vertical layers basically does not affect resistance at all. Capacitance is different.

Any thoughts on why this is the case?

[maliberty]

@arthurjolo please comment as this comes from 3733fc4

[maliberty]

and modified in a97c80f

[arthurjolo]

That seems to be some leftover code that was used in an early implementation. Originally when trying to get the res or cap without specifying a layer or the orientation the default value would be the horizontal, but later it was changed to assume an even split of H&V, this "if" statement was supposed to be removed and rsz::wireClkResistance should be just like it is done with rsz::wireClkCapacitance. PR #6662 should fix this, thanks for noticing.

[maliberty]

Fixed