From edb07a90195bb677063fe5e741abb598240300c1 Mon Sep 17 00:00:00 2001 From: Samadou OURO-AGOROUKO <101370501+Bakugo90@users.noreply.github.com> Date: Thu, 7 Mar 2024 18:00:15 +0000 Subject: [PATCH] Use extension discriminator for "A" and "M" extensions More support for #4. Using the `extension()` function in `mapping clause encdec` expressions for extensions allows a parser to clearly know when a function is part of an extension (or set of extensions). --- model/riscv_insts_aext.sail | 12 ++++++------ model/riscv_insts_mext.sail | 24 ++++++++++++------------ model/riscv_sys_regs.sail | 6 ++++-- 3 files changed, 22 insertions(+), 20 deletions(-) diff --git a/model/riscv_insts_aext.sail b/model/riscv_insts_aext.sail index 3bf44b8f5..f7ef3c846 100644 --- a/model/riscv_insts_aext.sail +++ b/model/riscv_insts_aext.sail @@ -43,8 +43,8 @@ function amo_width_valid(size : word_width) -> bool = { /* ****************************************************************** */ union clause ast = LOADRES : (bool, bool, regidx, word_width, regidx) -mapping clause encdec = LOADRES(aq, rl, rs1, size, rd) if haveZalrsc() & amo_width_valid(size) - <-> 0b00010 @ bool_bits(aq) @ bool_bits(rl) @ 0b00000 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveZalrsc() & amo_width_valid(size) +mapping clause encdec = LOADRES(aq, rl, rs1, size, rd) if extension("Zalrsc") & amo_width_valid(size) + <-> 0b00010 @ bool_bits(aq) @ bool_bits(rl) @ 0b00000 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if extension("Zalrsc") & amo_width_valid(size) /* We could set load-reservations on physical or virtual addresses. @@ -88,8 +88,8 @@ mapping clause assembly = LOADRES(aq, rl, rs1, size, rd) /* ****************************************************************** */ union clause ast = STORECON : (bool, bool, regidx, regidx, word_width, regidx) -mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd) if haveZalrsc() & amo_width_valid(size) - <-> 0b00011 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveZalrsc() & amo_width_valid(size) +mapping clause encdec = STORECON(aq, rl, rs2, rs1, size, rd) if extension("Zalrsc") & amo_width_valid(size) + <-> 0b00011 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if extension("Zalrsc") & amo_width_valid(size) /* NOTE: Currently, we only EA if address translation is successful. This may need revisiting. */ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = { @@ -163,8 +163,8 @@ mapping encdec_amoop : amoop <-> bits(5) = { AMOMAXU <-> 0b11100 } -mapping clause encdec = AMO(op, aq, rl, rs2, rs1, size, rd) if haveZaamo() & amo_width_valid(size) - <-> encdec_amoop(op) @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if haveZaamo() & amo_width_valid(size) +mapping clause encdec = AMO(op, aq, rl, rs2, rs1, size, rd) if extension("Zaamo") & amo_width_valid(size) + <-> encdec_amoop(op) @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if extension("Zaamo") & amo_width_valid(size) /* NOTE: Currently, we only EA if address translation is successful. This may need revisiting. */ diff --git a/model/riscv_insts_mext.sail b/model/riscv_insts_mext.sail index cfac3bb31..27483be17 100644 --- a/model/riscv_insts_mext.sail +++ b/model/riscv_insts_mext.sail @@ -20,8 +20,8 @@ mapping encdec_mul_op : mul_op <-> bits(3) = { struct { high = true, signed_rs1 = false, signed_rs2 = false } <-> 0b011 } -mapping clause encdec = MUL(rs2, rs1, rd, mul_op) if haveMulDiv() | haveZmmul() - <-> 0b0000001 @ rs2 @ rs1 @ encdec_mul_op(mul_op) @ rd @ 0b0110011 if haveMulDiv() | haveZmmul() +mapping clause encdec = MUL(rs2, rs1, rd, mul_op) if extension("M") | extension("Zmmul") + <-> 0b0000001 @ rs2 @ rs1 @ encdec_mul_op(mul_op) @ rd @ 0b0110011 if extension("M") | extension("Zmmul") function clause execute (MUL(rs2, rs1, rd, mul_op)) = { let rs1_val = X(rs1); @@ -49,8 +49,8 @@ mapping clause assembly = MUL(rs2, rs1, rd, mul_op) /* ****************************************************************** */ union clause ast = DIV : (regidx, regidx, regidx, bool) -mapping clause encdec = DIV(rs2, rs1, rd, s) if haveMulDiv() - <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0110011 if haveMulDiv() +mapping clause encdec = DIV(rs2, rs1, rd, s) if extension("M") + <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0110011 if extension("M") function clause execute (DIV(rs2, rs1, rd, s)) = { let rs1_val = X(rs1); @@ -75,8 +75,8 @@ mapping clause assembly = DIV(rs2, rs1, rd, s) /* ****************************************************************** */ union clause ast = REM : (regidx, regidx, regidx, bool) -mapping clause encdec = REM(rs2, rs1, rd, s) if haveMulDiv() - <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0110011 if haveMulDiv() +mapping clause encdec = REM(rs2, rs1, rd, s) if extension("M") + <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0110011 if extension("M") function clause execute (REM(rs2, rs1, rd, s)) = { let rs1_val = X(rs1); @@ -96,9 +96,9 @@ mapping clause assembly = REM(rs2, rs1, rd, s) union clause ast = MULW : (regidx, regidx, regidx) mapping clause encdec = MULW(rs2, rs1, rd) - if sizeof(xlen) == 64 & (haveMulDiv() | haveZmmul()) + if sizeof(xlen) == 64 & (extension("M") | extension("Zmmul")) <-> 0b0000001 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011 - if sizeof(xlen) == 64 & (haveMulDiv() | haveZmmul()) + if sizeof(xlen) == 64 & (extension("M") | extension("Zmmul")) function clause execute (MULW(rs2, rs1, rd)) = { let rs1_val = X(rs1)[31..0]; @@ -121,9 +121,9 @@ mapping clause assembly = MULW(rs2, rs1, rd) union clause ast = DIVW : (regidx, regidx, regidx, bool) mapping clause encdec = DIVW(rs2, rs1, rd, s) - if sizeof(xlen) == 64 & haveMulDiv() + if sizeof(xlen) == 64 & extension("M") <-> 0b0000001 @ rs2 @ rs1 @ 0b10 @ bool_not_bits(s) @ rd @ 0b0111011 - if sizeof(xlen) == 64 & haveMulDiv() + if sizeof(xlen) == 64 & extension("M") function clause execute (DIVW(rs2, rs1, rd, s)) = { let rs1_val = X(rs1)[31..0]; @@ -146,9 +146,9 @@ mapping clause assembly = DIVW(rs2, rs1, rd, s) union clause ast = REMW : (regidx, regidx, regidx, bool) mapping clause encdec = REMW(rs2, rs1, rd, s) - if sizeof(xlen) == 64 & haveMulDiv() + if sizeof(xlen) == 64 & extension("M") <-> 0b0000001 @ rs2 @ rs1 @ 0b11 @ bool_not_bits(s) @ rd @ 0b0111011 - if sizeof(xlen) == 64 & haveMulDiv() + if sizeof(xlen) == 64 & extension("M") function clause execute (REMW(rs2, rs1, rd, s)) = { let rs1_val = X(rs1)[31..0]; diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index e59378460..c803b75a4 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -928,15 +928,17 @@ val extension : (string) -> bool function extension(ext) = { match ext { - "A" => misa.A() == 0b1, + "A" => misa[A] == 0b1, "C" => misa.C() == 0b1, "D" => (misa.D() == 0b1) & (mstatus.FS() != 0b00), "F" => (misa.F() == 0b1) & (mstatus.FS() != 0b00), - "M" => misa.M() == 0b1, + "M" => misa[A] == 0b1, "N" => misa.N() == 0b1, "U" => misa.U() == 0b1, "S" => misa.S() == 0b1, "V" => (misa.V() == 0b1) & (mstatus.VS() != 0b00), + "Zaamo" => haveAtomics(), + "Zalrsc" => haveAtomics(), "Zba" => true, "Zbb" => true, "Zbc" => true,