example.vcd

$date
	Mon Jul 29 17:26:18 2019
$end
$version
	ModelSim Version 10.5b
$end
$timescale
	1ns
$end

$scope module encoder_8b_10b_testbench $end
$var wire 1 ! s_clk_int $end
$var wire 1 " s_rst_int $end
$var wire 1 # s_datain_int [7] $end
$var wire 1 $ s_datain_int [6] $end
$var wire 1 % s_datain_int [5] $end
$var wire 1 & s_datain_int [4] $end
$var wire 1 ' s_datain_int [3] $end
$var wire 1 ( s_datain_int [2] $end
$var wire 1 ) s_datain_int [1] $end
$var wire 1 * s_datain_int [0] $end
$var wire 1 + s_rd_in_int [1] $end
$var wire 1 , s_rd_in_int [0] $end
$var wire 1 - s_dataout_int [9] $end
$var wire 1 . s_dataout_int [8] $end
$var wire 1 / s_dataout_int [7] $end
$var wire 1 0 s_dataout_int [6] $end
$var wire 1 1 s_dataout_int [5] $end
$var wire 1 2 s_dataout_int [4] $end
$var wire 1 3 s_dataout_int [3] $end
$var wire 1 4 s_dataout_int [2] $end
$var wire 1 5 s_dataout_int [1] $end
$var wire 1 6 s_dataout_int [0] $end
$var wire 1 7 s_dataout_valid_int $end
$var wire 1 8 s_rd_out_int [1] $end
$var wire 1 9 s_rd_out_int [0] $end
$var wire 1 : s_dataout_kerr_int $end
$var wire 1 ; s_datain_k_int $end
$var wire 1 < s_datain_valid_int $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0!
0"
07
0:
x;
x<
x#
x$
x%
x&
x'
x(
x)
x*
1+
0,
0-
0.
0/
00
01
02
03
04
05
06
18
09
$end
#5
1!
#6
1<
1;
1#
0$
1%
1&
1'
1(
0)
0*
1"
19
08
#10
0!
#15
1!
17
14
13
12
11
10
1.
#16
1*
0'
0&
0%
1$
0;
09
18
#20
0!
#25
1!
16
03
02
00
1/
#26
0+
1,
1;
0$
1%
1&
1'
0*
19
08
09
18
#30
0!
#35
1!
15
04
01
0.
1-
#36
1*
0'
0&
0%
1$
0;
19
08
#40
0!
#45
1!
05
14
11
1.
0-
#46
0<
1;
0$
1%
1&
1'
0*
#50
0!
#55
1!
07
#56
1*
0'
0&
0%
1$
0;
#60
0!
#65
1!
#70
0!
#75
1!
#80
0!
#85
1!
#90
0!
#95
1!
#100
0!