From 29b09fa17dc9a6d9e06a754900e4d65ca69a019a Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 13:24:41 +0200 Subject: [PATCH 01/30] generate bindings --- .github/workflows/cross.yaml | 4 +- build.rs | 50 +- src/bindings_aarch64_linux_android.rs | 632 ++++++++++++++++ src/bindings_aarch64_pc_windows_msvc.rs | 681 +++++++++++++++++ src/bindings_aarch64_unknown_linux_gnu.rs | 632 ++++++++++++++++ src/bindings_armv7_unknown_linux_gnueabihf.rs | 646 ++++++++++++++++ ....rs => bindings_x86_64_pc_windows_msvc.rs} | 0 src/bindings_x86_64_unknown_freebsd.rs | 699 +++++++++++++++++ src/bindings_x86_64_unknown_linux_gnu.rs | 701 ++++++++++++++++++ src/lib.rs | 109 ++- 10 files changed, 4123 insertions(+), 31 deletions(-) create mode 100644 src/bindings_aarch64_linux_android.rs create mode 100644 src/bindings_aarch64_pc_windows_msvc.rs create mode 100644 src/bindings_aarch64_unknown_linux_gnu.rs create mode 100644 src/bindings_armv7_unknown_linux_gnueabihf.rs rename src/{bindings.rs => bindings_x86_64_pc_windows_msvc.rs} (100%) create mode 100644 src/bindings_x86_64_unknown_freebsd.rs create mode 100644 src/bindings_x86_64_unknown_linux_gnu.rs diff --git a/.github/workflows/cross.yaml b/.github/workflows/cross.yaml index 7dba36d..87bff05 100644 --- a/.github/workflows/cross.yaml +++ b/.github/workflows/cross.yaml @@ -23,11 +23,13 @@ jobs: matrix: target: - x86_64-unknown-linux-gnu - - x86_64-apple-darwin + # - x86_64-apple-darwin - x86_64-pc-windows-msvc - x86_64-unknown-freebsd - aarch64-linux-android - aarch64-unknown-linux-gnu + - aarch64-pc-windows-msvc + # - aarch64-apple-darwin - armv7-unknown-linux-gnueabihf include: diff --git a/build.rs b/build.rs index edb4199..0dbfb5e 100644 --- a/build.rs +++ b/build.rs @@ -77,6 +77,19 @@ const MACH_ARM_SRCS: &[&str] = &["src/arm/mach/init.c"]; const FREEBSD_X86_SRCS: &[&str] = &["src/x86/freebsd/init.c"]; +/// Targets for which bindings will be generated. +const BINDGEN_SUPPORTED_TARGETS: &[&str] = &[ + "x86_64-unknown-linux-gnu", + // "x86_64-apple-darwin", + "x86_64-pc-windows-msvc", + "x86_64-unknown-freebsd", + "aarch64-linux-android", + "aarch64-unknown-linux-gnu", + "aarch64-pc-windows-msvc", + // "aarch64-apple-darwin", + "armv7-unknown-linux-gnueabihf", +]; + fn main() { let mut build = cc::Build::new(); @@ -134,25 +147,30 @@ fn main() { build.compile("cpuinfo"); - #[cfg(feature = "generate_bindings")] - generate_bindings("src/bindings.rs") + generate_bindings(); } #[cfg(feature = "generate_bindings")] -fn generate_bindings(output_file: &str) { - let bindings = bindgen::Builder::default() - .header("vendor/cpuinfo/include/cpuinfo.h") - .raw_line("#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)]") - .raw_line("#![allow(dead_code)]") - .clang_args(&["-xc++", "-std=c++11"]) - .layout_tests(false) - .generate() - .expect("Unable to generate bindings!"); - - bindings - .write_to_file(std::path::Path::new(output_file)) - .expect("Unable to write bindings!"); +fn generate_bindings() { + for target in BINDGEN_SUPPORTED_TARGETS { + let t = target.replace("-", "_"); + let output_file = format!("src/bindings_{t}.rs"); + + let bindings = bindgen::Builder::default() + .header("vendor/cpuinfo/include/cpuinfo.h") + .raw_line("#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)]") + .raw_line("#![allow(dead_code)]") + .clang_arg(format!("--target={target}")) + .clang_args(&["-xc++", "-std=c++11"]) + .layout_tests(false) + .generate() + .expect("Unable to generate bindings!"); + + bindings + .write_to_file(std::path::Path::new(&output_file)) + .expect("Unable to write bindings!"); + } } #[cfg(not(feature = "generate_bindings"))] -fn generate_bindings(_: &str) {} +fn generate_bindings() {} diff --git a/src/bindings_aarch64_linux_android.rs b/src/bindings_aarch64_linux_android.rs new file mode 100644 index 0000000..f3e4247 --- /dev/null +++ b/src/bindings_aarch64_linux_android.rs @@ -0,0 +1,632 @@ +/* automatically generated by rust-bindgen 0.69.4 */ + +#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] +#![allow(dead_code)] + +pub const CPUINFO_ARCH_ARM64: u32 = 1; +pub const CPUINFO_ARCH_X86: u32 = 0; +pub const CPUINFO_ARCH_X86_64: u32 = 0; +pub const CPUINFO_ARCH_ARM: u32 = 0; +pub const CPUINFO_ARCH_PPC64: u32 = 0; +pub const CPUINFO_ARCH_ASMJS: u32 = 0; +pub const CPUINFO_ARCH_WASM: u32 = 0; +pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; +pub const CPUINFO_ARCH_RISCV32: u32 = 0; +pub const CPUINFO_ARCH_RISCV64: u32 = 0; +pub const CPUINFO_CACHE_UNIFIED: u32 = 1; +pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; +pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; +pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; +pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; +pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; +pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; +pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; +pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; +pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; +pub type int_least64_t = i64; +pub type uint_least64_t = u64; +pub type int_fast64_t = i64; +pub type uint_fast64_t = u64; +pub type int_least32_t = i32; +pub type uint_least32_t = u32; +pub type int_fast32_t = i32; +pub type uint_fast32_t = u32; +pub type int_least16_t = i16; +pub type uint_least16_t = u16; +pub type int_fast16_t = i16; +pub type uint_fast16_t = u16; +pub type int_least8_t = i8; +pub type uint_least8_t = u8; +pub type int_fast8_t = i8; +pub type uint_fast8_t = u8; +pub type intmax_t = ::std::os::raw::c_long; +pub type uintmax_t = ::std::os::raw::c_ulong; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cache { + #[doc = " Cache size in bytes"] + pub size: u32, + #[doc = " Number of ways of associativity"] + pub associativity: u32, + #[doc = " Number of sets"] + pub sets: u32, + #[doc = " Number of partitions"] + pub partitions: u32, + #[doc = " Line size in bytes"] + pub line_size: u32, + #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] + pub flags: u32, + #[doc = " Index of the first logical processor that shares this cache"] + pub processor_start: u32, + #[doc = " Number of logical processors that share this cache"] + pub processor_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_trace_cache { + pub uops: u32, + pub associativity: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_tlb { + pub entries: u32, + pub associativity: u32, + pub pages: u64, +} +#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] +pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; +#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] +pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; +#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; +#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; +#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; +#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; +#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; +#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; +#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; +#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; +#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; +#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] +pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; +#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; +#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; +#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; +#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] +pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; +#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] +pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; +#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; +#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; +#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; +#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; +#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; +#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; +#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] +pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; +#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] +pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; +#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] +pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; +#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] +pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; +#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] +pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; +#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] +pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; +#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] +pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; +#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] +pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; +#[doc = " Vendor of processor core design"] +pub type cpuinfo_vendor = ::std::os::raw::c_uint; +#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] +pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; +#[doc = " Pentium and Pentium MMX microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; +#[doc = " Intel Quark microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; +#[doc = " Pentium Pro, Pentium II, and Pentium III."] +pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; +#[doc = " Pentium M."] +pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; +#[doc = " Intel Core microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; +#[doc = " Intel Core 2 microarchitecture on 65 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; +#[doc = " Intel Core 2 microarchitecture on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; +#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; +#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; +#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; +#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; +#[doc = " Intel Broadwell microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; +#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; +#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] +pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; +#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; +#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; +#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; +#[doc = " Pentium 4 with Prescott and later cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; +#[doc = " Intel Atom on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; +#[doc = " Intel Atom on 32 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; +#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; +#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; +#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; +#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; +#[doc = " Intel Knights Ferry HPC boards."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; +#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; +#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; +#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; +#[doc = " Intel Knights Mill Xeon Phi."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; +#[doc = " Intel/Marvell XScale series."] +pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; +#[doc = " AMD K5."] +pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; +#[doc = " AMD K6 and alike."] +pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; +#[doc = " AMD Athlon and Duron."] +pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; +#[doc = " AMD Athlon 64, Opteron 64."] +pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; +#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] +pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; +#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; +#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; +#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; +#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; +#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; +#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; +#[doc = " AMD Zen 3 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; +#[doc = " AMD Zen 4 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; +#[doc = " NSC Geode and AMD Geode GX and LX."] +pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; +#[doc = " AMD Bobcat mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; +#[doc = " AMD Jaguar mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; +#[doc = " AMD Puma mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; +#[doc = " ARM7 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; +#[doc = " ARM9 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; +#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; +#[doc = " ARM Cortex-A5."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; +#[doc = " ARM Cortex-A7."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; +#[doc = " ARM Cortex-A8."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; +#[doc = " ARM Cortex-A9."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; +#[doc = " ARM Cortex-A12."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; +#[doc = " ARM Cortex-A15."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; +#[doc = " ARM Cortex-A17."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; +#[doc = " ARM Cortex-A32."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; +#[doc = " ARM Cortex-A35."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; +#[doc = " ARM Cortex-A53."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; +#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; +#[doc = " ARM Cortex-A55."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; +#[doc = " ARM Cortex-A57."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; +#[doc = " ARM Cortex-A65."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; +#[doc = " ARM Cortex-A72."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; +#[doc = " ARM Cortex-A73."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; +#[doc = " ARM Cortex-A75."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; +#[doc = " ARM Cortex-A76."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; +#[doc = " ARM Cortex-A77."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; +#[doc = " ARM Cortex-A78."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; +#[doc = " ARM Neoverse N1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; +#[doc = " ARM Neoverse E1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; +#[doc = " ARM Neoverse V1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; +#[doc = " ARM Neoverse N2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; +#[doc = " ARM Neoverse V2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; +#[doc = " ARM Cortex-X1."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; +#[doc = " ARM Cortex-X2."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; +#[doc = " ARM Cortex-X3."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; +#[doc = " ARM Cortex-A510."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; +#[doc = " ARM Cortex-A710."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; +#[doc = " ARM Cortex-A715."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; +#[doc = " Qualcomm Scorpion."] +pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; +#[doc = " Qualcomm Krait."] +pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; +#[doc = " Qualcomm Kryo."] +pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; +#[doc = " Qualcomm Falkor."] +pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; +#[doc = " Qualcomm Saphira."] +pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; +#[doc = " Nvidia Denver."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; +#[doc = " Nvidia Denver 2."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; +#[doc = " Nvidia Carmel."] +pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; +#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; +#[doc = " Apple A6 and A6X processors."] +pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; +#[doc = " Apple A7 processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; +#[doc = " Apple A8 and A8X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; +#[doc = " Apple A9 and A9X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; +#[doc = " Apple A10 and A10X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; +#[doc = " Apple A11 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; +#[doc = " Apple A11 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; +#[doc = " Apple A12 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; +#[doc = " Apple A12 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; +#[doc = " Apple A13 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; +#[doc = " Apple A13 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; +#[doc = " Apple A14 / M1 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; +#[doc = " Apple A14 / M1 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; +#[doc = " Apple A15 / M2 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; +#[doc = " Apple A15 / M2 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; +#[doc = " Cavium ThunderX."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; +#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; +#[doc = " Marvell PJ4."] +pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; +#[doc = " Broadcom Brahma B15."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; +#[doc = " Broadcom Brahma B53."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; +#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] +pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; +#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] +pub type cpuinfo_uarch = ::std::os::raw::c_uint; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor { + #[doc = " SMT (hyperthread) ID within a core"] + pub smt_id: u32, + #[doc = " Core containing this logical processor"] + pub core: *const cpuinfo_core, + #[doc = " Cluster of cores containing this logical processor"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this logical processor"] + pub package: *const cpuinfo_package, + #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in\n /sys/devices/system/cpu/cpu/\n - Bit in the cpu_set_t identifies this logical processor"] + pub linux_id: ::std::os::raw::c_int, + pub cache: cpuinfo_processor__bindgen_ty_1, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor__bindgen_ty_1 { + #[doc = " Level 1 instruction cache"] + pub l1i: *const cpuinfo_cache, + #[doc = " Level 1 data cache"] + pub l1d: *const cpuinfo_cache, + #[doc = " Level 2 unified or data cache"] + pub l2: *const cpuinfo_cache, + #[doc = " Level 3 unified or data cache"] + pub l3: *const cpuinfo_cache, + #[doc = " Level 4 unified or data cache"] + pub l4: *const cpuinfo_cache, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_core { + #[doc = " Index of the first logical processor on this core."] + pub processor_start: u32, + #[doc = " Number of logical processors on this core"] + pub processor_count: u32, + #[doc = " Core ID within a package"] + pub core_id: u32, + #[doc = " Cluster containing this core"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this core."] + pub package: *const cpuinfo_package, + #[doc = " Vendor of the CPU microarchitecture for this core"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture for this core"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) for this core"] + pub midr: u32, + #[doc = " Clock rate (non-Turbo) of the core, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cluster { + #[doc = " Index of the first logical processor in the cluster"] + pub processor_start: u32, + #[doc = " Number of logical processors in the cluster"] + pub processor_count: u32, + #[doc = " Index of the first core in the cluster"] + pub core_start: u32, + #[doc = " Number of cores on the cluster"] + pub core_count: u32, + #[doc = " Cluster ID within a package"] + pub cluster_id: u32, + #[doc = " Physical package containing the cluster"] + pub package: *const cpuinfo_package, + #[doc = " CPU microarchitecture vendor of the cores in the cluster"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture of the cores in the cluster"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) of the cores in the cluster"] + pub midr: u32, + #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_package { + #[doc = " SoC or processor chip model name"] + pub name: [::std::os::raw::c_char; 48usize], + #[doc = " Index of the first logical processor on this physical package"] + pub processor_start: u32, + #[doc = " Number of logical processors on this physical package"] + pub processor_count: u32, + #[doc = " Index of the first core on this physical package"] + pub core_start: u32, + #[doc = " Number of cores on this physical package"] + pub core_count: u32, + #[doc = " Index of the first cluster of cores on this physical package"] + pub cluster_start: u32, + #[doc = " Number of clusters of cores on this physical package"] + pub cluster_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_uarch_info { + #[doc = " Type of CPU microarchitecture"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) for the microarchitecture"] + pub midr: u32, + #[doc = " Number of logical processors with the microarchitecture"] + pub processor_count: u32, + #[doc = " Number of cores with the microarchitecture"] + pub core_count: u32, +} +extern "C" { + pub fn cpuinfo_initialize() -> bool; +} +extern "C" { + pub fn cpuinfo_deinitialize(); +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_arm_isa { + pub atomics: bool, + pub bf16: bool, + pub sve: bool, + pub sve2: bool, + pub i8mm: bool, + pub rdm: bool, + pub fp16arith: bool, + pub dot: bool, + pub jscvt: bool, + pub fcma: bool, + pub fhm: bool, + pub aes: bool, + pub sha1: bool, + pub sha2: bool, + pub pmull: bool, + pub crc32: bool, +} +extern "C" { + pub static mut cpuinfo_isa: cpuinfo_arm_isa; +} +extern "C" { + pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_cores() -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_packages() -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processors_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_cores_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_clusters_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_packages_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_uarchs_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l2_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l3_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l4_caches_count() -> u32; +} +extern "C" { + #[doc = " Returns upper bound on cache size."] + pub fn cpuinfo_get_max_cache_size() -> u32; +} +extern "C" { + #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] + pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; +} +extern "C" { + #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] + pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index() -> u32; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; +} diff --git a/src/bindings_aarch64_pc_windows_msvc.rs b/src/bindings_aarch64_pc_windows_msvc.rs new file mode 100644 index 0000000..5c568f2 --- /dev/null +++ b/src/bindings_aarch64_pc_windows_msvc.rs @@ -0,0 +1,681 @@ +/* automatically generated by rust-bindgen 0.69.4 */ + +#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] +#![allow(dead_code)] + +pub const _VCRT_COMPILER_PREPROCESSOR: u32 = 1; +pub const _SAL_VERSION: u32 = 20; +pub const __SAL_H_VERSION: u32 = 180000000; +pub const _USE_DECLSPECS_FOR_SAL: u32 = 0; +pub const _USE_ATTRIBUTES_FOR_SAL: u32 = 0; +pub const _CRT_PACKING: u32 = 8; +pub const _VA_ALIGN: u32 = 8; +pub const _HAS_EXCEPTIONS: u32 = 1; +pub const NULL: u32 = 0; +pub const _HAS_CXX17: u32 = 0; +pub const _HAS_CXX20: u32 = 0; +pub const _HAS_CXX23: u32 = 0; +pub const _HAS_NODISCARD: u32 = 1; +pub const WCHAR_MIN: u32 = 0; +pub const WCHAR_MAX: u32 = 65535; +pub const WINT_MIN: u32 = 0; +pub const WINT_MAX: u32 = 65535; +pub const CPUINFO_ARCH_ARM64: u32 = 1; +pub const CPUINFO_ARCH_X86: u32 = 0; +pub const CPUINFO_ARCH_X86_64: u32 = 0; +pub const CPUINFO_ARCH_ARM: u32 = 0; +pub const CPUINFO_ARCH_PPC64: u32 = 0; +pub const CPUINFO_ARCH_ASMJS: u32 = 0; +pub const CPUINFO_ARCH_WASM: u32 = 0; +pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; +pub const CPUINFO_ARCH_RISCV32: u32 = 0; +pub const CPUINFO_ARCH_RISCV64: u32 = 0; +pub const CPUINFO_CACHE_UNIFIED: u32 = 1; +pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; +pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; +pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; +pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; +pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; +pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; +pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; +pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; +pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; +pub type va_list = *mut ::std::os::raw::c_char; +extern "C" { + pub fn __va_start(arg1: *mut va_list, ...); +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct __vcrt_va_list_is_reference { + pub _address: u8, +} +pub const __vcrt_va_list_is_reference___the_value: __vcrt_va_list_is_reference__bindgen_ty_1 = + false; +pub type __vcrt_va_list_is_reference__bindgen_ty_1 = bool; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct __vcrt_assert_va_start_is_not_reference { + pub _address: u8, +} +pub type __vcrt_bool = bool; +extern "C" { + pub fn __security_init_cookie(); +} +extern "C" { + pub fn __security_check_cookie(_StackCookie: usize); +} +extern "C" { + pub fn __report_gsfailure(_StackCookie: usize) -> !; +} +extern "C" { + pub static mut __security_cookie: usize; +} +pub type int_least8_t = ::std::os::raw::c_schar; +pub type int_least16_t = ::std::os::raw::c_short; +pub type int_least32_t = ::std::os::raw::c_int; +pub type int_least64_t = ::std::os::raw::c_longlong; +pub type uint_least8_t = ::std::os::raw::c_uchar; +pub type uint_least16_t = ::std::os::raw::c_ushort; +pub type uint_least32_t = ::std::os::raw::c_uint; +pub type uint_least64_t = ::std::os::raw::c_ulonglong; +pub type int_fast8_t = ::std::os::raw::c_schar; +pub type int_fast16_t = ::std::os::raw::c_int; +pub type int_fast32_t = ::std::os::raw::c_int; +pub type int_fast64_t = ::std::os::raw::c_longlong; +pub type uint_fast8_t = ::std::os::raw::c_uchar; +pub type uint_fast16_t = ::std::os::raw::c_uint; +pub type uint_fast32_t = ::std::os::raw::c_uint; +pub type uint_fast64_t = ::std::os::raw::c_ulonglong; +pub type intmax_t = ::std::os::raw::c_longlong; +pub type uintmax_t = ::std::os::raw::c_ulonglong; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cache { + #[doc = " Cache size in bytes"] + pub size: u32, + #[doc = " Number of ways of associativity"] + pub associativity: u32, + #[doc = " Number of sets"] + pub sets: u32, + #[doc = " Number of partitions"] + pub partitions: u32, + #[doc = " Line size in bytes"] + pub line_size: u32, + #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] + pub flags: u32, + #[doc = " Index of the first logical processor that shares this cache"] + pub processor_start: u32, + #[doc = " Number of logical processors that share this cache"] + pub processor_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_trace_cache { + pub uops: u32, + pub associativity: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_tlb { + pub entries: u32, + pub associativity: u32, + pub pages: u64, +} +#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] +pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; +#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] +pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; +#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; +#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; +#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; +#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; +#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; +#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; +#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; +#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; +#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; +#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] +pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; +#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; +#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; +#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; +#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] +pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; +#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] +pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; +#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; +#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; +#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; +#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; +#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; +#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; +#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] +pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; +#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] +pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; +#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] +pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; +#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] +pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; +#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] +pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; +#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] +pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; +#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] +pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; +#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] +pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; +#[doc = " Vendor of processor core design"] +pub type cpuinfo_vendor = ::std::os::raw::c_int; +#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] +pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; +#[doc = " Pentium and Pentium MMX microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; +#[doc = " Intel Quark microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; +#[doc = " Pentium Pro, Pentium II, and Pentium III."] +pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; +#[doc = " Pentium M."] +pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; +#[doc = " Intel Core microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; +#[doc = " Intel Core 2 microarchitecture on 65 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; +#[doc = " Intel Core 2 microarchitecture on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; +#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; +#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; +#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; +#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; +#[doc = " Intel Broadwell microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; +#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; +#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] +pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; +#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; +#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; +#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; +#[doc = " Pentium 4 with Prescott and later cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; +#[doc = " Intel Atom on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; +#[doc = " Intel Atom on 32 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; +#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; +#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; +#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; +#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; +#[doc = " Intel Knights Ferry HPC boards."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; +#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; +#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; +#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; +#[doc = " Intel Knights Mill Xeon Phi."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; +#[doc = " Intel/Marvell XScale series."] +pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; +#[doc = " AMD K5."] +pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; +#[doc = " AMD K6 and alike."] +pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; +#[doc = " AMD Athlon and Duron."] +pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; +#[doc = " AMD Athlon 64, Opteron 64."] +pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; +#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] +pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; +#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; +#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; +#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; +#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; +#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; +#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; +#[doc = " AMD Zen 3 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; +#[doc = " AMD Zen 4 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; +#[doc = " NSC Geode and AMD Geode GX and LX."] +pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; +#[doc = " AMD Bobcat mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; +#[doc = " AMD Jaguar mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; +#[doc = " AMD Puma mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; +#[doc = " ARM7 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; +#[doc = " ARM9 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; +#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; +#[doc = " ARM Cortex-A5."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; +#[doc = " ARM Cortex-A7."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; +#[doc = " ARM Cortex-A8."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; +#[doc = " ARM Cortex-A9."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; +#[doc = " ARM Cortex-A12."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; +#[doc = " ARM Cortex-A15."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; +#[doc = " ARM Cortex-A17."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; +#[doc = " ARM Cortex-A32."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; +#[doc = " ARM Cortex-A35."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; +#[doc = " ARM Cortex-A53."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; +#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; +#[doc = " ARM Cortex-A55."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; +#[doc = " ARM Cortex-A57."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; +#[doc = " ARM Cortex-A65."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; +#[doc = " ARM Cortex-A72."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; +#[doc = " ARM Cortex-A73."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; +#[doc = " ARM Cortex-A75."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; +#[doc = " ARM Cortex-A76."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; +#[doc = " ARM Cortex-A77."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; +#[doc = " ARM Cortex-A78."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; +#[doc = " ARM Neoverse N1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; +#[doc = " ARM Neoverse E1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; +#[doc = " ARM Neoverse V1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; +#[doc = " ARM Neoverse N2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; +#[doc = " ARM Neoverse V2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; +#[doc = " ARM Cortex-X1."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; +#[doc = " ARM Cortex-X2."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; +#[doc = " ARM Cortex-X3."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; +#[doc = " ARM Cortex-A510."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; +#[doc = " ARM Cortex-A710."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; +#[doc = " ARM Cortex-A715."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; +#[doc = " Qualcomm Scorpion."] +pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; +#[doc = " Qualcomm Krait."] +pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; +#[doc = " Qualcomm Kryo."] +pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; +#[doc = " Qualcomm Falkor."] +pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; +#[doc = " Qualcomm Saphira."] +pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; +#[doc = " Nvidia Denver."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; +#[doc = " Nvidia Denver 2."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; +#[doc = " Nvidia Carmel."] +pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; +#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; +#[doc = " Apple A6 and A6X processors."] +pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; +#[doc = " Apple A7 processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; +#[doc = " Apple A8 and A8X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; +#[doc = " Apple A9 and A9X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; +#[doc = " Apple A10 and A10X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; +#[doc = " Apple A11 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; +#[doc = " Apple A11 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; +#[doc = " Apple A12 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; +#[doc = " Apple A12 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; +#[doc = " Apple A13 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; +#[doc = " Apple A13 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; +#[doc = " Apple A14 / M1 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; +#[doc = " Apple A14 / M1 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; +#[doc = " Apple A15 / M2 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; +#[doc = " Apple A15 / M2 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; +#[doc = " Cavium ThunderX."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; +#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; +#[doc = " Marvell PJ4."] +pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; +#[doc = " Broadcom Brahma B15."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; +#[doc = " Broadcom Brahma B53."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; +#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] +pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; +#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] +pub type cpuinfo_uarch = ::std::os::raw::c_int; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor { + #[doc = " SMT (hyperthread) ID within a core"] + pub smt_id: u32, + #[doc = " Core containing this logical processor"] + pub core: *const cpuinfo_core, + #[doc = " Cluster of cores containing this logical processor"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this logical processor"] + pub package: *const cpuinfo_package, + #[doc = " Windows-specific ID for the group containing the logical processor."] + pub windows_group_id: u16, + #[doc = " Windows-specific ID of the logical processor within its group:\n - Bit in the KAFFINITY mask identifies this\n logical processor within its group."] + pub windows_processor_id: u16, + pub cache: cpuinfo_processor__bindgen_ty_1, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor__bindgen_ty_1 { + #[doc = " Level 1 instruction cache"] + pub l1i: *const cpuinfo_cache, + #[doc = " Level 1 data cache"] + pub l1d: *const cpuinfo_cache, + #[doc = " Level 2 unified or data cache"] + pub l2: *const cpuinfo_cache, + #[doc = " Level 3 unified or data cache"] + pub l3: *const cpuinfo_cache, + #[doc = " Level 4 unified or data cache"] + pub l4: *const cpuinfo_cache, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_core { + #[doc = " Index of the first logical processor on this core."] + pub processor_start: u32, + #[doc = " Number of logical processors on this core"] + pub processor_count: u32, + #[doc = " Core ID within a package"] + pub core_id: u32, + #[doc = " Cluster containing this core"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this core."] + pub package: *const cpuinfo_package, + #[doc = " Vendor of the CPU microarchitecture for this core"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture for this core"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) for this core"] + pub midr: u32, + #[doc = " Clock rate (non-Turbo) of the core, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cluster { + #[doc = " Index of the first logical processor in the cluster"] + pub processor_start: u32, + #[doc = " Number of logical processors in the cluster"] + pub processor_count: u32, + #[doc = " Index of the first core in the cluster"] + pub core_start: u32, + #[doc = " Number of cores on the cluster"] + pub core_count: u32, + #[doc = " Cluster ID within a package"] + pub cluster_id: u32, + #[doc = " Physical package containing the cluster"] + pub package: *const cpuinfo_package, + #[doc = " CPU microarchitecture vendor of the cores in the cluster"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture of the cores in the cluster"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) of the cores in the cluster"] + pub midr: u32, + #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_package { + #[doc = " SoC or processor chip model name"] + pub name: [::std::os::raw::c_char; 48usize], + #[doc = " Index of the first logical processor on this physical package"] + pub processor_start: u32, + #[doc = " Number of logical processors on this physical package"] + pub processor_count: u32, + #[doc = " Index of the first core on this physical package"] + pub core_start: u32, + #[doc = " Number of cores on this physical package"] + pub core_count: u32, + #[doc = " Index of the first cluster of cores on this physical package"] + pub cluster_start: u32, + #[doc = " Number of clusters of cores on this physical package"] + pub cluster_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_uarch_info { + #[doc = " Type of CPU microarchitecture"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) for the microarchitecture"] + pub midr: u32, + #[doc = " Number of logical processors with the microarchitecture"] + pub processor_count: u32, + #[doc = " Number of cores with the microarchitecture"] + pub core_count: u32, +} +extern "C" { + pub fn cpuinfo_initialize() -> bool; +} +extern "C" { + pub fn cpuinfo_deinitialize(); +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_arm_isa { + pub atomics: bool, + pub bf16: bool, + pub sve: bool, + pub sve2: bool, + pub i8mm: bool, + pub rdm: bool, + pub fp16arith: bool, + pub dot: bool, + pub jscvt: bool, + pub fcma: bool, + pub fhm: bool, + pub aes: bool, + pub sha1: bool, + pub sha2: bool, + pub pmull: bool, + pub crc32: bool, +} +extern "C" { + pub static mut cpuinfo_isa: cpuinfo_arm_isa; +} +extern "C" { + pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_cores() -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_packages() -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processors_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_cores_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_clusters_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_packages_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_uarchs_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l2_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l3_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l4_caches_count() -> u32; +} +extern "C" { + #[doc = " Returns upper bound on cache size."] + pub fn cpuinfo_get_max_cache_size() -> u32; +} +extern "C" { + #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] + pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; +} +extern "C" { + #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] + pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index() -> u32; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; +} diff --git a/src/bindings_aarch64_unknown_linux_gnu.rs b/src/bindings_aarch64_unknown_linux_gnu.rs new file mode 100644 index 0000000..f3e4247 --- /dev/null +++ b/src/bindings_aarch64_unknown_linux_gnu.rs @@ -0,0 +1,632 @@ +/* automatically generated by rust-bindgen 0.69.4 */ + +#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] +#![allow(dead_code)] + +pub const CPUINFO_ARCH_ARM64: u32 = 1; +pub const CPUINFO_ARCH_X86: u32 = 0; +pub const CPUINFO_ARCH_X86_64: u32 = 0; +pub const CPUINFO_ARCH_ARM: u32 = 0; +pub const CPUINFO_ARCH_PPC64: u32 = 0; +pub const CPUINFO_ARCH_ASMJS: u32 = 0; +pub const CPUINFO_ARCH_WASM: u32 = 0; +pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; +pub const CPUINFO_ARCH_RISCV32: u32 = 0; +pub const CPUINFO_ARCH_RISCV64: u32 = 0; +pub const CPUINFO_CACHE_UNIFIED: u32 = 1; +pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; +pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; +pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; +pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; +pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; +pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; +pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; +pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; +pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; +pub type int_least64_t = i64; +pub type uint_least64_t = u64; +pub type int_fast64_t = i64; +pub type uint_fast64_t = u64; +pub type int_least32_t = i32; +pub type uint_least32_t = u32; +pub type int_fast32_t = i32; +pub type uint_fast32_t = u32; +pub type int_least16_t = i16; +pub type uint_least16_t = u16; +pub type int_fast16_t = i16; +pub type uint_fast16_t = u16; +pub type int_least8_t = i8; +pub type uint_least8_t = u8; +pub type int_fast8_t = i8; +pub type uint_fast8_t = u8; +pub type intmax_t = ::std::os::raw::c_long; +pub type uintmax_t = ::std::os::raw::c_ulong; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cache { + #[doc = " Cache size in bytes"] + pub size: u32, + #[doc = " Number of ways of associativity"] + pub associativity: u32, + #[doc = " Number of sets"] + pub sets: u32, + #[doc = " Number of partitions"] + pub partitions: u32, + #[doc = " Line size in bytes"] + pub line_size: u32, + #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] + pub flags: u32, + #[doc = " Index of the first logical processor that shares this cache"] + pub processor_start: u32, + #[doc = " Number of logical processors that share this cache"] + pub processor_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_trace_cache { + pub uops: u32, + pub associativity: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_tlb { + pub entries: u32, + pub associativity: u32, + pub pages: u64, +} +#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] +pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; +#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] +pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; +#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; +#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; +#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; +#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; +#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; +#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; +#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; +#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; +#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; +#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] +pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; +#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; +#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; +#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; +#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] +pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; +#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] +pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; +#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; +#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; +#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; +#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; +#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; +#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; +#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] +pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; +#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] +pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; +#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] +pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; +#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] +pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; +#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] +pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; +#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] +pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; +#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] +pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; +#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] +pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; +#[doc = " Vendor of processor core design"] +pub type cpuinfo_vendor = ::std::os::raw::c_uint; +#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] +pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; +#[doc = " Pentium and Pentium MMX microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; +#[doc = " Intel Quark microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; +#[doc = " Pentium Pro, Pentium II, and Pentium III."] +pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; +#[doc = " Pentium M."] +pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; +#[doc = " Intel Core microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; +#[doc = " Intel Core 2 microarchitecture on 65 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; +#[doc = " Intel Core 2 microarchitecture on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; +#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; +#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; +#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; +#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; +#[doc = " Intel Broadwell microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; +#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; +#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] +pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; +#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; +#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; +#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; +#[doc = " Pentium 4 with Prescott and later cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; +#[doc = " Intel Atom on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; +#[doc = " Intel Atom on 32 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; +#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; +#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; +#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; +#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; +#[doc = " Intel Knights Ferry HPC boards."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; +#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; +#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; +#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; +#[doc = " Intel Knights Mill Xeon Phi."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; +#[doc = " Intel/Marvell XScale series."] +pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; +#[doc = " AMD K5."] +pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; +#[doc = " AMD K6 and alike."] +pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; +#[doc = " AMD Athlon and Duron."] +pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; +#[doc = " AMD Athlon 64, Opteron 64."] +pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; +#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] +pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; +#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; +#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; +#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; +#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; +#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; +#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; +#[doc = " AMD Zen 3 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; +#[doc = " AMD Zen 4 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; +#[doc = " NSC Geode and AMD Geode GX and LX."] +pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; +#[doc = " AMD Bobcat mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; +#[doc = " AMD Jaguar mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; +#[doc = " AMD Puma mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; +#[doc = " ARM7 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; +#[doc = " ARM9 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; +#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; +#[doc = " ARM Cortex-A5."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; +#[doc = " ARM Cortex-A7."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; +#[doc = " ARM Cortex-A8."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; +#[doc = " ARM Cortex-A9."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; +#[doc = " ARM Cortex-A12."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; +#[doc = " ARM Cortex-A15."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; +#[doc = " ARM Cortex-A17."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; +#[doc = " ARM Cortex-A32."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; +#[doc = " ARM Cortex-A35."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; +#[doc = " ARM Cortex-A53."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; +#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; +#[doc = " ARM Cortex-A55."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; +#[doc = " ARM Cortex-A57."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; +#[doc = " ARM Cortex-A65."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; +#[doc = " ARM Cortex-A72."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; +#[doc = " ARM Cortex-A73."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; +#[doc = " ARM Cortex-A75."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; +#[doc = " ARM Cortex-A76."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; +#[doc = " ARM Cortex-A77."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; +#[doc = " ARM Cortex-A78."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; +#[doc = " ARM Neoverse N1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; +#[doc = " ARM Neoverse E1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; +#[doc = " ARM Neoverse V1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; +#[doc = " ARM Neoverse N2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; +#[doc = " ARM Neoverse V2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; +#[doc = " ARM Cortex-X1."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; +#[doc = " ARM Cortex-X2."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; +#[doc = " ARM Cortex-X3."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; +#[doc = " ARM Cortex-A510."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; +#[doc = " ARM Cortex-A710."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; +#[doc = " ARM Cortex-A715."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; +#[doc = " Qualcomm Scorpion."] +pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; +#[doc = " Qualcomm Krait."] +pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; +#[doc = " Qualcomm Kryo."] +pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; +#[doc = " Qualcomm Falkor."] +pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; +#[doc = " Qualcomm Saphira."] +pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; +#[doc = " Nvidia Denver."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; +#[doc = " Nvidia Denver 2."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; +#[doc = " Nvidia Carmel."] +pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; +#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; +#[doc = " Apple A6 and A6X processors."] +pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; +#[doc = " Apple A7 processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; +#[doc = " Apple A8 and A8X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; +#[doc = " Apple A9 and A9X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; +#[doc = " Apple A10 and A10X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; +#[doc = " Apple A11 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; +#[doc = " Apple A11 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; +#[doc = " Apple A12 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; +#[doc = " Apple A12 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; +#[doc = " Apple A13 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; +#[doc = " Apple A13 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; +#[doc = " Apple A14 / M1 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; +#[doc = " Apple A14 / M1 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; +#[doc = " Apple A15 / M2 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; +#[doc = " Apple A15 / M2 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; +#[doc = " Cavium ThunderX."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; +#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; +#[doc = " Marvell PJ4."] +pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; +#[doc = " Broadcom Brahma B15."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; +#[doc = " Broadcom Brahma B53."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; +#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] +pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; +#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] +pub type cpuinfo_uarch = ::std::os::raw::c_uint; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor { + #[doc = " SMT (hyperthread) ID within a core"] + pub smt_id: u32, + #[doc = " Core containing this logical processor"] + pub core: *const cpuinfo_core, + #[doc = " Cluster of cores containing this logical processor"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this logical processor"] + pub package: *const cpuinfo_package, + #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in\n /sys/devices/system/cpu/cpu/\n - Bit in the cpu_set_t identifies this logical processor"] + pub linux_id: ::std::os::raw::c_int, + pub cache: cpuinfo_processor__bindgen_ty_1, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor__bindgen_ty_1 { + #[doc = " Level 1 instruction cache"] + pub l1i: *const cpuinfo_cache, + #[doc = " Level 1 data cache"] + pub l1d: *const cpuinfo_cache, + #[doc = " Level 2 unified or data cache"] + pub l2: *const cpuinfo_cache, + #[doc = " Level 3 unified or data cache"] + pub l3: *const cpuinfo_cache, + #[doc = " Level 4 unified or data cache"] + pub l4: *const cpuinfo_cache, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_core { + #[doc = " Index of the first logical processor on this core."] + pub processor_start: u32, + #[doc = " Number of logical processors on this core"] + pub processor_count: u32, + #[doc = " Core ID within a package"] + pub core_id: u32, + #[doc = " Cluster containing this core"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this core."] + pub package: *const cpuinfo_package, + #[doc = " Vendor of the CPU microarchitecture for this core"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture for this core"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) for this core"] + pub midr: u32, + #[doc = " Clock rate (non-Turbo) of the core, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cluster { + #[doc = " Index of the first logical processor in the cluster"] + pub processor_start: u32, + #[doc = " Number of logical processors in the cluster"] + pub processor_count: u32, + #[doc = " Index of the first core in the cluster"] + pub core_start: u32, + #[doc = " Number of cores on the cluster"] + pub core_count: u32, + #[doc = " Cluster ID within a package"] + pub cluster_id: u32, + #[doc = " Physical package containing the cluster"] + pub package: *const cpuinfo_package, + #[doc = " CPU microarchitecture vendor of the cores in the cluster"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture of the cores in the cluster"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) of the cores in the cluster"] + pub midr: u32, + #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_package { + #[doc = " SoC or processor chip model name"] + pub name: [::std::os::raw::c_char; 48usize], + #[doc = " Index of the first logical processor on this physical package"] + pub processor_start: u32, + #[doc = " Number of logical processors on this physical package"] + pub processor_count: u32, + #[doc = " Index of the first core on this physical package"] + pub core_start: u32, + #[doc = " Number of cores on this physical package"] + pub core_count: u32, + #[doc = " Index of the first cluster of cores on this physical package"] + pub cluster_start: u32, + #[doc = " Number of clusters of cores on this physical package"] + pub cluster_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_uarch_info { + #[doc = " Type of CPU microarchitecture"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) for the microarchitecture"] + pub midr: u32, + #[doc = " Number of logical processors with the microarchitecture"] + pub processor_count: u32, + #[doc = " Number of cores with the microarchitecture"] + pub core_count: u32, +} +extern "C" { + pub fn cpuinfo_initialize() -> bool; +} +extern "C" { + pub fn cpuinfo_deinitialize(); +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_arm_isa { + pub atomics: bool, + pub bf16: bool, + pub sve: bool, + pub sve2: bool, + pub i8mm: bool, + pub rdm: bool, + pub fp16arith: bool, + pub dot: bool, + pub jscvt: bool, + pub fcma: bool, + pub fhm: bool, + pub aes: bool, + pub sha1: bool, + pub sha2: bool, + pub pmull: bool, + pub crc32: bool, +} +extern "C" { + pub static mut cpuinfo_isa: cpuinfo_arm_isa; +} +extern "C" { + pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_cores() -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_packages() -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processors_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_cores_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_clusters_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_packages_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_uarchs_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l2_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l3_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l4_caches_count() -> u32; +} +extern "C" { + #[doc = " Returns upper bound on cache size."] + pub fn cpuinfo_get_max_cache_size() -> u32; +} +extern "C" { + #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] + pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; +} +extern "C" { + #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] + pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index() -> u32; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; +} diff --git a/src/bindings_armv7_unknown_linux_gnueabihf.rs b/src/bindings_armv7_unknown_linux_gnueabihf.rs new file mode 100644 index 0000000..44c0cb2 --- /dev/null +++ b/src/bindings_armv7_unknown_linux_gnueabihf.rs @@ -0,0 +1,646 @@ +/* automatically generated by rust-bindgen 0.69.4 */ + +#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] +#![allow(dead_code)] + +pub const CPUINFO_ARCH_ARM: u32 = 1; +pub const CPUINFO_ARCH_X86: u32 = 0; +pub const CPUINFO_ARCH_X86_64: u32 = 0; +pub const CPUINFO_ARCH_ARM64: u32 = 0; +pub const CPUINFO_ARCH_PPC64: u32 = 0; +pub const CPUINFO_ARCH_ASMJS: u32 = 0; +pub const CPUINFO_ARCH_WASM: u32 = 0; +pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; +pub const CPUINFO_ARCH_RISCV32: u32 = 0; +pub const CPUINFO_ARCH_RISCV64: u32 = 0; +pub const CPUINFO_CACHE_UNIFIED: u32 = 1; +pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; +pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; +pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; +pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; +pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; +pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; +pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; +pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; +pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; +pub type int_least64_t = i64; +pub type uint_least64_t = u64; +pub type int_fast64_t = i64; +pub type uint_fast64_t = u64; +pub type int_least32_t = i32; +pub type uint_least32_t = u32; +pub type int_fast32_t = i32; +pub type uint_fast32_t = u32; +pub type int_least16_t = i16; +pub type uint_least16_t = u16; +pub type int_fast16_t = i16; +pub type uint_fast16_t = u16; +pub type int_least8_t = i8; +pub type uint_least8_t = u8; +pub type int_fast8_t = i8; +pub type uint_fast8_t = u8; +pub type intmax_t = ::std::os::raw::c_longlong; +pub type uintmax_t = ::std::os::raw::c_ulonglong; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cache { + #[doc = " Cache size in bytes"] + pub size: u32, + #[doc = " Number of ways of associativity"] + pub associativity: u32, + #[doc = " Number of sets"] + pub sets: u32, + #[doc = " Number of partitions"] + pub partitions: u32, + #[doc = " Line size in bytes"] + pub line_size: u32, + #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] + pub flags: u32, + #[doc = " Index of the first logical processor that shares this cache"] + pub processor_start: u32, + #[doc = " Number of logical processors that share this cache"] + pub processor_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_trace_cache { + pub uops: u32, + pub associativity: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_tlb { + pub entries: u32, + pub associativity: u32, + pub pages: u64, +} +#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] +pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; +#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] +pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; +#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; +#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; +#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; +#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; +#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; +#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; +#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; +#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; +#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; +#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] +pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; +#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; +#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; +#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; +#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] +pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; +#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] +pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; +#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; +#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; +#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; +#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; +#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; +#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; +#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] +pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; +#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] +pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; +#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] +pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; +#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] +pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; +#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] +pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; +#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] +pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; +#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] +pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; +#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] +pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; +#[doc = " Vendor of processor core design"] +pub type cpuinfo_vendor = ::std::os::raw::c_uint; +#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] +pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; +#[doc = " Pentium and Pentium MMX microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; +#[doc = " Intel Quark microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; +#[doc = " Pentium Pro, Pentium II, and Pentium III."] +pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; +#[doc = " Pentium M."] +pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; +#[doc = " Intel Core microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; +#[doc = " Intel Core 2 microarchitecture on 65 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; +#[doc = " Intel Core 2 microarchitecture on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; +#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; +#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; +#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; +#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; +#[doc = " Intel Broadwell microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; +#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; +#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] +pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; +#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; +#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; +#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; +#[doc = " Pentium 4 with Prescott and later cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; +#[doc = " Intel Atom on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; +#[doc = " Intel Atom on 32 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; +#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; +#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; +#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; +#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; +#[doc = " Intel Knights Ferry HPC boards."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; +#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; +#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; +#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; +#[doc = " Intel Knights Mill Xeon Phi."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; +#[doc = " Intel/Marvell XScale series."] +pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; +#[doc = " AMD K5."] +pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; +#[doc = " AMD K6 and alike."] +pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; +#[doc = " AMD Athlon and Duron."] +pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; +#[doc = " AMD Athlon 64, Opteron 64."] +pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; +#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] +pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; +#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; +#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; +#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; +#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; +#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; +#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; +#[doc = " AMD Zen 3 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; +#[doc = " AMD Zen 4 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; +#[doc = " NSC Geode and AMD Geode GX and LX."] +pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; +#[doc = " AMD Bobcat mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; +#[doc = " AMD Jaguar mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; +#[doc = " AMD Puma mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; +#[doc = " ARM7 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; +#[doc = " ARM9 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; +#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; +#[doc = " ARM Cortex-A5."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; +#[doc = " ARM Cortex-A7."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; +#[doc = " ARM Cortex-A8."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; +#[doc = " ARM Cortex-A9."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; +#[doc = " ARM Cortex-A12."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; +#[doc = " ARM Cortex-A15."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; +#[doc = " ARM Cortex-A17."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; +#[doc = " ARM Cortex-A32."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; +#[doc = " ARM Cortex-A35."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; +#[doc = " ARM Cortex-A53."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; +#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; +#[doc = " ARM Cortex-A55."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; +#[doc = " ARM Cortex-A57."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; +#[doc = " ARM Cortex-A65."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; +#[doc = " ARM Cortex-A72."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; +#[doc = " ARM Cortex-A73."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; +#[doc = " ARM Cortex-A75."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; +#[doc = " ARM Cortex-A76."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; +#[doc = " ARM Cortex-A77."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; +#[doc = " ARM Cortex-A78."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; +#[doc = " ARM Neoverse N1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; +#[doc = " ARM Neoverse E1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; +#[doc = " ARM Neoverse V1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; +#[doc = " ARM Neoverse N2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; +#[doc = " ARM Neoverse V2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; +#[doc = " ARM Cortex-X1."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; +#[doc = " ARM Cortex-X2."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; +#[doc = " ARM Cortex-X3."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; +#[doc = " ARM Cortex-A510."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; +#[doc = " ARM Cortex-A710."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; +#[doc = " ARM Cortex-A715."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; +#[doc = " Qualcomm Scorpion."] +pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; +#[doc = " Qualcomm Krait."] +pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; +#[doc = " Qualcomm Kryo."] +pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; +#[doc = " Qualcomm Falkor."] +pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; +#[doc = " Qualcomm Saphira."] +pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; +#[doc = " Nvidia Denver."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; +#[doc = " Nvidia Denver 2."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; +#[doc = " Nvidia Carmel."] +pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; +#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; +#[doc = " Apple A6 and A6X processors."] +pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; +#[doc = " Apple A7 processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; +#[doc = " Apple A8 and A8X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; +#[doc = " Apple A9 and A9X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; +#[doc = " Apple A10 and A10X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; +#[doc = " Apple A11 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; +#[doc = " Apple A11 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; +#[doc = " Apple A12 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; +#[doc = " Apple A12 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; +#[doc = " Apple A13 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; +#[doc = " Apple A13 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; +#[doc = " Apple A14 / M1 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; +#[doc = " Apple A14 / M1 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; +#[doc = " Apple A15 / M2 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; +#[doc = " Apple A15 / M2 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; +#[doc = " Cavium ThunderX."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; +#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; +#[doc = " Marvell PJ4."] +pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; +#[doc = " Broadcom Brahma B15."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; +#[doc = " Broadcom Brahma B53."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; +#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] +pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; +#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] +pub type cpuinfo_uarch = ::std::os::raw::c_uint; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor { + #[doc = " SMT (hyperthread) ID within a core"] + pub smt_id: u32, + #[doc = " Core containing this logical processor"] + pub core: *const cpuinfo_core, + #[doc = " Cluster of cores containing this logical processor"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this logical processor"] + pub package: *const cpuinfo_package, + #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in\n /sys/devices/system/cpu/cpu/\n - Bit in the cpu_set_t identifies this logical processor"] + pub linux_id: ::std::os::raw::c_int, + pub cache: cpuinfo_processor__bindgen_ty_1, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor__bindgen_ty_1 { + #[doc = " Level 1 instruction cache"] + pub l1i: *const cpuinfo_cache, + #[doc = " Level 1 data cache"] + pub l1d: *const cpuinfo_cache, + #[doc = " Level 2 unified or data cache"] + pub l2: *const cpuinfo_cache, + #[doc = " Level 3 unified or data cache"] + pub l3: *const cpuinfo_cache, + #[doc = " Level 4 unified or data cache"] + pub l4: *const cpuinfo_cache, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_core { + #[doc = " Index of the first logical processor on this core."] + pub processor_start: u32, + #[doc = " Number of logical processors on this core"] + pub processor_count: u32, + #[doc = " Core ID within a package"] + pub core_id: u32, + #[doc = " Cluster containing this core"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this core."] + pub package: *const cpuinfo_package, + #[doc = " Vendor of the CPU microarchitecture for this core"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture for this core"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) for this core"] + pub midr: u32, + #[doc = " Clock rate (non-Turbo) of the core, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cluster { + #[doc = " Index of the first logical processor in the cluster"] + pub processor_start: u32, + #[doc = " Number of logical processors in the cluster"] + pub processor_count: u32, + #[doc = " Index of the first core in the cluster"] + pub core_start: u32, + #[doc = " Number of cores on the cluster"] + pub core_count: u32, + #[doc = " Cluster ID within a package"] + pub cluster_id: u32, + #[doc = " Physical package containing the cluster"] + pub package: *const cpuinfo_package, + #[doc = " CPU microarchitecture vendor of the cores in the cluster"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture of the cores in the cluster"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) of the cores in the cluster"] + pub midr: u32, + #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_package { + #[doc = " SoC or processor chip model name"] + pub name: [::std::os::raw::c_char; 48usize], + #[doc = " Index of the first logical processor on this physical package"] + pub processor_start: u32, + #[doc = " Number of logical processors on this physical package"] + pub processor_count: u32, + #[doc = " Index of the first core on this physical package"] + pub core_start: u32, + #[doc = " Number of cores on this physical package"] + pub core_count: u32, + #[doc = " Index of the first cluster of cores on this physical package"] + pub cluster_start: u32, + #[doc = " Number of clusters of cores on this physical package"] + pub cluster_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_uarch_info { + #[doc = " Type of CPU microarchitecture"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of Main ID Register (MIDR) for the microarchitecture"] + pub midr: u32, + #[doc = " Number of logical processors with the microarchitecture"] + pub processor_count: u32, + #[doc = " Number of cores with the microarchitecture"] + pub core_count: u32, +} +extern "C" { + pub fn cpuinfo_initialize() -> bool; +} +extern "C" { + pub fn cpuinfo_deinitialize(); +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_arm_isa { + pub thumb: bool, + pub thumb2: bool, + pub thumbee: bool, + pub jazelle: bool, + pub armv5e: bool, + pub armv6: bool, + pub armv6k: bool, + pub armv7: bool, + pub armv7mp: bool, + pub armv8: bool, + pub idiv: bool, + pub vfpv2: bool, + pub vfpv3: bool, + pub d32: bool, + pub fp16: bool, + pub fma: bool, + pub wmmx: bool, + pub wmmx2: bool, + pub neon: bool, + pub rdm: bool, + pub fp16arith: bool, + pub dot: bool, + pub jscvt: bool, + pub fcma: bool, + pub fhm: bool, + pub aes: bool, + pub sha1: bool, + pub sha2: bool, + pub pmull: bool, + pub crc32: bool, +} +extern "C" { + pub static mut cpuinfo_isa: cpuinfo_arm_isa; +} +extern "C" { + pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_cores() -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_packages() -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processors_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_cores_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_clusters_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_packages_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_uarchs_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l2_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l3_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l4_caches_count() -> u32; +} +extern "C" { + #[doc = " Returns upper bound on cache size."] + pub fn cpuinfo_get_max_cache_size() -> u32; +} +extern "C" { + #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] + pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; +} +extern "C" { + #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] + pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index() -> u32; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; +} diff --git a/src/bindings.rs b/src/bindings_x86_64_pc_windows_msvc.rs similarity index 100% rename from src/bindings.rs rename to src/bindings_x86_64_pc_windows_msvc.rs diff --git a/src/bindings_x86_64_unknown_freebsd.rs b/src/bindings_x86_64_unknown_freebsd.rs new file mode 100644 index 0000000..356dc27 --- /dev/null +++ b/src/bindings_x86_64_unknown_freebsd.rs @@ -0,0 +1,699 @@ +/* automatically generated by rust-bindgen 0.69.4 */ + +#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] +#![allow(dead_code)] + +pub const CPUINFO_ARCH_X86_64: u32 = 1; +pub const CPUINFO_ARCH_X86: u32 = 0; +pub const CPUINFO_ARCH_ARM: u32 = 0; +pub const CPUINFO_ARCH_ARM64: u32 = 0; +pub const CPUINFO_ARCH_PPC64: u32 = 0; +pub const CPUINFO_ARCH_ASMJS: u32 = 0; +pub const CPUINFO_ARCH_WASM: u32 = 0; +pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; +pub const CPUINFO_ARCH_RISCV32: u32 = 0; +pub const CPUINFO_ARCH_RISCV64: u32 = 0; +pub const CPUINFO_CACHE_UNIFIED: u32 = 1; +pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; +pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; +pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; +pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; +pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; +pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; +pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; +pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; +pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; +pub type int_least64_t = i64; +pub type uint_least64_t = u64; +pub type int_fast64_t = i64; +pub type uint_fast64_t = u64; +pub type int_least32_t = i32; +pub type uint_least32_t = u32; +pub type int_fast32_t = i32; +pub type uint_fast32_t = u32; +pub type int_least16_t = i16; +pub type uint_least16_t = u16; +pub type int_fast16_t = i16; +pub type uint_fast16_t = u16; +pub type int_least8_t = i8; +pub type uint_least8_t = u8; +pub type int_fast8_t = i8; +pub type uint_fast8_t = u8; +pub type intmax_t = ::std::os::raw::c_long; +pub type uintmax_t = ::std::os::raw::c_ulong; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cache { + #[doc = " Cache size in bytes"] + pub size: u32, + #[doc = " Number of ways of associativity"] + pub associativity: u32, + #[doc = " Number of sets"] + pub sets: u32, + #[doc = " Number of partitions"] + pub partitions: u32, + #[doc = " Line size in bytes"] + pub line_size: u32, + #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] + pub flags: u32, + #[doc = " Index of the first logical processor that shares this cache"] + pub processor_start: u32, + #[doc = " Number of logical processors that share this cache"] + pub processor_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_trace_cache { + pub uops: u32, + pub associativity: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_tlb { + pub entries: u32, + pub associativity: u32, + pub pages: u64, +} +#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] +pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; +#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] +pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; +#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; +#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; +#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; +#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; +#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; +#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; +#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; +#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; +#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; +#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] +pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; +#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; +#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; +#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; +#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] +pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; +#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] +pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; +#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; +#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; +#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; +#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; +#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; +#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; +#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] +pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; +#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] +pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; +#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] +pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; +#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] +pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; +#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] +pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; +#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] +pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; +#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] +pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; +#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] +pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; +#[doc = " Vendor of processor core design"] +pub type cpuinfo_vendor = ::std::os::raw::c_uint; +#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] +pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; +#[doc = " Pentium and Pentium MMX microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; +#[doc = " Intel Quark microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; +#[doc = " Pentium Pro, Pentium II, and Pentium III."] +pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; +#[doc = " Pentium M."] +pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; +#[doc = " Intel Core microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; +#[doc = " Intel Core 2 microarchitecture on 65 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; +#[doc = " Intel Core 2 microarchitecture on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; +#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; +#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; +#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; +#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; +#[doc = " Intel Broadwell microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; +#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; +#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] +pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; +#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; +#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; +#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; +#[doc = " Pentium 4 with Prescott and later cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; +#[doc = " Intel Atom on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; +#[doc = " Intel Atom on 32 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; +#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; +#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; +#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; +#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; +#[doc = " Intel Knights Ferry HPC boards."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; +#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; +#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; +#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; +#[doc = " Intel Knights Mill Xeon Phi."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; +#[doc = " Intel/Marvell XScale series."] +pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; +#[doc = " AMD K5."] +pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; +#[doc = " AMD K6 and alike."] +pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; +#[doc = " AMD Athlon and Duron."] +pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; +#[doc = " AMD Athlon 64, Opteron 64."] +pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; +#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] +pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; +#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; +#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; +#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; +#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; +#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; +#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; +#[doc = " AMD Zen 3 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; +#[doc = " AMD Zen 4 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; +#[doc = " NSC Geode and AMD Geode GX and LX."] +pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; +#[doc = " AMD Bobcat mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; +#[doc = " AMD Jaguar mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; +#[doc = " AMD Puma mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; +#[doc = " ARM7 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; +#[doc = " ARM9 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; +#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; +#[doc = " ARM Cortex-A5."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; +#[doc = " ARM Cortex-A7."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; +#[doc = " ARM Cortex-A8."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; +#[doc = " ARM Cortex-A9."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; +#[doc = " ARM Cortex-A12."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; +#[doc = " ARM Cortex-A15."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; +#[doc = " ARM Cortex-A17."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; +#[doc = " ARM Cortex-A32."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; +#[doc = " ARM Cortex-A35."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; +#[doc = " ARM Cortex-A53."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; +#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; +#[doc = " ARM Cortex-A55."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; +#[doc = " ARM Cortex-A57."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; +#[doc = " ARM Cortex-A65."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; +#[doc = " ARM Cortex-A72."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; +#[doc = " ARM Cortex-A73."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; +#[doc = " ARM Cortex-A75."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; +#[doc = " ARM Cortex-A76."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; +#[doc = " ARM Cortex-A77."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; +#[doc = " ARM Cortex-A78."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; +#[doc = " ARM Neoverse N1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; +#[doc = " ARM Neoverse E1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; +#[doc = " ARM Neoverse V1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; +#[doc = " ARM Neoverse N2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; +#[doc = " ARM Neoverse V2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; +#[doc = " ARM Cortex-X1."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; +#[doc = " ARM Cortex-X2."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; +#[doc = " ARM Cortex-X3."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; +#[doc = " ARM Cortex-A510."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; +#[doc = " ARM Cortex-A710."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; +#[doc = " ARM Cortex-A715."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; +#[doc = " Qualcomm Scorpion."] +pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; +#[doc = " Qualcomm Krait."] +pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; +#[doc = " Qualcomm Kryo."] +pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; +#[doc = " Qualcomm Falkor."] +pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; +#[doc = " Qualcomm Saphira."] +pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; +#[doc = " Nvidia Denver."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; +#[doc = " Nvidia Denver 2."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; +#[doc = " Nvidia Carmel."] +pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; +#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; +#[doc = " Apple A6 and A6X processors."] +pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; +#[doc = " Apple A7 processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; +#[doc = " Apple A8 and A8X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; +#[doc = " Apple A9 and A9X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; +#[doc = " Apple A10 and A10X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; +#[doc = " Apple A11 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; +#[doc = " Apple A11 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; +#[doc = " Apple A12 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; +#[doc = " Apple A12 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; +#[doc = " Apple A13 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; +#[doc = " Apple A13 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; +#[doc = " Apple A14 / M1 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; +#[doc = " Apple A14 / M1 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; +#[doc = " Apple A15 / M2 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; +#[doc = " Apple A15 / M2 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; +#[doc = " Cavium ThunderX."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; +#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; +#[doc = " Marvell PJ4."] +pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; +#[doc = " Broadcom Brahma B15."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; +#[doc = " Broadcom Brahma B53."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; +#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] +pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; +#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] +pub type cpuinfo_uarch = ::std::os::raw::c_uint; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor { + #[doc = " SMT (hyperthread) ID within a core"] + pub smt_id: u32, + #[doc = " Core containing this logical processor"] + pub core: *const cpuinfo_core, + #[doc = " Cluster of cores containing this logical processor"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this logical processor"] + pub package: *const cpuinfo_package, + #[doc = " APIC ID (unique x86-specific ID of the logical processor)"] + pub apic_id: u32, + pub cache: cpuinfo_processor__bindgen_ty_1, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor__bindgen_ty_1 { + #[doc = " Level 1 instruction cache"] + pub l1i: *const cpuinfo_cache, + #[doc = " Level 1 data cache"] + pub l1d: *const cpuinfo_cache, + #[doc = " Level 2 unified or data cache"] + pub l2: *const cpuinfo_cache, + #[doc = " Level 3 unified or data cache"] + pub l3: *const cpuinfo_cache, + #[doc = " Level 4 unified or data cache"] + pub l4: *const cpuinfo_cache, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_core { + #[doc = " Index of the first logical processor on this core."] + pub processor_start: u32, + #[doc = " Number of logical processors on this core"] + pub processor_count: u32, + #[doc = " Core ID within a package"] + pub core_id: u32, + #[doc = " Cluster containing this core"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this core."] + pub package: *const cpuinfo_package, + #[doc = " Vendor of the CPU microarchitecture for this core"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture for this core"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of CPUID leaf 1 EAX register for this core"] + pub cpuid: u32, + #[doc = " Clock rate (non-Turbo) of the core, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cluster { + #[doc = " Index of the first logical processor in the cluster"] + pub processor_start: u32, + #[doc = " Number of logical processors in the cluster"] + pub processor_count: u32, + #[doc = " Index of the first core in the cluster"] + pub core_start: u32, + #[doc = " Number of cores on the cluster"] + pub core_count: u32, + #[doc = " Cluster ID within a package"] + pub cluster_id: u32, + #[doc = " Physical package containing the cluster"] + pub package: *const cpuinfo_package, + #[doc = " CPU microarchitecture vendor of the cores in the cluster"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture of the cores in the cluster"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of CPUID leaf 1 EAX register of the cores in the cluster"] + pub cpuid: u32, + #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_package { + #[doc = " SoC or processor chip model name"] + pub name: [::std::os::raw::c_char; 48usize], + #[doc = " Index of the first logical processor on this physical package"] + pub processor_start: u32, + #[doc = " Number of logical processors on this physical package"] + pub processor_count: u32, + #[doc = " Index of the first core on this physical package"] + pub core_start: u32, + #[doc = " Number of cores on this physical package"] + pub core_count: u32, + #[doc = " Index of the first cluster of cores on this physical package"] + pub cluster_start: u32, + #[doc = " Number of clusters of cores on this physical package"] + pub cluster_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_uarch_info { + #[doc = " Type of CPU microarchitecture"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture"] + pub cpuid: u32, + #[doc = " Number of logical processors with the microarchitecture"] + pub processor_count: u32, + #[doc = " Number of cores with the microarchitecture"] + pub core_count: u32, +} +extern "C" { + pub fn cpuinfo_initialize() -> bool; +} +extern "C" { + pub fn cpuinfo_deinitialize(); +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_x86_isa { + pub rdtscp: bool, + pub rdpid: bool, + pub sysenter: bool, + pub msr: bool, + pub clzero: bool, + pub clflush: bool, + pub clflushopt: bool, + pub mwait: bool, + pub mwaitx: bool, + pub fxsave: bool, + pub xsave: bool, + pub three_d_now: bool, + pub three_d_now_plus: bool, + pub prefetch: bool, + pub prefetchw: bool, + pub prefetchwt1: bool, + pub sse3: bool, + pub ssse3: bool, + pub sse4_1: bool, + pub sse4_2: bool, + pub sse4a: bool, + pub misaligned_sse: bool, + pub avx: bool, + pub avxvnni: bool, + pub fma3: bool, + pub fma4: bool, + pub xop: bool, + pub f16c: bool, + pub avx2: bool, + pub avx512f: bool, + pub avx512pf: bool, + pub avx512er: bool, + pub avx512cd: bool, + pub avx512dq: bool, + pub avx512bw: bool, + pub avx512vl: bool, + pub avx512ifma: bool, + pub avx512vbmi: bool, + pub avx512vbmi2: bool, + pub avx512bitalg: bool, + pub avx512vpopcntdq: bool, + pub avx512vnni: bool, + pub avx512bf16: bool, + pub avx512fp16: bool, + pub avx512vp2intersect: bool, + pub avx512_4vnniw: bool, + pub avx512_4fmaps: bool, + pub amx_bf16: bool, + pub amx_tile: bool, + pub amx_int8: bool, + pub amx_fp16: bool, + pub avx_vnni_int8: bool, + pub avx_vnni_int16: bool, + pub avx_ne_convert: bool, + pub hle: bool, + pub rtm: bool, + pub xtest: bool, + pub mpx: bool, + pub cmpxchg16b: bool, + pub clwb: bool, + pub movbe: bool, + pub lahf_sahf: bool, + pub fs_gs_base: bool, + pub lzcnt: bool, + pub popcnt: bool, + pub tbm: bool, + pub bmi: bool, + pub bmi2: bool, + pub adx: bool, + pub aes: bool, + pub vaes: bool, + pub pclmulqdq: bool, + pub vpclmulqdq: bool, + pub gfni: bool, + pub rdrand: bool, + pub rdseed: bool, + pub sha: bool, + pub rng: bool, + pub ace: bool, + pub ace2: bool, + pub phe: bool, + pub pmm: bool, + pub lwp: bool, +} +extern "C" { + pub static mut cpuinfo_isa: cpuinfo_x86_isa; +} +extern "C" { + pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_cores() -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_packages() -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processors_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_cores_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_clusters_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_packages_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_uarchs_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l2_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l3_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l4_caches_count() -> u32; +} +extern "C" { + #[doc = " Returns upper bound on cache size."] + pub fn cpuinfo_get_max_cache_size() -> u32; +} +extern "C" { + #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] + pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; +} +extern "C" { + #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] + pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index() -> u32; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; +} diff --git a/src/bindings_x86_64_unknown_linux_gnu.rs b/src/bindings_x86_64_unknown_linux_gnu.rs new file mode 100644 index 0000000..3160d12 --- /dev/null +++ b/src/bindings_x86_64_unknown_linux_gnu.rs @@ -0,0 +1,701 @@ +/* automatically generated by rust-bindgen 0.69.4 */ + +#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] +#![allow(dead_code)] + +pub const CPUINFO_ARCH_X86_64: u32 = 1; +pub const CPUINFO_ARCH_X86: u32 = 0; +pub const CPUINFO_ARCH_ARM: u32 = 0; +pub const CPUINFO_ARCH_ARM64: u32 = 0; +pub const CPUINFO_ARCH_PPC64: u32 = 0; +pub const CPUINFO_ARCH_ASMJS: u32 = 0; +pub const CPUINFO_ARCH_WASM: u32 = 0; +pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; +pub const CPUINFO_ARCH_RISCV32: u32 = 0; +pub const CPUINFO_ARCH_RISCV64: u32 = 0; +pub const CPUINFO_CACHE_UNIFIED: u32 = 1; +pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; +pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; +pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; +pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; +pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; +pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; +pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; +pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; +pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; +pub type int_least64_t = i64; +pub type uint_least64_t = u64; +pub type int_fast64_t = i64; +pub type uint_fast64_t = u64; +pub type int_least32_t = i32; +pub type uint_least32_t = u32; +pub type int_fast32_t = i32; +pub type uint_fast32_t = u32; +pub type int_least16_t = i16; +pub type uint_least16_t = u16; +pub type int_fast16_t = i16; +pub type uint_fast16_t = u16; +pub type int_least8_t = i8; +pub type uint_least8_t = u8; +pub type int_fast8_t = i8; +pub type uint_fast8_t = u8; +pub type intmax_t = ::std::os::raw::c_long; +pub type uintmax_t = ::std::os::raw::c_ulong; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cache { + #[doc = " Cache size in bytes"] + pub size: u32, + #[doc = " Number of ways of associativity"] + pub associativity: u32, + #[doc = " Number of sets"] + pub sets: u32, + #[doc = " Number of partitions"] + pub partitions: u32, + #[doc = " Line size in bytes"] + pub line_size: u32, + #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] + pub flags: u32, + #[doc = " Index of the first logical processor that shares this cache"] + pub processor_start: u32, + #[doc = " Number of logical processors that share this cache"] + pub processor_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_trace_cache { + pub uops: u32, + pub associativity: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_tlb { + pub entries: u32, + pub associativity: u32, + pub pages: u64, +} +#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] +pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; +#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] +pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; +#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; +#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; +#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; +#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; +#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; +#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; +#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; +#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; +#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; +#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] +pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; +#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; +#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; +#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; +#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] +pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; +#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] +pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; +#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; +#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; +#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; +#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; +#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; +#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] +pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; +#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] +pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; +#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] +pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; +#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] +pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; +#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] +pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; +#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] +pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; +#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] +pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; +#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] +pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; +#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] +pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; +#[doc = " Vendor of processor core design"] +pub type cpuinfo_vendor = ::std::os::raw::c_uint; +#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] +pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; +#[doc = " Pentium and Pentium MMX microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; +#[doc = " Intel Quark microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; +#[doc = " Pentium Pro, Pentium II, and Pentium III."] +pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; +#[doc = " Pentium M."] +pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; +#[doc = " Intel Core microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; +#[doc = " Intel Core 2 microarchitecture on 65 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; +#[doc = " Intel Core 2 microarchitecture on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; +#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; +#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; +#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; +#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] +pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; +#[doc = " Intel Broadwell microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; +#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; +#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] +pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; +#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; +#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; +#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; +#[doc = " Pentium 4 with Prescott and later cores."] +pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; +#[doc = " Intel Atom on 45 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; +#[doc = " Intel Atom on 32 nm process."] +pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; +#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; +#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] +pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; +#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; +#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] +pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; +#[doc = " Intel Knights Ferry HPC boards."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; +#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; +#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; +#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; +#[doc = " Intel Knights Mill Xeon Phi."] +pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; +#[doc = " Intel/Marvell XScale series."] +pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; +#[doc = " AMD K5."] +pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; +#[doc = " AMD K6 and alike."] +pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; +#[doc = " AMD Athlon and Duron."] +pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; +#[doc = " AMD Athlon 64, Opteron 64."] +pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; +#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] +pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; +#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; +#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] +pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; +#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; +#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; +#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; +#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; +#[doc = " AMD Zen 3 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; +#[doc = " AMD Zen 4 microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; +#[doc = " NSC Geode and AMD Geode GX and LX."] +pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; +#[doc = " AMD Bobcat mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; +#[doc = " AMD Jaguar mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; +#[doc = " AMD Puma mobile microarchitecture."] +pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; +#[doc = " ARM7 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; +#[doc = " ARM9 series."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; +#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] +pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; +#[doc = " ARM Cortex-A5."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; +#[doc = " ARM Cortex-A7."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; +#[doc = " ARM Cortex-A8."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; +#[doc = " ARM Cortex-A9."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; +#[doc = " ARM Cortex-A12."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; +#[doc = " ARM Cortex-A15."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; +#[doc = " ARM Cortex-A17."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; +#[doc = " ARM Cortex-A32."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; +#[doc = " ARM Cortex-A35."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; +#[doc = " ARM Cortex-A53."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; +#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; +#[doc = " ARM Cortex-A55."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; +#[doc = " ARM Cortex-A57."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; +#[doc = " ARM Cortex-A65."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; +#[doc = " ARM Cortex-A72."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; +#[doc = " ARM Cortex-A73."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; +#[doc = " ARM Cortex-A75."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; +#[doc = " ARM Cortex-A76."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; +#[doc = " ARM Cortex-A77."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; +#[doc = " ARM Cortex-A78."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; +#[doc = " ARM Neoverse N1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; +#[doc = " ARM Neoverse E1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; +#[doc = " ARM Neoverse V1."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; +#[doc = " ARM Neoverse N2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; +#[doc = " ARM Neoverse V2."] +pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; +#[doc = " ARM Cortex-X1."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; +#[doc = " ARM Cortex-X2."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; +#[doc = " ARM Cortex-X3."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; +#[doc = " ARM Cortex-A510."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; +#[doc = " ARM Cortex-A710."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; +#[doc = " ARM Cortex-A715."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; +#[doc = " Qualcomm Scorpion."] +pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; +#[doc = " Qualcomm Krait."] +pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; +#[doc = " Qualcomm Kryo."] +pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; +#[doc = " Qualcomm Falkor."] +pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; +#[doc = " Qualcomm Saphira."] +pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; +#[doc = " Nvidia Denver."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; +#[doc = " Nvidia Denver 2."] +pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; +#[doc = " Nvidia Carmel."] +pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; +#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; +#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; +#[doc = " Apple A6 and A6X processors."] +pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; +#[doc = " Apple A7 processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; +#[doc = " Apple A8 and A8X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; +#[doc = " Apple A9 and A9X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; +#[doc = " Apple A10 and A10X processor."] +pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; +#[doc = " Apple A11 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; +#[doc = " Apple A11 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; +#[doc = " Apple A12 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; +#[doc = " Apple A12 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; +#[doc = " Apple A13 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; +#[doc = " Apple A13 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; +#[doc = " Apple A14 / M1 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; +#[doc = " Apple A14 / M1 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; +#[doc = " Apple A15 / M2 processor (big cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; +#[doc = " Apple A15 / M2 processor (little cores)."] +pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; +#[doc = " Cavium ThunderX."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; +#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] +pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; +#[doc = " Marvell PJ4."] +pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; +#[doc = " Broadcom Brahma B15."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; +#[doc = " Broadcom Brahma B53."] +pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; +#[doc = " Applied Micro X-Gene."] +pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; +#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] +pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; +#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] +pub type cpuinfo_uarch = ::std::os::raw::c_uint; +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor { + #[doc = " SMT (hyperthread) ID within a core"] + pub smt_id: u32, + #[doc = " Core containing this logical processor"] + pub core: *const cpuinfo_core, + #[doc = " Cluster of cores containing this logical processor"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this logical processor"] + pub package: *const cpuinfo_package, + #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in\n /sys/devices/system/cpu/cpu/\n - Bit in the cpu_set_t identifies this logical processor"] + pub linux_id: ::std::os::raw::c_int, + #[doc = " APIC ID (unique x86-specific ID of the logical processor)"] + pub apic_id: u32, + pub cache: cpuinfo_processor__bindgen_ty_1, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_processor__bindgen_ty_1 { + #[doc = " Level 1 instruction cache"] + pub l1i: *const cpuinfo_cache, + #[doc = " Level 1 data cache"] + pub l1d: *const cpuinfo_cache, + #[doc = " Level 2 unified or data cache"] + pub l2: *const cpuinfo_cache, + #[doc = " Level 3 unified or data cache"] + pub l3: *const cpuinfo_cache, + #[doc = " Level 4 unified or data cache"] + pub l4: *const cpuinfo_cache, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_core { + #[doc = " Index of the first logical processor on this core."] + pub processor_start: u32, + #[doc = " Number of logical processors on this core"] + pub processor_count: u32, + #[doc = " Core ID within a package"] + pub core_id: u32, + #[doc = " Cluster containing this core"] + pub cluster: *const cpuinfo_cluster, + #[doc = " Physical package containing this core."] + pub package: *const cpuinfo_package, + #[doc = " Vendor of the CPU microarchitecture for this core"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture for this core"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of CPUID leaf 1 EAX register for this core"] + pub cpuid: u32, + #[doc = " Clock rate (non-Turbo) of the core, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_cluster { + #[doc = " Index of the first logical processor in the cluster"] + pub processor_start: u32, + #[doc = " Number of logical processors in the cluster"] + pub processor_count: u32, + #[doc = " Index of the first core in the cluster"] + pub core_start: u32, + #[doc = " Number of cores on the cluster"] + pub core_count: u32, + #[doc = " Cluster ID within a package"] + pub cluster_id: u32, + #[doc = " Physical package containing the cluster"] + pub package: *const cpuinfo_package, + #[doc = " CPU microarchitecture vendor of the cores in the cluster"] + pub vendor: cpuinfo_vendor, + #[doc = " CPU microarchitecture of the cores in the cluster"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of CPUID leaf 1 EAX register of the cores in the cluster"] + pub cpuid: u32, + #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] + pub frequency: u64, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_package { + #[doc = " SoC or processor chip model name"] + pub name: [::std::os::raw::c_char; 48usize], + #[doc = " Index of the first logical processor on this physical package"] + pub processor_start: u32, + #[doc = " Number of logical processors on this physical package"] + pub processor_count: u32, + #[doc = " Index of the first core on this physical package"] + pub core_start: u32, + #[doc = " Number of cores on this physical package"] + pub core_count: u32, + #[doc = " Index of the first cluster of cores on this physical package"] + pub cluster_start: u32, + #[doc = " Number of clusters of cores on this physical package"] + pub cluster_count: u32, +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_uarch_info { + #[doc = " Type of CPU microarchitecture"] + pub uarch: cpuinfo_uarch, + #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture"] + pub cpuid: u32, + #[doc = " Number of logical processors with the microarchitecture"] + pub processor_count: u32, + #[doc = " Number of cores with the microarchitecture"] + pub core_count: u32, +} +extern "C" { + pub fn cpuinfo_initialize() -> bool; +} +extern "C" { + pub fn cpuinfo_deinitialize(); +} +#[repr(C)] +#[derive(Debug, Copy, Clone)] +pub struct cpuinfo_x86_isa { + pub rdtscp: bool, + pub rdpid: bool, + pub sysenter: bool, + pub msr: bool, + pub clzero: bool, + pub clflush: bool, + pub clflushopt: bool, + pub mwait: bool, + pub mwaitx: bool, + pub fxsave: bool, + pub xsave: bool, + pub three_d_now: bool, + pub three_d_now_plus: bool, + pub prefetch: bool, + pub prefetchw: bool, + pub prefetchwt1: bool, + pub sse3: bool, + pub ssse3: bool, + pub sse4_1: bool, + pub sse4_2: bool, + pub sse4a: bool, + pub misaligned_sse: bool, + pub avx: bool, + pub avxvnni: bool, + pub fma3: bool, + pub fma4: bool, + pub xop: bool, + pub f16c: bool, + pub avx2: bool, + pub avx512f: bool, + pub avx512pf: bool, + pub avx512er: bool, + pub avx512cd: bool, + pub avx512dq: bool, + pub avx512bw: bool, + pub avx512vl: bool, + pub avx512ifma: bool, + pub avx512vbmi: bool, + pub avx512vbmi2: bool, + pub avx512bitalg: bool, + pub avx512vpopcntdq: bool, + pub avx512vnni: bool, + pub avx512bf16: bool, + pub avx512fp16: bool, + pub avx512vp2intersect: bool, + pub avx512_4vnniw: bool, + pub avx512_4fmaps: bool, + pub amx_bf16: bool, + pub amx_tile: bool, + pub amx_int8: bool, + pub amx_fp16: bool, + pub avx_vnni_int8: bool, + pub avx_vnni_int16: bool, + pub avx_ne_convert: bool, + pub hle: bool, + pub rtm: bool, + pub xtest: bool, + pub mpx: bool, + pub cmpxchg16b: bool, + pub clwb: bool, + pub movbe: bool, + pub lahf_sahf: bool, + pub fs_gs_base: bool, + pub lzcnt: bool, + pub popcnt: bool, + pub tbm: bool, + pub bmi: bool, + pub bmi2: bool, + pub adx: bool, + pub aes: bool, + pub vaes: bool, + pub pclmulqdq: bool, + pub vpclmulqdq: bool, + pub gfni: bool, + pub rdrand: bool, + pub rdseed: bool, + pub sha: bool, + pub rng: bool, + pub ace: bool, + pub ace2: bool, + pub phe: bool, + pub pmm: bool, + pub lwp: bool, +} +extern "C" { + pub static mut cpuinfo_isa: cpuinfo_x86_isa; +} +extern "C" { + pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_cores() -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_packages() -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; +} +extern "C" { + pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; +} +extern "C" { + pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; +} +extern "C" { + pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; +} +extern "C" { + pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; +} +extern "C" { + pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; +} +extern "C" { + pub fn cpuinfo_get_processors_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_cores_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_clusters_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_packages_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_uarchs_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1i_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l1d_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l2_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l3_caches_count() -> u32; +} +extern "C" { + pub fn cpuinfo_get_l4_caches_count() -> u32; +} +extern "C" { + #[doc = " Returns upper bound on cache size."] + pub fn cpuinfo_get_max_cache_size() -> u32; +} +extern "C" { + #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] + pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; +} +extern "C" { + #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] + pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index() -> u32; +} +extern "C" { + #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] + pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; +} diff --git a/src/lib.rs b/src/lib.rs index 02de504..2641362 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,7 +1,39 @@ #![doc = include_str!("../README.md")] -mod bindings; -use bindings::*; +#[cfg(all(target_arch = "aarch64", target_os = "android"))] +mod bindings_aarch64_linux_android; +#[cfg(all(target_arch = "aarch64", target_os = "android"))] +use bindings_aarch64_linux_android::*; + +#[cfg(all(target_arch = "aarch64", target_os = "windows", target_env = "msvc"))] +mod bindings_aarch64_pc_windows_msvc; +#[cfg(all(target_arch = "aarch64", target_os = "windows", target_env = "msvc"))] +use bindings_aarch64_pc_windows_msvc::*; + +#[cfg(all(target_arch = "aarch64", target_os = "linux", target_env = "gnu"))] +mod bindings_aarch64_unknown_linux_gnu; +#[cfg(all(target_arch = "aarch64", target_os = "linux", target_env = "gnu"))] +use bindings_aarch64_unknown_linux_gnu::*; + +#[cfg(all(target_arch = "arm", target_os = "linux", target_env = "gnu"))] +mod bindings_armv7_unknown_linux_gnueabihf; +#[cfg(all(target_arch = "arm", target_os = "linux", target_env = "gnu"))] +use bindings_armv7_unknown_linux_gnueabihf::*; + +#[cfg(all(target_arch = "x86_64", target_os = "windows", target_env = "msvc"))] +mod bindings_x86_64_pc_windows_msvc; +#[cfg(all(target_arch = "x86_64", target_os = "windows", target_env = "msvc"))] +use bindings_x86_64_pc_windows_msvc::*; + +#[cfg(all(target_arch = "x86_64", target_os = "freebsd"))] +mod bindings_x86_64_unknown_freebsd; +#[cfg(all(target_arch = "x86_64", target_os = "freebsd"))] +use bindings_x86_64_unknown_freebsd::*; + +#[cfg(all(target_arch = "x86_64", target_os = "linux", target_env = "gnu"))] +mod bindings_x86_64_unknown_linux_gnu; +#[cfg(all(target_arch = "x86_64", target_os = "linux", target_env = "gnu"))] +use bindings_x86_64_unknown_linux_gnu::*; use std::borrow::Cow; use std::sync::{Arc, Once}; @@ -73,6 +105,16 @@ impl CpuInfo { fn cluster(cluster: *const cpuinfo_cluster, package: Arc) -> Arc { Arc::new(unsafe { + #[cfg(target_arch = "x86_64")] + let cpuid = Some((*cluster).cpuid); + #[cfg(not(target_arch = "x86_64"))] + let cpuid = None; + + #[cfg(target_arch = "aarch64")] + let midr = Some((*cluster).midr); + #[cfg(not(target_arch = "aarch64"))] + let midr = None; + Cluster { processor_start: (*cluster).processor_start, processor_count: (*cluster).processor_count, @@ -82,7 +124,8 @@ impl CpuInfo { package: package.clone(), vendor: Self::vendor((*cluster).vendor), uarch: Self::uarch((*cluster).uarch), - cpuid: (*cluster).cpuid, + cpuid, + midr, frequency: (*cluster).frequency, } }) @@ -97,6 +140,16 @@ impl CpuInfo { fn core(core: *const cpuinfo_core, cluster: Arc, package: Arc) -> Arc { Arc::new(unsafe { + #[cfg(target_arch = "x86_64")] + let cpuid = (*cluster).cpuid; + #[cfg(not(target_arch = "x86_64"))] + let cpuid = None; + + #[cfg(target_arch = "aarch64")] + let midr = (*cluster).midr; + #[cfg(not(target_arch = "aarch64"))] + let midr = None; + Core { processor_start: (*core).processor_start, processor_count: (*core).processor_count, @@ -105,7 +158,8 @@ impl CpuInfo { package, vendor: Self::vendor((*core).vendor), uarch: Self::uarch((*core).uarch), - cpuid: (*core).cpuid, + cpuid, + midr, frequency: (*core).frequency, } }) @@ -170,14 +224,35 @@ impl CpuInfo { ); processors.push(unsafe { + #[cfg(target_os = "linux")] + let linux_id = Some((*processor).linux_id); + #[cfg(not(target_os = "linux"))] + let linux_id = None; + + #[cfg(target_os = "windows")] + let (windows_group_id, windows_processor_id) = { + ( + Some((*processor).windows_group_id), + Some((*processor).windows_processor_id), + ) + }; + #[cfg(not(target_os = "windows"))] + let (windows_group_id, windows_processor_id) = (None, None); + + #[cfg(target_arch = "x86_64")] + let apic_id = Some((*processor).apic_id); + #[cfg(not(target_arch = "x86_64"))] + let apic_id = None; + Processor { smt_id: (*processor).smt_id, core, cluster, package, - windows_group_id: (*processor).windows_group_id, - windows_processor_id: (*processor).windows_processor_id, - apic_id: (*processor).apic_id, + linux_id, + windows_group_id, + windows_processor_id, + apic_id, cache: Self::cache_info(&(*processor).cache), } }) @@ -218,12 +293,14 @@ pub struct Processor { pub cluster: Arc, #[doc = " Physical package containing this logical processor"] pub package: Arc, + #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in /sys/devices/system/cpu/cpu/ \n - Bit in the cpu_set_t identifies this logical processor"] + pub linux_id: Option, #[doc = " Windows-specific ID for the group containing the logical processor."] - pub windows_group_id: u16, + pub windows_group_id: Option, #[doc = " Windows-specific ID of the logical processor within its group:\n - Bit in the KAFFINITY mask identifies this\n logical processor within its group."] - pub windows_processor_id: u16, + pub windows_processor_id: Option, #[doc = " APIC ID (unique x86-specific ID of the logical processor)"] - pub apic_id: u32, + pub apic_id: Option, pub cache: CacheInfo, } @@ -264,8 +341,10 @@ pub struct Core { pub vendor: Vendor, #[doc = " CPU microarchitecture for this core"] pub uarch: Uarch, - #[doc = " Value of CPUID leaf 1 EAX register for this core"] - pub cpuid: u32, + #[doc = " Value of CPUID leaf 1 EAX register for this core (x86-specific ID)"] + pub cpuid: Option, + #[doc = " Value of Main ID Register (MIDR) for this core (arm-specific ID)"] + pub midr: Option, #[doc = " Clock rate (non-Turbo) of the core, in Hz"] pub frequency: u64, } @@ -288,8 +367,10 @@ pub struct Cluster { pub vendor: Vendor, #[doc = " CPU microarchitecture of the cores in the cluster"] pub uarch: Uarch, - #[doc = " Value of CPUID leaf 1 EAX register of the cores in the cluster"] - pub cpuid: u32, + #[doc = " Value of CPUID leaf 1 EAX register for this core (x86-specific ID)"] + pub cpuid: Option, + #[doc = " Value of Main ID Register (MIDR) for this core (arm-specific ID)"] + pub midr: Option, #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] pub frequency: u64, } From 6f93cdc0f9d10a4882c3bf84ea29d2ba32a932ce Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 13:36:40 +0200 Subject: [PATCH 02/30] fix --- src/lib.rs | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index 2641362..15a5c09 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -71,9 +71,20 @@ impl CpuInfo { for i in 0..count { let uarch_info = unsafe { cpuinfo_get_uarch(i) }; infos.push(unsafe { + #[cfg(target_arch = "x86_64")] + let cpuid = Some((*uarch_info).cpuid); + #[cfg(not(target_arch = "x86_64"))] + let cpuid = None; + + #[cfg(target_arch = "aarch64")] + let midr = Some((*uarch_info).midr); + #[cfg(not(target_arch = "aarch64"))] + let midr = None; + UarchInfo { uarch: Self::uarch((*uarch_info).uarch), - cpuid: (*uarch_info).cpuid, + cpuid, + midr, processor_count: (*uarch_info).processor_count, core_count: (*uarch_info).core_count, } @@ -140,17 +151,10 @@ impl CpuInfo { fn core(core: *const cpuinfo_core, cluster: Arc, package: Arc) -> Arc { Arc::new(unsafe { - #[cfg(target_arch = "x86_64")] - let cpuid = (*cluster).cpuid; - #[cfg(not(target_arch = "x86_64"))] - let cpuid = None; - - #[cfg(target_arch = "aarch64")] - let midr = (*cluster).midr; - #[cfg(not(target_arch = "aarch64"))] - let midr = None; - Core { + cpuid: cluster.cpuid, + midr: cluster.midr, + processor_start: (*core).processor_start, processor_count: (*core).processor_count, core_id: (*core).core_id, @@ -158,8 +162,6 @@ impl CpuInfo { package, vendor: Self::vendor((*core).vendor), uarch: Self::uarch((*core).uarch), - cpuid, - midr, frequency: (*core).frequency, } }) @@ -407,7 +409,9 @@ pub struct UarchInfo { #[doc = " Type of CPU microarchitecture"] pub uarch: Uarch, #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture"] - pub cpuid: u32, + pub cpuid: Option, + #[doc = " Value of Main ID Register (MIDR) for this core (arm-specific ID)"] + pub midr: Option, #[doc = " Number of logical processors with the microarchitecture"] pub processor_count: u32, #[doc = " Number of cores with the microarchitecture"] From b8a971f9b19d4466d394ee04c1c64883d9aa1a1d Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 13:47:35 +0200 Subject: [PATCH 03/30] move into single workflow --- .github/workflows/ci.yml | 96 ++++++++++++++++++++++++++++++- .github/workflows/cross.yaml | 106 ----------------------------------- 2 files changed, 94 insertions(+), 108 deletions(-) delete mode 100644 .github/workflows/cross.yaml diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index f7f0572..51d64bc 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,3 +1,5 @@ +name: CI + on: push: pull_request: @@ -14,8 +16,6 @@ jobs: run: cargo fmt --all -- --check - name: Cargo clippy run: cargo clippy --workspace --all-targets -- -D warnings - - name: Cargo test - run: cargo test --workspace rust-msrv: name: Build-test MSRV (1.74) with minimal crate dependencies @@ -33,3 +33,95 @@ jobs: - uses: dtolnay/rust-toolchain@1.74.0 - name: Cargo check run: cargo check --workspace --all-targets + + cross: + name: ${{ matrix.name }} (${{ matrix.target }}) + runs-on: ${{ matrix.os }} + env: + PROGRAM: ${{ matrix.cross && 'cross' || 'cargo' }} + strategy: + fail-fast: false + matrix: + target: + - x86_64-unknown-linux-gnu + # - x86_64-apple-darwin + - x86_64-pc-windows-msvc + - x86_64-unknown-freebsd + - aarch64-linux-android + - aarch64-unknown-linux-gnu + - aarch64-pc-windows-msvc + # - aarch64-apple-darwin + - armv7-unknown-linux-gnueabihf + + include: + - os: ubuntu-latest + name: Linux + target: x86_64-unknown-linux-gnu + cross: false + test: true + + - os: macos-latest + name: macOS + target: x86_64-apple-darwin + cross: false + test: true + + - os: windows-latest + name: Windows + target: x86_64-pc-windows-msvc + cross: false + test: true + + - os: ubuntu-latest + name: FreeBSD + target: x86_64-unknown-freebsd + cross: true + test: false + + - os: ubuntu-latest + name: Android + target: aarch64-linux-android + cross: true + test: true + + - os: ubuntu-latest + name: OpenWrt + target: aarch64-unknown-linux-gnu + cross: true + test: true + cargo_args: --features "openwrt" + + - os: ubuntu-latest + name: Linux ARMv7 + target: armv7-unknown-linux-gnueabihf + cross: true + test: true + + steps: + - name: Checkout + uses: actions/checkout@v4 + with: + submodules: 'true' + + - name: Bootstrap + uses: dtolnay/rust-toolchain@stable + with: + targets: ${{ matrix.target }} + + - name: Install cross + run: cargo install cross + if: ${{ matrix.cross }} + + - name: Build + run: ${{ env.PROGRAM }} build --target=${{ matrix.target }} ${{ matrix.cargo_args }} + + - name: Test + run: ${{ env.PROGRAM }} test --target=${{ matrix.target }} ${{ matrix.cargo_args }} + if: ${{ matrix.test }} + + - name: Run example + run: cargo run --example info + - uses: actions/upload-artifact@v4 + with: + name: info-${{ matrix.target }} + path: info.txt diff --git a/.github/workflows/cross.yaml b/.github/workflows/cross.yaml deleted file mode 100644 index 87bff05..0000000 --- a/.github/workflows/cross.yaml +++ /dev/null @@ -1,106 +0,0 @@ -on: [push, pull_request] - -name: CI - -jobs: - lint: - runs-on: ubuntu-latest - name: Lint - env: - RUSTFLAGS: "-Dwarnings" - steps: - - name: Checkout - uses: actions/checkout@v4 - with: - submodules: 'true' - checks: - name: ${{ matrix.name }} (${{ matrix.target }}) - runs-on: ${{ matrix.os }} - env: - PROGRAM: ${{ matrix.cross && 'cross' || 'cargo' }} - strategy: - fail-fast: false - matrix: - target: - - x86_64-unknown-linux-gnu - # - x86_64-apple-darwin - - x86_64-pc-windows-msvc - - x86_64-unknown-freebsd - - aarch64-linux-android - - aarch64-unknown-linux-gnu - - aarch64-pc-windows-msvc - # - aarch64-apple-darwin - - armv7-unknown-linux-gnueabihf - - include: - - os: ubuntu-latest - name: Linux - target: x86_64-unknown-linux-gnu - cross: false - test: true - - - os: macos-latest - name: macOS - target: x86_64-apple-darwin - cross: false - test: true - - - os: windows-latest - name: Windows - target: x86_64-pc-windows-msvc - cross: false - test: true - - - os: ubuntu-latest - name: FreeBSD - target: x86_64-unknown-freebsd - cross: true - test: false - - - os: ubuntu-latest - name: Android - target: aarch64-linux-android - cross: true - test: true - - - os: ubuntu-latest - name: OpenWrt - target: aarch64-unknown-linux-gnu - cross: true - test: true - cargo_args: --features "openwrt" - - - os: ubuntu-latest - name: Linux ARMv7 - target: armv7-unknown-linux-gnueabihf - cross: true - test: true - - steps: - - name: Checkout - uses: actions/checkout@v4 - with: - submodules: 'true' - - - name: Bootstrap - uses: dtolnay/rust-toolchain@stable - with: - targets: ${{ matrix.target }} - - - name: Install cross - run: cargo install cross - if: ${{ matrix.cross }} - - - name: Build - run: ${{ env.PROGRAM }} build --target=${{ matrix.target }} ${{ matrix.cargo_args }} - - - name: Test - run: ${{ env.PROGRAM }} test --target=${{ matrix.target }} ${{ matrix.cargo_args }} - if: ${{ matrix.test }} - - - name: Run example - run: cargo run --example info - - uses: actions/upload-artifact@v4 - with: - name: info-${{ matrix.target }} - path: info.txt \ No newline at end of file From 8478459a1b1ac1aa482bdca6a2995a0b5cd2285a Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 13:56:05 +0200 Subject: [PATCH 04/30] fix cross job --- .github/workflows/ci.yml | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 51d64bc..eefd2d1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -43,15 +43,15 @@ jobs: fail-fast: false matrix: target: - - x86_64-unknown-linux-gnu - # - x86_64-apple-darwin - - x86_64-pc-windows-msvc - - x86_64-unknown-freebsd - - aarch64-linux-android - - aarch64-unknown-linux-gnu - - aarch64-pc-windows-msvc - # - aarch64-apple-darwin - - armv7-unknown-linux-gnueabihf + # - x86_64-unknown-linux-gnu + # # - x86_64-apple-darwin + # - x86_64-pc-windows-msvc + # - x86_64-unknown-freebsd + # - aarch64-linux-android + # - aarch64-unknown-linux-gnu + # # - aarch64-pc-windows-msvc + # # - aarch64-apple-darwin + # - armv7-unknown-linux-gnueabihf include: - os: ubuntu-latest @@ -101,7 +101,7 @@ jobs: - name: Checkout uses: actions/checkout@v4 with: - submodules: 'true' + submodules: true - name: Bootstrap uses: dtolnay/rust-toolchain@stable @@ -124,4 +124,4 @@ jobs: - uses: actions/upload-artifact@v4 with: name: info-${{ matrix.target }} - path: info.txt + path: info.txt \ No newline at end of file From 974bfc9b52ed70aaee5b51955a91709ebbd0d6ba Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 13:56:51 +0200 Subject: [PATCH 05/30] fix.. --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index eefd2d1..623d6d1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -42,7 +42,7 @@ jobs: strategy: fail-fast: false matrix: - target: + # target: # - x86_64-unknown-linux-gnu # # - x86_64-apple-darwin # - x86_64-pc-windows-msvc From b3c8f82bfb90aedc00e35f8a7de55abdc9c53670 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:32:34 +0200 Subject: [PATCH 06/30] generate bindings ci --- .github/workflows/ci.yml | 22 ++--- .github/workflows/generate_bindings.yaml | 107 +++++++++++++++++++++++ build.rs | 5 +- 3 files changed, 120 insertions(+), 14 deletions(-) create mode 100644 .github/workflows/generate_bindings.yaml diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 623d6d1..38c3fff 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -72,11 +72,11 @@ jobs: cross: false test: true - - os: ubuntu-latest - name: FreeBSD - target: x86_64-unknown-freebsd - cross: true - test: false + # - os: ubuntu-latest + # name: FreeBSD + # target: x86_64-unknown-freebsd + # cross: true + # test: false - os: ubuntu-latest name: Android @@ -84,12 +84,12 @@ jobs: cross: true test: true - - os: ubuntu-latest - name: OpenWrt - target: aarch64-unknown-linux-gnu - cross: true - test: true - cargo_args: --features "openwrt" + # - os: ubuntu-latest + # name: OpenWrt + # target: aarch64-unknown-linux-gnu + # cross: true + # test: true + # cargo_args: --features "openwrt" - os: ubuntu-latest name: Linux ARMv7 diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml new file mode 100644 index 0000000..c319f97 --- /dev/null +++ b/.github/workflows/generate_bindings.yaml @@ -0,0 +1,107 @@ +name: Generate Bindings + +on: + workflow_dispatch: + +jobs: + generate: + name: Generate bindings + strategy: + include: + - target: x86_64-unknown-linux-gnu + path: x86_64_unknown_linux_gnu + os: ubuntu-latest + + - target: x86_64-apple-darwin + os: macos-latest + + - target: x86_64-pc-windows-msvc + os: ubuntu-latest + + - target: aarch64-linux-android + os: ubuntu-latest + + - target: aarch64-unknown-linux-gnu + os: ubuntu-latest + + - target: aarch64-pc-windows-msvc + os: ubuntu-latest + + - target: aarch64-apple-darwin + os: macos-latest + + - target: armv7-unknown-linux-gnueabihf + os: ubuntu-latest + + runs-on: ${{ matrix.os }} + steps: + - name: Checkout + uses: actions/checkout@v4 + with: + submodules: true + + - name: Build + run: cargo build --target ${{ matrix.target }} + + - name: Upload bindings + uses: actions/upload-artifact@v4 + with: + name: ${{ matrix.target }} + path: src/bindings_${ ${{ matrix.target }}//-/_}}.rs + + zip: + name: Zip bindings + needs: [generate] + runs_on: ubuntu-latest + + steps: + - name: Download x86_64-unknown-linux-gnu bindings + uses: actions/download-artifact@v4 + with: + name: x86_64-unknown-linux-gnu + + - name: Download x86_64-apple-darwin bindings + uses: actions/download-artifact@v4 + with: + name: x86_64-apple-darwin + + - name: Download x86_64-pc-windows-msvc bindings + uses: actions/download-artifact@v4 + with: + name: x86_64-pc-windows-msvc + + - name: Download aarch64-linux-android bindings + uses: actions/download-artifact@v4 + with: + name: aarch64-linux-android + + - name: Download aarch64-unknown-linux-gnu bindings + uses: actions/download-artifact@v4 + with: + name: aarch64-unknown-linux-gnu + + - name: Download aarch64-pc-windows-msvc bindings + uses: actions/download-artifact@v4 + with: + name: aarch64-pc-windows-msvc + + - name: Download aarch64-apple-darwin bindings + uses: actions/download-artifact@v4 + with: + name: aarch64-apple-darwin + + - name: Download armv7-unknown-linux-gnueabihf bindings + uses: actions/download-artifact@v4 + with: + name: armv7-unknown-linux-gnueabihf + + - name: Zip bindings + run: zip bindings.zip . + + - name: Upload zipped bindings + uses: actions/upload-artifact@v4 + with: + name: bindings + path: bindings.zip + + diff --git a/build.rs b/build.rs index 0dbfb5e..2b40898 100644 --- a/build.rs +++ b/build.rs @@ -80,13 +80,12 @@ const FREEBSD_X86_SRCS: &[&str] = &["src/x86/freebsd/init.c"]; /// Targets for which bindings will be generated. const BINDGEN_SUPPORTED_TARGETS: &[&str] = &[ "x86_64-unknown-linux-gnu", - // "x86_64-apple-darwin", + "x86_64-apple-darwin", "x86_64-pc-windows-msvc", - "x86_64-unknown-freebsd", "aarch64-linux-android", "aarch64-unknown-linux-gnu", "aarch64-pc-windows-msvc", - // "aarch64-apple-darwin", + "aarch64-apple-darwin", "armv7-unknown-linux-gnueabihf", ]; From 339228cb32621f43a875fbd27ee84992b990d3b4 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:33:26 +0200 Subject: [PATCH 07/30] on push --- .github/workflows/generate_bindings.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml index c319f97..cb6b84f 100644 --- a/.github/workflows/generate_bindings.yaml +++ b/.github/workflows/generate_bindings.yaml @@ -2,6 +2,7 @@ name: Generate Bindings on: workflow_dispatch: + push: jobs: generate: From e819cbef6e7271795eddfabd00992ca6fc069393 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:35:50 +0200 Subject: [PATCH 08/30] fix syntax --- .github/workflows/generate_bindings.yaml | 39 ++++++++++++------------ 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml index cb6b84f..afc1262 100644 --- a/.github/workflows/generate_bindings.yaml +++ b/.github/workflows/generate_bindings.yaml @@ -8,32 +8,33 @@ jobs: generate: name: Generate bindings strategy: - include: - - target: x86_64-unknown-linux-gnu - path: x86_64_unknown_linux_gnu - os: ubuntu-latest + matrix: + include: + - target: x86_64-unknown-linux-gnu + path: x86_64_unknown_linux_gnu + os: ubuntu-latest - - target: x86_64-apple-darwin - os: macos-latest + - target: x86_64-apple-darwin + os: macos-latest - - target: x86_64-pc-windows-msvc - os: ubuntu-latest + - target: x86_64-pc-windows-msvc + os: ubuntu-latest - - target: aarch64-linux-android - os: ubuntu-latest + - target: aarch64-linux-android + os: ubuntu-latest - - target: aarch64-unknown-linux-gnu - os: ubuntu-latest + - target: aarch64-unknown-linux-gnu + os: ubuntu-latest - - target: aarch64-pc-windows-msvc - os: ubuntu-latest + - target: aarch64-pc-windows-msvc + os: ubuntu-latest - - target: aarch64-apple-darwin - os: macos-latest - - - target: armv7-unknown-linux-gnueabihf - os: ubuntu-latest + - target: aarch64-apple-darwin + os: macos-latest + - target: armv7-unknown-linux-gnueabihf + os: ubuntu-latest + runs-on: ${{ matrix.os }} steps: - name: Checkout From 82cace9d939261453d98b73b46aae601de2b24ba Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:36:44 +0200 Subject: [PATCH 09/30] moar syntax --- .github/workflows/generate_bindings.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml index afc1262..3daf8a4 100644 --- a/.github/workflows/generate_bindings.yaml +++ b/.github/workflows/generate_bindings.yaml @@ -34,7 +34,7 @@ jobs: - target: armv7-unknown-linux-gnueabihf os: ubuntu-latest - + runs-on: ${{ matrix.os }} steps: - name: Checkout @@ -54,7 +54,7 @@ jobs: zip: name: Zip bindings needs: [generate] - runs_on: ubuntu-latest + runs-on: ubuntu-latest steps: - name: Download x86_64-unknown-linux-gnu bindings From 60afef8b924d3aa0474fb2cb89b460d6148cbeae Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:38:31 +0200 Subject: [PATCH 10/30] add target --- .github/workflows/generate_bindings.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml index 3daf8a4..c7d1688 100644 --- a/.github/workflows/generate_bindings.yaml +++ b/.github/workflows/generate_bindings.yaml @@ -42,6 +42,9 @@ jobs: with: submodules: true + - name: Setup + run: rustup target add ${{ matrix.target }} + - name: Build run: cargo build --target ${{ matrix.target }} From 64b5b718ac8c71b04a2ce23b22778e9cf2ff0556 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:41:37 +0200 Subject: [PATCH 11/30] cross compile --- .github/workflows/generate_bindings.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml index c7d1688..138d747 100644 --- a/.github/workflows/generate_bindings.yaml +++ b/.github/workflows/generate_bindings.yaml @@ -43,10 +43,15 @@ jobs: submodules: true - name: Setup - run: rustup target add ${{ matrix.target }} + uses: dtolnay/rust-toolchain@stable + with: + targets: ${{ matrix.target }} + + - name: Install cross + run: cargo install cross - name: Build - run: cargo build --target ${{ matrix.target }} + run: cross build --target ${{ matrix.target }} - name: Upload bindings uses: actions/upload-artifact@v4 From 440a22ee71528fe759b04554d54114b02b9b6803 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:44:05 +0200 Subject: [PATCH 12/30] fix build.rs --- build.rs | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/build.rs b/build.rs index 2b40898..5093fb3 100644 --- a/build.rs +++ b/build.rs @@ -146,30 +146,28 @@ fn main() { build.compile("cpuinfo"); - generate_bindings(); + generate_bindings(&target); } #[cfg(feature = "generate_bindings")] -fn generate_bindings() { - for target in BINDGEN_SUPPORTED_TARGETS { - let t = target.replace("-", "_"); - let output_file = format!("src/bindings_{t}.rs"); - - let bindings = bindgen::Builder::default() - .header("vendor/cpuinfo/include/cpuinfo.h") - .raw_line("#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)]") - .raw_line("#![allow(dead_code)]") - .clang_arg(format!("--target={target}")) - .clang_args(&["-xc++", "-std=c++11"]) - .layout_tests(false) - .generate() - .expect("Unable to generate bindings!"); - - bindings - .write_to_file(std::path::Path::new(&output_file)) - .expect("Unable to write bindings!"); - } +fn generate_bindings(target: &str) { + let t = target.replace("-", "_"); + let output_file = format!("src/bindings_{t}.rs"); + + let bindings = bindgen::Builder::default() + .header("vendor/cpuinfo/include/cpuinfo.h") + .raw_line("#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)]") + .raw_line("#![allow(dead_code)]") + .clang_arg(format!("--target={target}")) + .clang_args(&["-xc++", "-std=c++11"]) + .layout_tests(false) + .generate() + .expect("Unable to generate bindings!"); + + bindings + .write_to_file(std::path::Path::new(&output_file)) + .expect("Unable to write bindings!"); } #[cfg(not(feature = "generate_bindings"))] -fn generate_bindings() {} +fn generate_bindings(_: &str) {} From 5423a10663956ec3c3a4244c8aed33ff67bd4328 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:46:13 +0200 Subject: [PATCH 13/30] check --- .github/workflows/generate_bindings.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml index 138d747..e0cb002 100644 --- a/.github/workflows/generate_bindings.yaml +++ b/.github/workflows/generate_bindings.yaml @@ -8,10 +8,10 @@ jobs: generate: name: Generate bindings strategy: + fail-fast: false matrix: include: - target: x86_64-unknown-linux-gnu - path: x86_64_unknown_linux_gnu os: ubuntu-latest - target: x86_64-apple-darwin From 9b5adebd34f09306e37516d2ea3e9fd34bbeb605 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:50:17 +0200 Subject: [PATCH 14/30] Windows on windows --- .github/workflows/generate_bindings.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml index e0cb002..aed55e4 100644 --- a/.github/workflows/generate_bindings.yaml +++ b/.github/workflows/generate_bindings.yaml @@ -18,7 +18,7 @@ jobs: os: macos-latest - target: x86_64-pc-windows-msvc - os: ubuntu-latest + os: windows-latest - target: aarch64-linux-android os: ubuntu-latest @@ -27,7 +27,7 @@ jobs: os: ubuntu-latest - target: aarch64-pc-windows-msvc - os: ubuntu-latest + os: windows-latest - target: aarch64-apple-darwin os: macos-latest From 832a6decfb608081e29fda83d61d942f56ad35a2 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 14:55:30 +0200 Subject: [PATCH 15/30] add apple targets --- src/lib.rs | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index 15a5c09..50b8118 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -5,6 +5,11 @@ mod bindings_aarch64_linux_android; #[cfg(all(target_arch = "aarch64", target_os = "android"))] use bindings_aarch64_linux_android::*; +#[cfg(all(target_arch = "aarch64", target_os = "macos"))] +mod bindings_aarch64_apple_darwin; +#[cfg(all(target_arch = "aarch64", target_os = "macos"))] +use bindings_aarch64_apple_darwin::*; + #[cfg(all(target_arch = "aarch64", target_os = "windows", target_env = "msvc"))] mod bindings_aarch64_pc_windows_msvc; #[cfg(all(target_arch = "aarch64", target_os = "windows", target_env = "msvc"))] @@ -15,26 +20,26 @@ mod bindings_aarch64_unknown_linux_gnu; #[cfg(all(target_arch = "aarch64", target_os = "linux", target_env = "gnu"))] use bindings_aarch64_unknown_linux_gnu::*; -#[cfg(all(target_arch = "arm", target_os = "linux", target_env = "gnu"))] -mod bindings_armv7_unknown_linux_gnueabihf; -#[cfg(all(target_arch = "arm", target_os = "linux", target_env = "gnu"))] -use bindings_armv7_unknown_linux_gnueabihf::*; - #[cfg(all(target_arch = "x86_64", target_os = "windows", target_env = "msvc"))] mod bindings_x86_64_pc_windows_msvc; #[cfg(all(target_arch = "x86_64", target_os = "windows", target_env = "msvc"))] use bindings_x86_64_pc_windows_msvc::*; -#[cfg(all(target_arch = "x86_64", target_os = "freebsd"))] -mod bindings_x86_64_unknown_freebsd; -#[cfg(all(target_arch = "x86_64", target_os = "freebsd"))] -use bindings_x86_64_unknown_freebsd::*; - #[cfg(all(target_arch = "x86_64", target_os = "linux", target_env = "gnu"))] mod bindings_x86_64_unknown_linux_gnu; #[cfg(all(target_arch = "x86_64", target_os = "linux", target_env = "gnu"))] use bindings_x86_64_unknown_linux_gnu::*; +#[cfg(all(target_arch = "x86_64", target_os = "macos"))] +mod bindings_x86_64_apple_darwin; +#[cfg(all(target_arch = "x86_64", target_os = "macos"))] +use bindings_x86_64_apple_darwin::*; + +#[cfg(all(target_arch = "arm", target_os = "linux", target_env = "gnu"))] +mod bindings_armv7_unknown_linux_gnueabihf; +#[cfg(all(target_arch = "arm", target_os = "linux", target_env = "gnu"))] +use bindings_armv7_unknown_linux_gnueabihf::*; + use std::borrow::Cow; use std::sync::{Arc, Once}; From 5cb898d5bead3971e95cbf5fb994b34c1ea495b7 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 15:20:31 +0200 Subject: [PATCH 16/30] remove pregenerated bindings --- .github/workflows/ci.yml | 27 +- .github/workflows/generate_bindings.yaml | 117 --- .gitignore | 2 + Cargo.toml | 5 +- build.rs | 14 +- src/bindings_aarch64_linux_android.rs | 632 --------------- src/bindings_aarch64_pc_windows_msvc.rs | 681 ---------------- src/bindings_aarch64_unknown_linux_gnu.rs | 632 --------------- src/bindings_armv7_unknown_linux_gnueabihf.rs | 646 --------------- src/bindings_x86_64_pc_windows_msvc.rs | 749 ------------------ src/bindings_x86_64_unknown_freebsd.rs | 699 ---------------- src/bindings_x86_64_unknown_linux_gnu.rs | 701 ---------------- src/lib.rs | 41 +- 13 files changed, 16 insertions(+), 4930 deletions(-) delete mode 100644 .github/workflows/generate_bindings.yaml delete mode 100644 src/bindings_aarch64_linux_android.rs delete mode 100644 src/bindings_aarch64_pc_windows_msvc.rs delete mode 100644 src/bindings_aarch64_unknown_linux_gnu.rs delete mode 100644 src/bindings_armv7_unknown_linux_gnueabihf.rs delete mode 100644 src/bindings_x86_64_pc_windows_msvc.rs delete mode 100644 src/bindings_x86_64_unknown_freebsd.rs delete mode 100644 src/bindings_x86_64_unknown_linux_gnu.rs diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 38c3fff..248ce84 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -42,27 +42,16 @@ jobs: strategy: fail-fast: false matrix: - # target: - # - x86_64-unknown-linux-gnu - # # - x86_64-apple-darwin - # - x86_64-pc-windows-msvc - # - x86_64-unknown-freebsd - # - aarch64-linux-android - # - aarch64-unknown-linux-gnu - # # - aarch64-pc-windows-msvc - # # - aarch64-apple-darwin - # - armv7-unknown-linux-gnueabihf - include: - - os: ubuntu-latest + - target: x86_64-unknown-linux-gnu + os: ubuntu-latest name: Linux - target: x86_64-unknown-linux-gnu cross: false test: true - - os: macos-latest + - target: x86_64-apple-darwin + os: macos-latest name: macOS - target: x86_64-apple-darwin cross: false test: true @@ -78,9 +67,9 @@ jobs: # cross: true # test: false - - os: ubuntu-latest + - target: aarch64-linux-android + os: ubuntu-latest name: Android - target: aarch64-linux-android cross: true test: true @@ -91,9 +80,9 @@ jobs: # test: true # cargo_args: --features "openwrt" - - os: ubuntu-latest + - target: armv7-unknown-linux-gnueabihf + os: ubuntu-latest name: Linux ARMv7 - target: armv7-unknown-linux-gnueabihf cross: true test: true diff --git a/.github/workflows/generate_bindings.yaml b/.github/workflows/generate_bindings.yaml deleted file mode 100644 index aed55e4..0000000 --- a/.github/workflows/generate_bindings.yaml +++ /dev/null @@ -1,117 +0,0 @@ -name: Generate Bindings - -on: - workflow_dispatch: - push: - -jobs: - generate: - name: Generate bindings - strategy: - fail-fast: false - matrix: - include: - - target: x86_64-unknown-linux-gnu - os: ubuntu-latest - - - target: x86_64-apple-darwin - os: macos-latest - - - target: x86_64-pc-windows-msvc - os: windows-latest - - - target: aarch64-linux-android - os: ubuntu-latest - - - target: aarch64-unknown-linux-gnu - os: ubuntu-latest - - - target: aarch64-pc-windows-msvc - os: windows-latest - - - target: aarch64-apple-darwin - os: macos-latest - - - target: armv7-unknown-linux-gnueabihf - os: ubuntu-latest - - runs-on: ${{ matrix.os }} - steps: - - name: Checkout - uses: actions/checkout@v4 - with: - submodules: true - - - name: Setup - uses: dtolnay/rust-toolchain@stable - with: - targets: ${{ matrix.target }} - - - name: Install cross - run: cargo install cross - - - name: Build - run: cross build --target ${{ matrix.target }} - - - name: Upload bindings - uses: actions/upload-artifact@v4 - with: - name: ${{ matrix.target }} - path: src/bindings_${ ${{ matrix.target }}//-/_}}.rs - - zip: - name: Zip bindings - needs: [generate] - runs-on: ubuntu-latest - - steps: - - name: Download x86_64-unknown-linux-gnu bindings - uses: actions/download-artifact@v4 - with: - name: x86_64-unknown-linux-gnu - - - name: Download x86_64-apple-darwin bindings - uses: actions/download-artifact@v4 - with: - name: x86_64-apple-darwin - - - name: Download x86_64-pc-windows-msvc bindings - uses: actions/download-artifact@v4 - with: - name: x86_64-pc-windows-msvc - - - name: Download aarch64-linux-android bindings - uses: actions/download-artifact@v4 - with: - name: aarch64-linux-android - - - name: Download aarch64-unknown-linux-gnu bindings - uses: actions/download-artifact@v4 - with: - name: aarch64-unknown-linux-gnu - - - name: Download aarch64-pc-windows-msvc bindings - uses: actions/download-artifact@v4 - with: - name: aarch64-pc-windows-msvc - - - name: Download aarch64-apple-darwin bindings - uses: actions/download-artifact@v4 - with: - name: aarch64-apple-darwin - - - name: Download armv7-unknown-linux-gnueabihf bindings - uses: actions/download-artifact@v4 - with: - name: armv7-unknown-linux-gnueabihf - - - name: Zip bindings - run: zip bindings.zip . - - - name: Upload zipped bindings - uses: actions/upload-artifact@v4 - with: - name: bindings - path: bindings.zip - - diff --git a/.gitignore b/.gitignore index 250e9c4..9d543b7 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,5 @@ /target /Cargo.lock +/src/bindings.rs info.txt + diff --git a/Cargo.toml b/Cargo.toml index 4bc5cff..9b6e441 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -11,9 +11,6 @@ include = ["src", "vendor", "examples", "LICENSE", "build.rs"] categories = ["hardware-support"] # https://crates.io/category_slugs keywords = [] -[features] -generate_bindings = ["dep:bindgen"] - [dependencies] bytemuck = "1" serde = { version = "1", features = ["derive", "rc"] } @@ -22,5 +19,5 @@ serde = { version = "1", features = ["derive", "rc"] } serde_json = "1" [build-dependencies] -bindgen = { version = "0.69", optional = true } +bindgen = { version = "0.69" } cc = "1.1.0" diff --git a/build.rs b/build.rs index 5093fb3..a1fd88c 100644 --- a/build.rs +++ b/build.rs @@ -146,28 +146,20 @@ fn main() { build.compile("cpuinfo"); - generate_bindings(&target); + generate_bindings("src/bindings.rs"); } -#[cfg(feature = "generate_bindings")] -fn generate_bindings(target: &str) { - let t = target.replace("-", "_"); - let output_file = format!("src/bindings_{t}.rs"); - +fn generate_bindings(output_file: &str) { let bindings = bindgen::Builder::default() .header("vendor/cpuinfo/include/cpuinfo.h") .raw_line("#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)]") .raw_line("#![allow(dead_code)]") - .clang_arg(format!("--target={target}")) .clang_args(&["-xc++", "-std=c++11"]) .layout_tests(false) .generate() .expect("Unable to generate bindings!"); bindings - .write_to_file(std::path::Path::new(&output_file)) + .write_to_file(std::path::Path::new(output_file)) .expect("Unable to write bindings!"); } - -#[cfg(not(feature = "generate_bindings"))] -fn generate_bindings(_: &str) {} diff --git a/src/bindings_aarch64_linux_android.rs b/src/bindings_aarch64_linux_android.rs deleted file mode 100644 index f3e4247..0000000 --- a/src/bindings_aarch64_linux_android.rs +++ /dev/null @@ -1,632 +0,0 @@ -/* automatically generated by rust-bindgen 0.69.4 */ - -#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] -#![allow(dead_code)] - -pub const CPUINFO_ARCH_ARM64: u32 = 1; -pub const CPUINFO_ARCH_X86: u32 = 0; -pub const CPUINFO_ARCH_X86_64: u32 = 0; -pub const CPUINFO_ARCH_ARM: u32 = 0; -pub const CPUINFO_ARCH_PPC64: u32 = 0; -pub const CPUINFO_ARCH_ASMJS: u32 = 0; -pub const CPUINFO_ARCH_WASM: u32 = 0; -pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; -pub const CPUINFO_ARCH_RISCV32: u32 = 0; -pub const CPUINFO_ARCH_RISCV64: u32 = 0; -pub const CPUINFO_CACHE_UNIFIED: u32 = 1; -pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; -pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; -pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; -pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; -pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; -pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; -pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; -pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; -pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; -pub type int_least64_t = i64; -pub type uint_least64_t = u64; -pub type int_fast64_t = i64; -pub type uint_fast64_t = u64; -pub type int_least32_t = i32; -pub type uint_least32_t = u32; -pub type int_fast32_t = i32; -pub type uint_fast32_t = u32; -pub type int_least16_t = i16; -pub type uint_least16_t = u16; -pub type int_fast16_t = i16; -pub type uint_fast16_t = u16; -pub type int_least8_t = i8; -pub type uint_least8_t = u8; -pub type int_fast8_t = i8; -pub type uint_fast8_t = u8; -pub type intmax_t = ::std::os::raw::c_long; -pub type uintmax_t = ::std::os::raw::c_ulong; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cache { - #[doc = " Cache size in bytes"] - pub size: u32, - #[doc = " Number of ways of associativity"] - pub associativity: u32, - #[doc = " Number of sets"] - pub sets: u32, - #[doc = " Number of partitions"] - pub partitions: u32, - #[doc = " Line size in bytes"] - pub line_size: u32, - #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] - pub flags: u32, - #[doc = " Index of the first logical processor that shares this cache"] - pub processor_start: u32, - #[doc = " Number of logical processors that share this cache"] - pub processor_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_trace_cache { - pub uops: u32, - pub associativity: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_tlb { - pub entries: u32, - pub associativity: u32, - pub pages: u64, -} -#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] -pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; -#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] -pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; -#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; -#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; -#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; -#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; -#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; -#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; -#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; -#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; -#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; -#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] -pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; -#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; -#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; -#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; -#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] -pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; -#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] -pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; -#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; -#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; -#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; -#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; -#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; -#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; -#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] -pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; -#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] -pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; -#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] -pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; -#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] -pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; -#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] -pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; -#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] -pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; -#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] -pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; -#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] -pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; -#[doc = " Vendor of processor core design"] -pub type cpuinfo_vendor = ::std::os::raw::c_uint; -#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] -pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; -#[doc = " Pentium and Pentium MMX microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; -#[doc = " Intel Quark microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; -#[doc = " Pentium Pro, Pentium II, and Pentium III."] -pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; -#[doc = " Pentium M."] -pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; -#[doc = " Intel Core microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; -#[doc = " Intel Core 2 microarchitecture on 65 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; -#[doc = " Intel Core 2 microarchitecture on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; -#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; -#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; -#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; -#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; -#[doc = " Intel Broadwell microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; -#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; -#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] -pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; -#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; -#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; -#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; -#[doc = " Pentium 4 with Prescott and later cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; -#[doc = " Intel Atom on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; -#[doc = " Intel Atom on 32 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; -#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; -#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; -#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; -#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; -#[doc = " Intel Knights Ferry HPC boards."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; -#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; -#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; -#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; -#[doc = " Intel Knights Mill Xeon Phi."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; -#[doc = " Intel/Marvell XScale series."] -pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; -#[doc = " AMD K5."] -pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; -#[doc = " AMD K6 and alike."] -pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; -#[doc = " AMD Athlon and Duron."] -pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; -#[doc = " AMD Athlon 64, Opteron 64."] -pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; -#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] -pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; -#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; -#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; -#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; -#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; -#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; -#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; -#[doc = " AMD Zen 3 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; -#[doc = " AMD Zen 4 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; -#[doc = " NSC Geode and AMD Geode GX and LX."] -pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; -#[doc = " AMD Bobcat mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; -#[doc = " AMD Jaguar mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; -#[doc = " AMD Puma mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; -#[doc = " ARM7 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; -#[doc = " ARM9 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; -#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; -#[doc = " ARM Cortex-A5."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; -#[doc = " ARM Cortex-A7."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; -#[doc = " ARM Cortex-A8."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; -#[doc = " ARM Cortex-A9."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; -#[doc = " ARM Cortex-A12."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; -#[doc = " ARM Cortex-A15."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; -#[doc = " ARM Cortex-A17."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; -#[doc = " ARM Cortex-A32."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; -#[doc = " ARM Cortex-A35."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; -#[doc = " ARM Cortex-A53."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; -#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; -#[doc = " ARM Cortex-A55."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; -#[doc = " ARM Cortex-A57."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; -#[doc = " ARM Cortex-A65."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; -#[doc = " ARM Cortex-A72."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; -#[doc = " ARM Cortex-A73."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; -#[doc = " ARM Cortex-A75."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; -#[doc = " ARM Cortex-A76."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; -#[doc = " ARM Cortex-A77."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; -#[doc = " ARM Cortex-A78."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; -#[doc = " ARM Neoverse N1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; -#[doc = " ARM Neoverse E1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; -#[doc = " ARM Neoverse V1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; -#[doc = " ARM Neoverse N2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; -#[doc = " ARM Neoverse V2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; -#[doc = " ARM Cortex-X1."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; -#[doc = " ARM Cortex-X2."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; -#[doc = " ARM Cortex-X3."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; -#[doc = " ARM Cortex-A510."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; -#[doc = " ARM Cortex-A710."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; -#[doc = " ARM Cortex-A715."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; -#[doc = " Qualcomm Scorpion."] -pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; -#[doc = " Qualcomm Krait."] -pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; -#[doc = " Qualcomm Kryo."] -pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; -#[doc = " Qualcomm Falkor."] -pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; -#[doc = " Qualcomm Saphira."] -pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; -#[doc = " Nvidia Denver."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; -#[doc = " Nvidia Denver 2."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; -#[doc = " Nvidia Carmel."] -pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; -#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; -#[doc = " Apple A6 and A6X processors."] -pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; -#[doc = " Apple A7 processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; -#[doc = " Apple A8 and A8X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; -#[doc = " Apple A9 and A9X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; -#[doc = " Apple A10 and A10X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; -#[doc = " Apple A11 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; -#[doc = " Apple A11 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; -#[doc = " Apple A12 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; -#[doc = " Apple A12 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; -#[doc = " Apple A13 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; -#[doc = " Apple A13 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; -#[doc = " Apple A14 / M1 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; -#[doc = " Apple A14 / M1 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; -#[doc = " Apple A15 / M2 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; -#[doc = " Apple A15 / M2 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; -#[doc = " Cavium ThunderX."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; -#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; -#[doc = " Marvell PJ4."] -pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; -#[doc = " Broadcom Brahma B15."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; -#[doc = " Broadcom Brahma B53."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; -#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] -pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; -#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] -pub type cpuinfo_uarch = ::std::os::raw::c_uint; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor { - #[doc = " SMT (hyperthread) ID within a core"] - pub smt_id: u32, - #[doc = " Core containing this logical processor"] - pub core: *const cpuinfo_core, - #[doc = " Cluster of cores containing this logical processor"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this logical processor"] - pub package: *const cpuinfo_package, - #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in\n /sys/devices/system/cpu/cpu/\n - Bit in the cpu_set_t identifies this logical processor"] - pub linux_id: ::std::os::raw::c_int, - pub cache: cpuinfo_processor__bindgen_ty_1, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor__bindgen_ty_1 { - #[doc = " Level 1 instruction cache"] - pub l1i: *const cpuinfo_cache, - #[doc = " Level 1 data cache"] - pub l1d: *const cpuinfo_cache, - #[doc = " Level 2 unified or data cache"] - pub l2: *const cpuinfo_cache, - #[doc = " Level 3 unified or data cache"] - pub l3: *const cpuinfo_cache, - #[doc = " Level 4 unified or data cache"] - pub l4: *const cpuinfo_cache, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_core { - #[doc = " Index of the first logical processor on this core."] - pub processor_start: u32, - #[doc = " Number of logical processors on this core"] - pub processor_count: u32, - #[doc = " Core ID within a package"] - pub core_id: u32, - #[doc = " Cluster containing this core"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this core."] - pub package: *const cpuinfo_package, - #[doc = " Vendor of the CPU microarchitecture for this core"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture for this core"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) for this core"] - pub midr: u32, - #[doc = " Clock rate (non-Turbo) of the core, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cluster { - #[doc = " Index of the first logical processor in the cluster"] - pub processor_start: u32, - #[doc = " Number of logical processors in the cluster"] - pub processor_count: u32, - #[doc = " Index of the first core in the cluster"] - pub core_start: u32, - #[doc = " Number of cores on the cluster"] - pub core_count: u32, - #[doc = " Cluster ID within a package"] - pub cluster_id: u32, - #[doc = " Physical package containing the cluster"] - pub package: *const cpuinfo_package, - #[doc = " CPU microarchitecture vendor of the cores in the cluster"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture of the cores in the cluster"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) of the cores in the cluster"] - pub midr: u32, - #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_package { - #[doc = " SoC or processor chip model name"] - pub name: [::std::os::raw::c_char; 48usize], - #[doc = " Index of the first logical processor on this physical package"] - pub processor_start: u32, - #[doc = " Number of logical processors on this physical package"] - pub processor_count: u32, - #[doc = " Index of the first core on this physical package"] - pub core_start: u32, - #[doc = " Number of cores on this physical package"] - pub core_count: u32, - #[doc = " Index of the first cluster of cores on this physical package"] - pub cluster_start: u32, - #[doc = " Number of clusters of cores on this physical package"] - pub cluster_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_uarch_info { - #[doc = " Type of CPU microarchitecture"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) for the microarchitecture"] - pub midr: u32, - #[doc = " Number of logical processors with the microarchitecture"] - pub processor_count: u32, - #[doc = " Number of cores with the microarchitecture"] - pub core_count: u32, -} -extern "C" { - pub fn cpuinfo_initialize() -> bool; -} -extern "C" { - pub fn cpuinfo_deinitialize(); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_arm_isa { - pub atomics: bool, - pub bf16: bool, - pub sve: bool, - pub sve2: bool, - pub i8mm: bool, - pub rdm: bool, - pub fp16arith: bool, - pub dot: bool, - pub jscvt: bool, - pub fcma: bool, - pub fhm: bool, - pub aes: bool, - pub sha1: bool, - pub sha2: bool, - pub pmull: bool, - pub crc32: bool, -} -extern "C" { - pub static mut cpuinfo_isa: cpuinfo_arm_isa; -} -extern "C" { - pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_cores() -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_packages() -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processors_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_cores_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_clusters_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_packages_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_uarchs_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l2_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l3_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l4_caches_count() -> u32; -} -extern "C" { - #[doc = " Returns upper bound on cache size."] - pub fn cpuinfo_get_max_cache_size() -> u32; -} -extern "C" { - #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] - pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; -} -extern "C" { - #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] - pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index() -> u32; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; -} diff --git a/src/bindings_aarch64_pc_windows_msvc.rs b/src/bindings_aarch64_pc_windows_msvc.rs deleted file mode 100644 index 5c568f2..0000000 --- a/src/bindings_aarch64_pc_windows_msvc.rs +++ /dev/null @@ -1,681 +0,0 @@ -/* automatically generated by rust-bindgen 0.69.4 */ - -#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] -#![allow(dead_code)] - -pub const _VCRT_COMPILER_PREPROCESSOR: u32 = 1; -pub const _SAL_VERSION: u32 = 20; -pub const __SAL_H_VERSION: u32 = 180000000; -pub const _USE_DECLSPECS_FOR_SAL: u32 = 0; -pub const _USE_ATTRIBUTES_FOR_SAL: u32 = 0; -pub const _CRT_PACKING: u32 = 8; -pub const _VA_ALIGN: u32 = 8; -pub const _HAS_EXCEPTIONS: u32 = 1; -pub const NULL: u32 = 0; -pub const _HAS_CXX17: u32 = 0; -pub const _HAS_CXX20: u32 = 0; -pub const _HAS_CXX23: u32 = 0; -pub const _HAS_NODISCARD: u32 = 1; -pub const WCHAR_MIN: u32 = 0; -pub const WCHAR_MAX: u32 = 65535; -pub const WINT_MIN: u32 = 0; -pub const WINT_MAX: u32 = 65535; -pub const CPUINFO_ARCH_ARM64: u32 = 1; -pub const CPUINFO_ARCH_X86: u32 = 0; -pub const CPUINFO_ARCH_X86_64: u32 = 0; -pub const CPUINFO_ARCH_ARM: u32 = 0; -pub const CPUINFO_ARCH_PPC64: u32 = 0; -pub const CPUINFO_ARCH_ASMJS: u32 = 0; -pub const CPUINFO_ARCH_WASM: u32 = 0; -pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; -pub const CPUINFO_ARCH_RISCV32: u32 = 0; -pub const CPUINFO_ARCH_RISCV64: u32 = 0; -pub const CPUINFO_CACHE_UNIFIED: u32 = 1; -pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; -pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; -pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; -pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; -pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; -pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; -pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; -pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; -pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; -pub type va_list = *mut ::std::os::raw::c_char; -extern "C" { - pub fn __va_start(arg1: *mut va_list, ...); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct __vcrt_va_list_is_reference { - pub _address: u8, -} -pub const __vcrt_va_list_is_reference___the_value: __vcrt_va_list_is_reference__bindgen_ty_1 = - false; -pub type __vcrt_va_list_is_reference__bindgen_ty_1 = bool; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct __vcrt_assert_va_start_is_not_reference { - pub _address: u8, -} -pub type __vcrt_bool = bool; -extern "C" { - pub fn __security_init_cookie(); -} -extern "C" { - pub fn __security_check_cookie(_StackCookie: usize); -} -extern "C" { - pub fn __report_gsfailure(_StackCookie: usize) -> !; -} -extern "C" { - pub static mut __security_cookie: usize; -} -pub type int_least8_t = ::std::os::raw::c_schar; -pub type int_least16_t = ::std::os::raw::c_short; -pub type int_least32_t = ::std::os::raw::c_int; -pub type int_least64_t = ::std::os::raw::c_longlong; -pub type uint_least8_t = ::std::os::raw::c_uchar; -pub type uint_least16_t = ::std::os::raw::c_ushort; -pub type uint_least32_t = ::std::os::raw::c_uint; -pub type uint_least64_t = ::std::os::raw::c_ulonglong; -pub type int_fast8_t = ::std::os::raw::c_schar; -pub type int_fast16_t = ::std::os::raw::c_int; -pub type int_fast32_t = ::std::os::raw::c_int; -pub type int_fast64_t = ::std::os::raw::c_longlong; -pub type uint_fast8_t = ::std::os::raw::c_uchar; -pub type uint_fast16_t = ::std::os::raw::c_uint; -pub type uint_fast32_t = ::std::os::raw::c_uint; -pub type uint_fast64_t = ::std::os::raw::c_ulonglong; -pub type intmax_t = ::std::os::raw::c_longlong; -pub type uintmax_t = ::std::os::raw::c_ulonglong; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cache { - #[doc = " Cache size in bytes"] - pub size: u32, - #[doc = " Number of ways of associativity"] - pub associativity: u32, - #[doc = " Number of sets"] - pub sets: u32, - #[doc = " Number of partitions"] - pub partitions: u32, - #[doc = " Line size in bytes"] - pub line_size: u32, - #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] - pub flags: u32, - #[doc = " Index of the first logical processor that shares this cache"] - pub processor_start: u32, - #[doc = " Number of logical processors that share this cache"] - pub processor_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_trace_cache { - pub uops: u32, - pub associativity: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_tlb { - pub entries: u32, - pub associativity: u32, - pub pages: u64, -} -#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] -pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; -#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] -pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; -#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; -#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; -#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; -#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; -#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; -#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; -#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; -#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; -#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; -#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] -pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; -#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; -#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; -#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; -#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] -pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; -#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] -pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; -#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; -#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; -#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; -#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; -#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; -#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; -#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] -pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; -#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] -pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; -#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] -pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; -#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] -pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; -#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] -pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; -#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] -pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; -#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] -pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; -#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] -pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; -#[doc = " Vendor of processor core design"] -pub type cpuinfo_vendor = ::std::os::raw::c_int; -#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] -pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; -#[doc = " Pentium and Pentium MMX microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; -#[doc = " Intel Quark microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; -#[doc = " Pentium Pro, Pentium II, and Pentium III."] -pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; -#[doc = " Pentium M."] -pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; -#[doc = " Intel Core microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; -#[doc = " Intel Core 2 microarchitecture on 65 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; -#[doc = " Intel Core 2 microarchitecture on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; -#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; -#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; -#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; -#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; -#[doc = " Intel Broadwell microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; -#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; -#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] -pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; -#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; -#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; -#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; -#[doc = " Pentium 4 with Prescott and later cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; -#[doc = " Intel Atom on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; -#[doc = " Intel Atom on 32 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; -#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; -#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; -#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; -#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; -#[doc = " Intel Knights Ferry HPC boards."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; -#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; -#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; -#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; -#[doc = " Intel Knights Mill Xeon Phi."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; -#[doc = " Intel/Marvell XScale series."] -pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; -#[doc = " AMD K5."] -pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; -#[doc = " AMD K6 and alike."] -pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; -#[doc = " AMD Athlon and Duron."] -pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; -#[doc = " AMD Athlon 64, Opteron 64."] -pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; -#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] -pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; -#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; -#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; -#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; -#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; -#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; -#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; -#[doc = " AMD Zen 3 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; -#[doc = " AMD Zen 4 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; -#[doc = " NSC Geode and AMD Geode GX and LX."] -pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; -#[doc = " AMD Bobcat mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; -#[doc = " AMD Jaguar mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; -#[doc = " AMD Puma mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; -#[doc = " ARM7 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; -#[doc = " ARM9 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; -#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; -#[doc = " ARM Cortex-A5."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; -#[doc = " ARM Cortex-A7."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; -#[doc = " ARM Cortex-A8."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; -#[doc = " ARM Cortex-A9."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; -#[doc = " ARM Cortex-A12."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; -#[doc = " ARM Cortex-A15."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; -#[doc = " ARM Cortex-A17."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; -#[doc = " ARM Cortex-A32."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; -#[doc = " ARM Cortex-A35."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; -#[doc = " ARM Cortex-A53."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; -#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; -#[doc = " ARM Cortex-A55."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; -#[doc = " ARM Cortex-A57."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; -#[doc = " ARM Cortex-A65."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; -#[doc = " ARM Cortex-A72."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; -#[doc = " ARM Cortex-A73."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; -#[doc = " ARM Cortex-A75."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; -#[doc = " ARM Cortex-A76."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; -#[doc = " ARM Cortex-A77."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; -#[doc = " ARM Cortex-A78."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; -#[doc = " ARM Neoverse N1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; -#[doc = " ARM Neoverse E1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; -#[doc = " ARM Neoverse V1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; -#[doc = " ARM Neoverse N2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; -#[doc = " ARM Neoverse V2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; -#[doc = " ARM Cortex-X1."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; -#[doc = " ARM Cortex-X2."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; -#[doc = " ARM Cortex-X3."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; -#[doc = " ARM Cortex-A510."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; -#[doc = " ARM Cortex-A710."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; -#[doc = " ARM Cortex-A715."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; -#[doc = " Qualcomm Scorpion."] -pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; -#[doc = " Qualcomm Krait."] -pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; -#[doc = " Qualcomm Kryo."] -pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; -#[doc = " Qualcomm Falkor."] -pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; -#[doc = " Qualcomm Saphira."] -pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; -#[doc = " Nvidia Denver."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; -#[doc = " Nvidia Denver 2."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; -#[doc = " Nvidia Carmel."] -pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; -#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; -#[doc = " Apple A6 and A6X processors."] -pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; -#[doc = " Apple A7 processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; -#[doc = " Apple A8 and A8X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; -#[doc = " Apple A9 and A9X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; -#[doc = " Apple A10 and A10X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; -#[doc = " Apple A11 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; -#[doc = " Apple A11 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; -#[doc = " Apple A12 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; -#[doc = " Apple A12 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; -#[doc = " Apple A13 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; -#[doc = " Apple A13 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; -#[doc = " Apple A14 / M1 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; -#[doc = " Apple A14 / M1 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; -#[doc = " Apple A15 / M2 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; -#[doc = " Apple A15 / M2 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; -#[doc = " Cavium ThunderX."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; -#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; -#[doc = " Marvell PJ4."] -pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; -#[doc = " Broadcom Brahma B15."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; -#[doc = " Broadcom Brahma B53."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; -#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] -pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; -#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] -pub type cpuinfo_uarch = ::std::os::raw::c_int; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor { - #[doc = " SMT (hyperthread) ID within a core"] - pub smt_id: u32, - #[doc = " Core containing this logical processor"] - pub core: *const cpuinfo_core, - #[doc = " Cluster of cores containing this logical processor"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this logical processor"] - pub package: *const cpuinfo_package, - #[doc = " Windows-specific ID for the group containing the logical processor."] - pub windows_group_id: u16, - #[doc = " Windows-specific ID of the logical processor within its group:\n - Bit in the KAFFINITY mask identifies this\n logical processor within its group."] - pub windows_processor_id: u16, - pub cache: cpuinfo_processor__bindgen_ty_1, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor__bindgen_ty_1 { - #[doc = " Level 1 instruction cache"] - pub l1i: *const cpuinfo_cache, - #[doc = " Level 1 data cache"] - pub l1d: *const cpuinfo_cache, - #[doc = " Level 2 unified or data cache"] - pub l2: *const cpuinfo_cache, - #[doc = " Level 3 unified or data cache"] - pub l3: *const cpuinfo_cache, - #[doc = " Level 4 unified or data cache"] - pub l4: *const cpuinfo_cache, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_core { - #[doc = " Index of the first logical processor on this core."] - pub processor_start: u32, - #[doc = " Number of logical processors on this core"] - pub processor_count: u32, - #[doc = " Core ID within a package"] - pub core_id: u32, - #[doc = " Cluster containing this core"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this core."] - pub package: *const cpuinfo_package, - #[doc = " Vendor of the CPU microarchitecture for this core"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture for this core"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) for this core"] - pub midr: u32, - #[doc = " Clock rate (non-Turbo) of the core, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cluster { - #[doc = " Index of the first logical processor in the cluster"] - pub processor_start: u32, - #[doc = " Number of logical processors in the cluster"] - pub processor_count: u32, - #[doc = " Index of the first core in the cluster"] - pub core_start: u32, - #[doc = " Number of cores on the cluster"] - pub core_count: u32, - #[doc = " Cluster ID within a package"] - pub cluster_id: u32, - #[doc = " Physical package containing the cluster"] - pub package: *const cpuinfo_package, - #[doc = " CPU microarchitecture vendor of the cores in the cluster"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture of the cores in the cluster"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) of the cores in the cluster"] - pub midr: u32, - #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_package { - #[doc = " SoC or processor chip model name"] - pub name: [::std::os::raw::c_char; 48usize], - #[doc = " Index of the first logical processor on this physical package"] - pub processor_start: u32, - #[doc = " Number of logical processors on this physical package"] - pub processor_count: u32, - #[doc = " Index of the first core on this physical package"] - pub core_start: u32, - #[doc = " Number of cores on this physical package"] - pub core_count: u32, - #[doc = " Index of the first cluster of cores on this physical package"] - pub cluster_start: u32, - #[doc = " Number of clusters of cores on this physical package"] - pub cluster_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_uarch_info { - #[doc = " Type of CPU microarchitecture"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) for the microarchitecture"] - pub midr: u32, - #[doc = " Number of logical processors with the microarchitecture"] - pub processor_count: u32, - #[doc = " Number of cores with the microarchitecture"] - pub core_count: u32, -} -extern "C" { - pub fn cpuinfo_initialize() -> bool; -} -extern "C" { - pub fn cpuinfo_deinitialize(); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_arm_isa { - pub atomics: bool, - pub bf16: bool, - pub sve: bool, - pub sve2: bool, - pub i8mm: bool, - pub rdm: bool, - pub fp16arith: bool, - pub dot: bool, - pub jscvt: bool, - pub fcma: bool, - pub fhm: bool, - pub aes: bool, - pub sha1: bool, - pub sha2: bool, - pub pmull: bool, - pub crc32: bool, -} -extern "C" { - pub static mut cpuinfo_isa: cpuinfo_arm_isa; -} -extern "C" { - pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_cores() -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_packages() -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processors_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_cores_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_clusters_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_packages_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_uarchs_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l2_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l3_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l4_caches_count() -> u32; -} -extern "C" { - #[doc = " Returns upper bound on cache size."] - pub fn cpuinfo_get_max_cache_size() -> u32; -} -extern "C" { - #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] - pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; -} -extern "C" { - #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] - pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index() -> u32; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; -} diff --git a/src/bindings_aarch64_unknown_linux_gnu.rs b/src/bindings_aarch64_unknown_linux_gnu.rs deleted file mode 100644 index f3e4247..0000000 --- a/src/bindings_aarch64_unknown_linux_gnu.rs +++ /dev/null @@ -1,632 +0,0 @@ -/* automatically generated by rust-bindgen 0.69.4 */ - -#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] -#![allow(dead_code)] - -pub const CPUINFO_ARCH_ARM64: u32 = 1; -pub const CPUINFO_ARCH_X86: u32 = 0; -pub const CPUINFO_ARCH_X86_64: u32 = 0; -pub const CPUINFO_ARCH_ARM: u32 = 0; -pub const CPUINFO_ARCH_PPC64: u32 = 0; -pub const CPUINFO_ARCH_ASMJS: u32 = 0; -pub const CPUINFO_ARCH_WASM: u32 = 0; -pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; -pub const CPUINFO_ARCH_RISCV32: u32 = 0; -pub const CPUINFO_ARCH_RISCV64: u32 = 0; -pub const CPUINFO_CACHE_UNIFIED: u32 = 1; -pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; -pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; -pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; -pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; -pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; -pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; -pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; -pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; -pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; -pub type int_least64_t = i64; -pub type uint_least64_t = u64; -pub type int_fast64_t = i64; -pub type uint_fast64_t = u64; -pub type int_least32_t = i32; -pub type uint_least32_t = u32; -pub type int_fast32_t = i32; -pub type uint_fast32_t = u32; -pub type int_least16_t = i16; -pub type uint_least16_t = u16; -pub type int_fast16_t = i16; -pub type uint_fast16_t = u16; -pub type int_least8_t = i8; -pub type uint_least8_t = u8; -pub type int_fast8_t = i8; -pub type uint_fast8_t = u8; -pub type intmax_t = ::std::os::raw::c_long; -pub type uintmax_t = ::std::os::raw::c_ulong; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cache { - #[doc = " Cache size in bytes"] - pub size: u32, - #[doc = " Number of ways of associativity"] - pub associativity: u32, - #[doc = " Number of sets"] - pub sets: u32, - #[doc = " Number of partitions"] - pub partitions: u32, - #[doc = " Line size in bytes"] - pub line_size: u32, - #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] - pub flags: u32, - #[doc = " Index of the first logical processor that shares this cache"] - pub processor_start: u32, - #[doc = " Number of logical processors that share this cache"] - pub processor_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_trace_cache { - pub uops: u32, - pub associativity: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_tlb { - pub entries: u32, - pub associativity: u32, - pub pages: u64, -} -#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] -pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; -#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] -pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; -#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; -#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; -#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; -#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; -#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; -#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; -#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; -#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; -#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; -#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] -pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; -#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; -#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; -#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; -#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] -pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; -#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] -pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; -#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; -#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; -#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; -#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; -#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; -#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; -#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] -pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; -#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] -pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; -#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] -pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; -#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] -pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; -#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] -pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; -#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] -pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; -#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] -pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; -#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] -pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; -#[doc = " Vendor of processor core design"] -pub type cpuinfo_vendor = ::std::os::raw::c_uint; -#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] -pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; -#[doc = " Pentium and Pentium MMX microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; -#[doc = " Intel Quark microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; -#[doc = " Pentium Pro, Pentium II, and Pentium III."] -pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; -#[doc = " Pentium M."] -pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; -#[doc = " Intel Core microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; -#[doc = " Intel Core 2 microarchitecture on 65 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; -#[doc = " Intel Core 2 microarchitecture on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; -#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; -#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; -#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; -#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; -#[doc = " Intel Broadwell microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; -#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; -#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] -pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; -#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; -#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; -#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; -#[doc = " Pentium 4 with Prescott and later cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; -#[doc = " Intel Atom on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; -#[doc = " Intel Atom on 32 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; -#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; -#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; -#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; -#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; -#[doc = " Intel Knights Ferry HPC boards."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; -#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; -#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; -#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; -#[doc = " Intel Knights Mill Xeon Phi."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; -#[doc = " Intel/Marvell XScale series."] -pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; -#[doc = " AMD K5."] -pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; -#[doc = " AMD K6 and alike."] -pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; -#[doc = " AMD Athlon and Duron."] -pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; -#[doc = " AMD Athlon 64, Opteron 64."] -pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; -#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] -pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; -#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; -#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; -#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; -#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; -#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; -#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; -#[doc = " AMD Zen 3 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; -#[doc = " AMD Zen 4 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; -#[doc = " NSC Geode and AMD Geode GX and LX."] -pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; -#[doc = " AMD Bobcat mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; -#[doc = " AMD Jaguar mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; -#[doc = " AMD Puma mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; -#[doc = " ARM7 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; -#[doc = " ARM9 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; -#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; -#[doc = " ARM Cortex-A5."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; -#[doc = " ARM Cortex-A7."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; -#[doc = " ARM Cortex-A8."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; -#[doc = " ARM Cortex-A9."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; -#[doc = " ARM Cortex-A12."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; -#[doc = " ARM Cortex-A15."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; -#[doc = " ARM Cortex-A17."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; -#[doc = " ARM Cortex-A32."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; -#[doc = " ARM Cortex-A35."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; -#[doc = " ARM Cortex-A53."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; -#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; -#[doc = " ARM Cortex-A55."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; -#[doc = " ARM Cortex-A57."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; -#[doc = " ARM Cortex-A65."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; -#[doc = " ARM Cortex-A72."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; -#[doc = " ARM Cortex-A73."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; -#[doc = " ARM Cortex-A75."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; -#[doc = " ARM Cortex-A76."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; -#[doc = " ARM Cortex-A77."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; -#[doc = " ARM Cortex-A78."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; -#[doc = " ARM Neoverse N1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; -#[doc = " ARM Neoverse E1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; -#[doc = " ARM Neoverse V1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; -#[doc = " ARM Neoverse N2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; -#[doc = " ARM Neoverse V2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; -#[doc = " ARM Cortex-X1."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; -#[doc = " ARM Cortex-X2."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; -#[doc = " ARM Cortex-X3."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; -#[doc = " ARM Cortex-A510."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; -#[doc = " ARM Cortex-A710."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; -#[doc = " ARM Cortex-A715."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; -#[doc = " Qualcomm Scorpion."] -pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; -#[doc = " Qualcomm Krait."] -pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; -#[doc = " Qualcomm Kryo."] -pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; -#[doc = " Qualcomm Falkor."] -pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; -#[doc = " Qualcomm Saphira."] -pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; -#[doc = " Nvidia Denver."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; -#[doc = " Nvidia Denver 2."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; -#[doc = " Nvidia Carmel."] -pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; -#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; -#[doc = " Apple A6 and A6X processors."] -pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; -#[doc = " Apple A7 processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; -#[doc = " Apple A8 and A8X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; -#[doc = " Apple A9 and A9X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; -#[doc = " Apple A10 and A10X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; -#[doc = " Apple A11 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; -#[doc = " Apple A11 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; -#[doc = " Apple A12 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; -#[doc = " Apple A12 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; -#[doc = " Apple A13 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; -#[doc = " Apple A13 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; -#[doc = " Apple A14 / M1 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; -#[doc = " Apple A14 / M1 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; -#[doc = " Apple A15 / M2 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; -#[doc = " Apple A15 / M2 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; -#[doc = " Cavium ThunderX."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; -#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; -#[doc = " Marvell PJ4."] -pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; -#[doc = " Broadcom Brahma B15."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; -#[doc = " Broadcom Brahma B53."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; -#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] -pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; -#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] -pub type cpuinfo_uarch = ::std::os::raw::c_uint; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor { - #[doc = " SMT (hyperthread) ID within a core"] - pub smt_id: u32, - #[doc = " Core containing this logical processor"] - pub core: *const cpuinfo_core, - #[doc = " Cluster of cores containing this logical processor"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this logical processor"] - pub package: *const cpuinfo_package, - #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in\n /sys/devices/system/cpu/cpu/\n - Bit in the cpu_set_t identifies this logical processor"] - pub linux_id: ::std::os::raw::c_int, - pub cache: cpuinfo_processor__bindgen_ty_1, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor__bindgen_ty_1 { - #[doc = " Level 1 instruction cache"] - pub l1i: *const cpuinfo_cache, - #[doc = " Level 1 data cache"] - pub l1d: *const cpuinfo_cache, - #[doc = " Level 2 unified or data cache"] - pub l2: *const cpuinfo_cache, - #[doc = " Level 3 unified or data cache"] - pub l3: *const cpuinfo_cache, - #[doc = " Level 4 unified or data cache"] - pub l4: *const cpuinfo_cache, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_core { - #[doc = " Index of the first logical processor on this core."] - pub processor_start: u32, - #[doc = " Number of logical processors on this core"] - pub processor_count: u32, - #[doc = " Core ID within a package"] - pub core_id: u32, - #[doc = " Cluster containing this core"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this core."] - pub package: *const cpuinfo_package, - #[doc = " Vendor of the CPU microarchitecture for this core"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture for this core"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) for this core"] - pub midr: u32, - #[doc = " Clock rate (non-Turbo) of the core, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cluster { - #[doc = " Index of the first logical processor in the cluster"] - pub processor_start: u32, - #[doc = " Number of logical processors in the cluster"] - pub processor_count: u32, - #[doc = " Index of the first core in the cluster"] - pub core_start: u32, - #[doc = " Number of cores on the cluster"] - pub core_count: u32, - #[doc = " Cluster ID within a package"] - pub cluster_id: u32, - #[doc = " Physical package containing the cluster"] - pub package: *const cpuinfo_package, - #[doc = " CPU microarchitecture vendor of the cores in the cluster"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture of the cores in the cluster"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) of the cores in the cluster"] - pub midr: u32, - #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_package { - #[doc = " SoC or processor chip model name"] - pub name: [::std::os::raw::c_char; 48usize], - #[doc = " Index of the first logical processor on this physical package"] - pub processor_start: u32, - #[doc = " Number of logical processors on this physical package"] - pub processor_count: u32, - #[doc = " Index of the first core on this physical package"] - pub core_start: u32, - #[doc = " Number of cores on this physical package"] - pub core_count: u32, - #[doc = " Index of the first cluster of cores on this physical package"] - pub cluster_start: u32, - #[doc = " Number of clusters of cores on this physical package"] - pub cluster_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_uarch_info { - #[doc = " Type of CPU microarchitecture"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) for the microarchitecture"] - pub midr: u32, - #[doc = " Number of logical processors with the microarchitecture"] - pub processor_count: u32, - #[doc = " Number of cores with the microarchitecture"] - pub core_count: u32, -} -extern "C" { - pub fn cpuinfo_initialize() -> bool; -} -extern "C" { - pub fn cpuinfo_deinitialize(); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_arm_isa { - pub atomics: bool, - pub bf16: bool, - pub sve: bool, - pub sve2: bool, - pub i8mm: bool, - pub rdm: bool, - pub fp16arith: bool, - pub dot: bool, - pub jscvt: bool, - pub fcma: bool, - pub fhm: bool, - pub aes: bool, - pub sha1: bool, - pub sha2: bool, - pub pmull: bool, - pub crc32: bool, -} -extern "C" { - pub static mut cpuinfo_isa: cpuinfo_arm_isa; -} -extern "C" { - pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_cores() -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_packages() -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processors_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_cores_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_clusters_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_packages_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_uarchs_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l2_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l3_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l4_caches_count() -> u32; -} -extern "C" { - #[doc = " Returns upper bound on cache size."] - pub fn cpuinfo_get_max_cache_size() -> u32; -} -extern "C" { - #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] - pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; -} -extern "C" { - #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] - pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index() -> u32; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; -} diff --git a/src/bindings_armv7_unknown_linux_gnueabihf.rs b/src/bindings_armv7_unknown_linux_gnueabihf.rs deleted file mode 100644 index 44c0cb2..0000000 --- a/src/bindings_armv7_unknown_linux_gnueabihf.rs +++ /dev/null @@ -1,646 +0,0 @@ -/* automatically generated by rust-bindgen 0.69.4 */ - -#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] -#![allow(dead_code)] - -pub const CPUINFO_ARCH_ARM: u32 = 1; -pub const CPUINFO_ARCH_X86: u32 = 0; -pub const CPUINFO_ARCH_X86_64: u32 = 0; -pub const CPUINFO_ARCH_ARM64: u32 = 0; -pub const CPUINFO_ARCH_PPC64: u32 = 0; -pub const CPUINFO_ARCH_ASMJS: u32 = 0; -pub const CPUINFO_ARCH_WASM: u32 = 0; -pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; -pub const CPUINFO_ARCH_RISCV32: u32 = 0; -pub const CPUINFO_ARCH_RISCV64: u32 = 0; -pub const CPUINFO_CACHE_UNIFIED: u32 = 1; -pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; -pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; -pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; -pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; -pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; -pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; -pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; -pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; -pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; -pub type int_least64_t = i64; -pub type uint_least64_t = u64; -pub type int_fast64_t = i64; -pub type uint_fast64_t = u64; -pub type int_least32_t = i32; -pub type uint_least32_t = u32; -pub type int_fast32_t = i32; -pub type uint_fast32_t = u32; -pub type int_least16_t = i16; -pub type uint_least16_t = u16; -pub type int_fast16_t = i16; -pub type uint_fast16_t = u16; -pub type int_least8_t = i8; -pub type uint_least8_t = u8; -pub type int_fast8_t = i8; -pub type uint_fast8_t = u8; -pub type intmax_t = ::std::os::raw::c_longlong; -pub type uintmax_t = ::std::os::raw::c_ulonglong; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cache { - #[doc = " Cache size in bytes"] - pub size: u32, - #[doc = " Number of ways of associativity"] - pub associativity: u32, - #[doc = " Number of sets"] - pub sets: u32, - #[doc = " Number of partitions"] - pub partitions: u32, - #[doc = " Line size in bytes"] - pub line_size: u32, - #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] - pub flags: u32, - #[doc = " Index of the first logical processor that shares this cache"] - pub processor_start: u32, - #[doc = " Number of logical processors that share this cache"] - pub processor_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_trace_cache { - pub uops: u32, - pub associativity: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_tlb { - pub entries: u32, - pub associativity: u32, - pub pages: u64, -} -#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] -pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; -#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] -pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; -#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; -#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; -#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; -#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; -#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; -#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; -#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; -#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; -#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; -#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] -pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; -#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; -#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; -#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; -#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] -pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; -#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] -pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; -#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; -#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; -#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; -#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; -#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; -#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; -#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] -pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; -#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] -pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; -#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] -pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; -#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] -pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; -#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] -pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; -#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] -pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; -#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] -pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; -#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] -pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; -#[doc = " Vendor of processor core design"] -pub type cpuinfo_vendor = ::std::os::raw::c_uint; -#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] -pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; -#[doc = " Pentium and Pentium MMX microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; -#[doc = " Intel Quark microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; -#[doc = " Pentium Pro, Pentium II, and Pentium III."] -pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; -#[doc = " Pentium M."] -pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; -#[doc = " Intel Core microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; -#[doc = " Intel Core 2 microarchitecture on 65 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; -#[doc = " Intel Core 2 microarchitecture on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; -#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; -#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; -#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; -#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; -#[doc = " Intel Broadwell microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; -#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; -#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] -pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; -#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; -#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; -#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; -#[doc = " Pentium 4 with Prescott and later cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; -#[doc = " Intel Atom on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; -#[doc = " Intel Atom on 32 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; -#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; -#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; -#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; -#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; -#[doc = " Intel Knights Ferry HPC boards."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; -#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; -#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; -#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; -#[doc = " Intel Knights Mill Xeon Phi."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; -#[doc = " Intel/Marvell XScale series."] -pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; -#[doc = " AMD K5."] -pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; -#[doc = " AMD K6 and alike."] -pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; -#[doc = " AMD Athlon and Duron."] -pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; -#[doc = " AMD Athlon 64, Opteron 64."] -pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; -#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] -pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; -#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; -#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; -#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; -#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; -#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; -#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; -#[doc = " AMD Zen 3 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; -#[doc = " AMD Zen 4 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; -#[doc = " NSC Geode and AMD Geode GX and LX."] -pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; -#[doc = " AMD Bobcat mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; -#[doc = " AMD Jaguar mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; -#[doc = " AMD Puma mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; -#[doc = " ARM7 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; -#[doc = " ARM9 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; -#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; -#[doc = " ARM Cortex-A5."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; -#[doc = " ARM Cortex-A7."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; -#[doc = " ARM Cortex-A8."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; -#[doc = " ARM Cortex-A9."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; -#[doc = " ARM Cortex-A12."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; -#[doc = " ARM Cortex-A15."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; -#[doc = " ARM Cortex-A17."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; -#[doc = " ARM Cortex-A32."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; -#[doc = " ARM Cortex-A35."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; -#[doc = " ARM Cortex-A53."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; -#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; -#[doc = " ARM Cortex-A55."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; -#[doc = " ARM Cortex-A57."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; -#[doc = " ARM Cortex-A65."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; -#[doc = " ARM Cortex-A72."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; -#[doc = " ARM Cortex-A73."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; -#[doc = " ARM Cortex-A75."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; -#[doc = " ARM Cortex-A76."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; -#[doc = " ARM Cortex-A77."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; -#[doc = " ARM Cortex-A78."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; -#[doc = " ARM Neoverse N1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; -#[doc = " ARM Neoverse E1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; -#[doc = " ARM Neoverse V1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; -#[doc = " ARM Neoverse N2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; -#[doc = " ARM Neoverse V2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; -#[doc = " ARM Cortex-X1."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; -#[doc = " ARM Cortex-X2."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; -#[doc = " ARM Cortex-X3."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; -#[doc = " ARM Cortex-A510."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; -#[doc = " ARM Cortex-A710."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; -#[doc = " ARM Cortex-A715."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; -#[doc = " Qualcomm Scorpion."] -pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; -#[doc = " Qualcomm Krait."] -pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; -#[doc = " Qualcomm Kryo."] -pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; -#[doc = " Qualcomm Falkor."] -pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; -#[doc = " Qualcomm Saphira."] -pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; -#[doc = " Nvidia Denver."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; -#[doc = " Nvidia Denver 2."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; -#[doc = " Nvidia Carmel."] -pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; -#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; -#[doc = " Apple A6 and A6X processors."] -pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; -#[doc = " Apple A7 processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; -#[doc = " Apple A8 and A8X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; -#[doc = " Apple A9 and A9X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; -#[doc = " Apple A10 and A10X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; -#[doc = " Apple A11 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; -#[doc = " Apple A11 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; -#[doc = " Apple A12 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; -#[doc = " Apple A12 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; -#[doc = " Apple A13 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; -#[doc = " Apple A13 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; -#[doc = " Apple A14 / M1 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; -#[doc = " Apple A14 / M1 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; -#[doc = " Apple A15 / M2 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; -#[doc = " Apple A15 / M2 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; -#[doc = " Cavium ThunderX."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; -#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; -#[doc = " Marvell PJ4."] -pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; -#[doc = " Broadcom Brahma B15."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; -#[doc = " Broadcom Brahma B53."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; -#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] -pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; -#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] -pub type cpuinfo_uarch = ::std::os::raw::c_uint; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor { - #[doc = " SMT (hyperthread) ID within a core"] - pub smt_id: u32, - #[doc = " Core containing this logical processor"] - pub core: *const cpuinfo_core, - #[doc = " Cluster of cores containing this logical processor"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this logical processor"] - pub package: *const cpuinfo_package, - #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in\n /sys/devices/system/cpu/cpu/\n - Bit in the cpu_set_t identifies this logical processor"] - pub linux_id: ::std::os::raw::c_int, - pub cache: cpuinfo_processor__bindgen_ty_1, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor__bindgen_ty_1 { - #[doc = " Level 1 instruction cache"] - pub l1i: *const cpuinfo_cache, - #[doc = " Level 1 data cache"] - pub l1d: *const cpuinfo_cache, - #[doc = " Level 2 unified or data cache"] - pub l2: *const cpuinfo_cache, - #[doc = " Level 3 unified or data cache"] - pub l3: *const cpuinfo_cache, - #[doc = " Level 4 unified or data cache"] - pub l4: *const cpuinfo_cache, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_core { - #[doc = " Index of the first logical processor on this core."] - pub processor_start: u32, - #[doc = " Number of logical processors on this core"] - pub processor_count: u32, - #[doc = " Core ID within a package"] - pub core_id: u32, - #[doc = " Cluster containing this core"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this core."] - pub package: *const cpuinfo_package, - #[doc = " Vendor of the CPU microarchitecture for this core"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture for this core"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) for this core"] - pub midr: u32, - #[doc = " Clock rate (non-Turbo) of the core, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cluster { - #[doc = " Index of the first logical processor in the cluster"] - pub processor_start: u32, - #[doc = " Number of logical processors in the cluster"] - pub processor_count: u32, - #[doc = " Index of the first core in the cluster"] - pub core_start: u32, - #[doc = " Number of cores on the cluster"] - pub core_count: u32, - #[doc = " Cluster ID within a package"] - pub cluster_id: u32, - #[doc = " Physical package containing the cluster"] - pub package: *const cpuinfo_package, - #[doc = " CPU microarchitecture vendor of the cores in the cluster"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture of the cores in the cluster"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) of the cores in the cluster"] - pub midr: u32, - #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_package { - #[doc = " SoC or processor chip model name"] - pub name: [::std::os::raw::c_char; 48usize], - #[doc = " Index of the first logical processor on this physical package"] - pub processor_start: u32, - #[doc = " Number of logical processors on this physical package"] - pub processor_count: u32, - #[doc = " Index of the first core on this physical package"] - pub core_start: u32, - #[doc = " Number of cores on this physical package"] - pub core_count: u32, - #[doc = " Index of the first cluster of cores on this physical package"] - pub cluster_start: u32, - #[doc = " Number of clusters of cores on this physical package"] - pub cluster_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_uarch_info { - #[doc = " Type of CPU microarchitecture"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of Main ID Register (MIDR) for the microarchitecture"] - pub midr: u32, - #[doc = " Number of logical processors with the microarchitecture"] - pub processor_count: u32, - #[doc = " Number of cores with the microarchitecture"] - pub core_count: u32, -} -extern "C" { - pub fn cpuinfo_initialize() -> bool; -} -extern "C" { - pub fn cpuinfo_deinitialize(); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_arm_isa { - pub thumb: bool, - pub thumb2: bool, - pub thumbee: bool, - pub jazelle: bool, - pub armv5e: bool, - pub armv6: bool, - pub armv6k: bool, - pub armv7: bool, - pub armv7mp: bool, - pub armv8: bool, - pub idiv: bool, - pub vfpv2: bool, - pub vfpv3: bool, - pub d32: bool, - pub fp16: bool, - pub fma: bool, - pub wmmx: bool, - pub wmmx2: bool, - pub neon: bool, - pub rdm: bool, - pub fp16arith: bool, - pub dot: bool, - pub jscvt: bool, - pub fcma: bool, - pub fhm: bool, - pub aes: bool, - pub sha1: bool, - pub sha2: bool, - pub pmull: bool, - pub crc32: bool, -} -extern "C" { - pub static mut cpuinfo_isa: cpuinfo_arm_isa; -} -extern "C" { - pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_cores() -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_packages() -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processors_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_cores_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_clusters_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_packages_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_uarchs_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l2_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l3_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l4_caches_count() -> u32; -} -extern "C" { - #[doc = " Returns upper bound on cache size."] - pub fn cpuinfo_get_max_cache_size() -> u32; -} -extern "C" { - #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] - pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; -} -extern "C" { - #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] - pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index() -> u32; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; -} diff --git a/src/bindings_x86_64_pc_windows_msvc.rs b/src/bindings_x86_64_pc_windows_msvc.rs deleted file mode 100644 index 940dab5..0000000 --- a/src/bindings_x86_64_pc_windows_msvc.rs +++ /dev/null @@ -1,749 +0,0 @@ -/* automatically generated by rust-bindgen 0.69.4 */ - -#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] -#![allow(dead_code)] - -pub const _VCRT_COMPILER_PREPROCESSOR: u32 = 1; -pub const _SAL_VERSION: u32 = 20; -pub const __SAL_H_VERSION: u32 = 180000000; -pub const _USE_DECLSPECS_FOR_SAL: u32 = 0; -pub const _USE_ATTRIBUTES_FOR_SAL: u32 = 0; -pub const _CRT_PACKING: u32 = 8; -pub const _HAS_EXCEPTIONS: u32 = 1; -pub const NULL: u32 = 0; -pub const _HAS_CXX17: u32 = 0; -pub const _HAS_CXX20: u32 = 0; -pub const _HAS_CXX23: u32 = 0; -pub const _HAS_NODISCARD: u32 = 1; -pub const WCHAR_MIN: u32 = 0; -pub const WCHAR_MAX: u32 = 65535; -pub const WINT_MIN: u32 = 0; -pub const WINT_MAX: u32 = 65535; -pub const CPUINFO_ARCH_X86_64: u32 = 1; -pub const CPUINFO_ARCH_X86: u32 = 0; -pub const CPUINFO_ARCH_ARM: u32 = 0; -pub const CPUINFO_ARCH_ARM64: u32 = 0; -pub const CPUINFO_ARCH_PPC64: u32 = 0; -pub const CPUINFO_ARCH_ASMJS: u32 = 0; -pub const CPUINFO_ARCH_WASM: u32 = 0; -pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; -pub const CPUINFO_ARCH_RISCV32: u32 = 0; -pub const CPUINFO_ARCH_RISCV64: u32 = 0; -pub const CPUINFO_CACHE_UNIFIED: u32 = 1; -pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; -pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; -pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; -pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; -pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; -pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; -pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; -pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; -pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; -pub type va_list = *mut ::std::os::raw::c_char; -extern "C" { - pub fn __va_start(arg1: *mut va_list, ...); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct __vcrt_va_list_is_reference { - pub _address: u8, -} -pub const __vcrt_va_list_is_reference___the_value: __vcrt_va_list_is_reference__bindgen_ty_1 = - false; -pub type __vcrt_va_list_is_reference__bindgen_ty_1 = bool; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct __vcrt_assert_va_start_is_not_reference { - pub _address: u8, -} -pub type __vcrt_bool = bool; -extern "C" { - pub fn __security_init_cookie(); -} -extern "C" { - pub fn __security_check_cookie(_StackCookie: usize); -} -extern "C" { - pub fn __report_gsfailure(_StackCookie: usize) -> !; -} -extern "C" { - pub static mut __security_cookie: usize; -} -pub type int_least8_t = ::std::os::raw::c_schar; -pub type int_least16_t = ::std::os::raw::c_short; -pub type int_least32_t = ::std::os::raw::c_int; -pub type int_least64_t = ::std::os::raw::c_longlong; -pub type uint_least8_t = ::std::os::raw::c_uchar; -pub type uint_least16_t = ::std::os::raw::c_ushort; -pub type uint_least32_t = ::std::os::raw::c_uint; -pub type uint_least64_t = ::std::os::raw::c_ulonglong; -pub type int_fast8_t = ::std::os::raw::c_schar; -pub type int_fast16_t = ::std::os::raw::c_int; -pub type int_fast32_t = ::std::os::raw::c_int; -pub type int_fast64_t = ::std::os::raw::c_longlong; -pub type uint_fast8_t = ::std::os::raw::c_uchar; -pub type uint_fast16_t = ::std::os::raw::c_uint; -pub type uint_fast32_t = ::std::os::raw::c_uint; -pub type uint_fast64_t = ::std::os::raw::c_ulonglong; -pub type intmax_t = ::std::os::raw::c_longlong; -pub type uintmax_t = ::std::os::raw::c_ulonglong; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cache { - #[doc = " Cache size in bytes"] - pub size: u32, - #[doc = " Number of ways of associativity"] - pub associativity: u32, - #[doc = " Number of sets"] - pub sets: u32, - #[doc = " Number of partitions"] - pub partitions: u32, - #[doc = " Line size in bytes"] - pub line_size: u32, - #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] - pub flags: u32, - #[doc = " Index of the first logical processor that shares this cache"] - pub processor_start: u32, - #[doc = " Number of logical processors that share this cache"] - pub processor_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_trace_cache { - pub uops: u32, - pub associativity: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_tlb { - pub entries: u32, - pub associativity: u32, - pub pages: u64, -} -#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] -pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; -#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] -pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; -#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; -#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; -#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; -#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; -#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; -#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; -#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; -#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; -#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; -#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] -pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; -#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; -#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; -#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; -#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] -pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; -#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] -pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; -#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; -#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; -#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; -#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; -#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; -#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; -#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] -pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; -#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] -pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; -#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] -pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; -#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] -pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; -#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] -pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; -#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] -pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; -#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] -pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; -#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] -pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; -#[doc = " Vendor of processor core design"] -pub type cpuinfo_vendor = ::std::os::raw::c_int; -#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] -pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; -#[doc = " Pentium and Pentium MMX microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; -#[doc = " Intel Quark microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; -#[doc = " Pentium Pro, Pentium II, and Pentium III."] -pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; -#[doc = " Pentium M."] -pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; -#[doc = " Intel Core microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; -#[doc = " Intel Core 2 microarchitecture on 65 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; -#[doc = " Intel Core 2 microarchitecture on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; -#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; -#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; -#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; -#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; -#[doc = " Intel Broadwell microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; -#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; -#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] -pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; -#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; -#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; -#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; -#[doc = " Pentium 4 with Prescott and later cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; -#[doc = " Intel Atom on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; -#[doc = " Intel Atom on 32 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; -#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; -#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; -#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; -#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; -#[doc = " Intel Knights Ferry HPC boards."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; -#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; -#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; -#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; -#[doc = " Intel Knights Mill Xeon Phi."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; -#[doc = " Intel/Marvell XScale series."] -pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; -#[doc = " AMD K5."] -pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; -#[doc = " AMD K6 and alike."] -pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; -#[doc = " AMD Athlon and Duron."] -pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; -#[doc = " AMD Athlon 64, Opteron 64."] -pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; -#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] -pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; -#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; -#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; -#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; -#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; -#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; -#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; -#[doc = " AMD Zen 3 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; -#[doc = " AMD Zen 4 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; -#[doc = " NSC Geode and AMD Geode GX and LX."] -pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; -#[doc = " AMD Bobcat mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; -#[doc = " AMD Jaguar mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; -#[doc = " AMD Puma mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; -#[doc = " ARM7 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; -#[doc = " ARM9 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; -#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; -#[doc = " ARM Cortex-A5."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; -#[doc = " ARM Cortex-A7."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; -#[doc = " ARM Cortex-A8."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; -#[doc = " ARM Cortex-A9."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; -#[doc = " ARM Cortex-A12."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; -#[doc = " ARM Cortex-A15."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; -#[doc = " ARM Cortex-A17."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; -#[doc = " ARM Cortex-A32."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; -#[doc = " ARM Cortex-A35."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; -#[doc = " ARM Cortex-A53."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; -#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; -#[doc = " ARM Cortex-A55."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; -#[doc = " ARM Cortex-A57."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; -#[doc = " ARM Cortex-A65."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; -#[doc = " ARM Cortex-A72."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; -#[doc = " ARM Cortex-A73."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; -#[doc = " ARM Cortex-A75."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; -#[doc = " ARM Cortex-A76."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; -#[doc = " ARM Cortex-A77."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; -#[doc = " ARM Cortex-A78."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; -#[doc = " ARM Neoverse N1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; -#[doc = " ARM Neoverse E1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; -#[doc = " ARM Neoverse V1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; -#[doc = " ARM Neoverse N2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; -#[doc = " ARM Neoverse V2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; -#[doc = " ARM Cortex-X1."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; -#[doc = " ARM Cortex-X2."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; -#[doc = " ARM Cortex-X3."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; -#[doc = " ARM Cortex-A510."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; -#[doc = " ARM Cortex-A710."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; -#[doc = " ARM Cortex-A715."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; -#[doc = " Qualcomm Scorpion."] -pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; -#[doc = " Qualcomm Krait."] -pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; -#[doc = " Qualcomm Kryo."] -pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; -#[doc = " Qualcomm Falkor."] -pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; -#[doc = " Qualcomm Saphira."] -pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; -#[doc = " Nvidia Denver."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; -#[doc = " Nvidia Denver 2."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; -#[doc = " Nvidia Carmel."] -pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; -#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; -#[doc = " Apple A6 and A6X processors."] -pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; -#[doc = " Apple A7 processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; -#[doc = " Apple A8 and A8X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; -#[doc = " Apple A9 and A9X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; -#[doc = " Apple A10 and A10X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; -#[doc = " Apple A11 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; -#[doc = " Apple A11 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; -#[doc = " Apple A12 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; -#[doc = " Apple A12 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; -#[doc = " Apple A13 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; -#[doc = " Apple A13 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; -#[doc = " Apple A14 / M1 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; -#[doc = " Apple A14 / M1 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; -#[doc = " Apple A15 / M2 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; -#[doc = " Apple A15 / M2 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; -#[doc = " Cavium ThunderX."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; -#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; -#[doc = " Marvell PJ4."] -pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; -#[doc = " Broadcom Brahma B15."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; -#[doc = " Broadcom Brahma B53."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; -#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] -pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; -#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] -pub type cpuinfo_uarch = ::std::os::raw::c_int; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor { - #[doc = " SMT (hyperthread) ID within a core"] - pub smt_id: u32, - #[doc = " Core containing this logical processor"] - pub core: *const cpuinfo_core, - #[doc = " Cluster of cores containing this logical processor"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this logical processor"] - pub package: *const cpuinfo_package, - #[doc = " Windows-specific ID for the group containing the logical processor."] - pub windows_group_id: u16, - #[doc = " Windows-specific ID of the logical processor within its group:\n - Bit in the KAFFINITY mask identifies this\n logical processor within its group."] - pub windows_processor_id: u16, - #[doc = " APIC ID (unique x86-specific ID of the logical processor)"] - pub apic_id: u32, - pub cache: cpuinfo_processor__bindgen_ty_1, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor__bindgen_ty_1 { - #[doc = " Level 1 instruction cache"] - pub l1i: *const cpuinfo_cache, - #[doc = " Level 1 data cache"] - pub l1d: *const cpuinfo_cache, - #[doc = " Level 2 unified or data cache"] - pub l2: *const cpuinfo_cache, - #[doc = " Level 3 unified or data cache"] - pub l3: *const cpuinfo_cache, - #[doc = " Level 4 unified or data cache"] - pub l4: *const cpuinfo_cache, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_core { - #[doc = " Index of the first logical processor on this core."] - pub processor_start: u32, - #[doc = " Number of logical processors on this core"] - pub processor_count: u32, - #[doc = " Core ID within a package"] - pub core_id: u32, - #[doc = " Cluster containing this core"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this core."] - pub package: *const cpuinfo_package, - #[doc = " Vendor of the CPU microarchitecture for this core"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture for this core"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register for this core"] - pub cpuid: u32, - #[doc = " Clock rate (non-Turbo) of the core, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cluster { - #[doc = " Index of the first logical processor in the cluster"] - pub processor_start: u32, - #[doc = " Number of logical processors in the cluster"] - pub processor_count: u32, - #[doc = " Index of the first core in the cluster"] - pub core_start: u32, - #[doc = " Number of cores on the cluster"] - pub core_count: u32, - #[doc = " Cluster ID within a package"] - pub cluster_id: u32, - #[doc = " Physical package containing the cluster"] - pub package: *const cpuinfo_package, - #[doc = " CPU microarchitecture vendor of the cores in the cluster"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture of the cores in the cluster"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register of the cores in the cluster"] - pub cpuid: u32, - #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_package { - #[doc = " SoC or processor chip model name"] - pub name: [::std::os::raw::c_char; 48usize], - #[doc = " Index of the first logical processor on this physical package"] - pub processor_start: u32, - #[doc = " Number of logical processors on this physical package"] - pub processor_count: u32, - #[doc = " Index of the first core on this physical package"] - pub core_start: u32, - #[doc = " Number of cores on this physical package"] - pub core_count: u32, - #[doc = " Index of the first cluster of cores on this physical package"] - pub cluster_start: u32, - #[doc = " Number of clusters of cores on this physical package"] - pub cluster_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_uarch_info { - #[doc = " Type of CPU microarchitecture"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture"] - pub cpuid: u32, - #[doc = " Number of logical processors with the microarchitecture"] - pub processor_count: u32, - #[doc = " Number of cores with the microarchitecture"] - pub core_count: u32, -} -extern "C" { - pub fn cpuinfo_initialize() -> bool; -} -extern "C" { - pub fn cpuinfo_deinitialize(); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_x86_isa { - pub rdtscp: bool, - pub rdpid: bool, - pub sysenter: bool, - pub msr: bool, - pub clzero: bool, - pub clflush: bool, - pub clflushopt: bool, - pub mwait: bool, - pub mwaitx: bool, - pub fxsave: bool, - pub xsave: bool, - pub three_d_now: bool, - pub three_d_now_plus: bool, - pub prefetch: bool, - pub prefetchw: bool, - pub prefetchwt1: bool, - pub sse3: bool, - pub ssse3: bool, - pub sse4_1: bool, - pub sse4_2: bool, - pub sse4a: bool, - pub misaligned_sse: bool, - pub avx: bool, - pub avxvnni: bool, - pub fma3: bool, - pub fma4: bool, - pub xop: bool, - pub f16c: bool, - pub avx2: bool, - pub avx512f: bool, - pub avx512pf: bool, - pub avx512er: bool, - pub avx512cd: bool, - pub avx512dq: bool, - pub avx512bw: bool, - pub avx512vl: bool, - pub avx512ifma: bool, - pub avx512vbmi: bool, - pub avx512vbmi2: bool, - pub avx512bitalg: bool, - pub avx512vpopcntdq: bool, - pub avx512vnni: bool, - pub avx512bf16: bool, - pub avx512fp16: bool, - pub avx512vp2intersect: bool, - pub avx512_4vnniw: bool, - pub avx512_4fmaps: bool, - pub amx_bf16: bool, - pub amx_tile: bool, - pub amx_int8: bool, - pub amx_fp16: bool, - pub avx_vnni_int8: bool, - pub avx_vnni_int16: bool, - pub avx_ne_convert: bool, - pub hle: bool, - pub rtm: bool, - pub xtest: bool, - pub mpx: bool, - pub cmpxchg16b: bool, - pub clwb: bool, - pub movbe: bool, - pub lahf_sahf: bool, - pub fs_gs_base: bool, - pub lzcnt: bool, - pub popcnt: bool, - pub tbm: bool, - pub bmi: bool, - pub bmi2: bool, - pub adx: bool, - pub aes: bool, - pub vaes: bool, - pub pclmulqdq: bool, - pub vpclmulqdq: bool, - pub gfni: bool, - pub rdrand: bool, - pub rdseed: bool, - pub sha: bool, - pub rng: bool, - pub ace: bool, - pub ace2: bool, - pub phe: bool, - pub pmm: bool, - pub lwp: bool, -} -extern "C" { - pub static mut cpuinfo_isa: cpuinfo_x86_isa; -} -extern "C" { - pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_cores() -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_packages() -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processors_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_cores_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_clusters_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_packages_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_uarchs_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l2_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l3_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l4_caches_count() -> u32; -} -extern "C" { - #[doc = " Returns upper bound on cache size."] - pub fn cpuinfo_get_max_cache_size() -> u32; -} -extern "C" { - #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] - pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; -} -extern "C" { - #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] - pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index() -> u32; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; -} diff --git a/src/bindings_x86_64_unknown_freebsd.rs b/src/bindings_x86_64_unknown_freebsd.rs deleted file mode 100644 index 356dc27..0000000 --- a/src/bindings_x86_64_unknown_freebsd.rs +++ /dev/null @@ -1,699 +0,0 @@ -/* automatically generated by rust-bindgen 0.69.4 */ - -#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] -#![allow(dead_code)] - -pub const CPUINFO_ARCH_X86_64: u32 = 1; -pub const CPUINFO_ARCH_X86: u32 = 0; -pub const CPUINFO_ARCH_ARM: u32 = 0; -pub const CPUINFO_ARCH_ARM64: u32 = 0; -pub const CPUINFO_ARCH_PPC64: u32 = 0; -pub const CPUINFO_ARCH_ASMJS: u32 = 0; -pub const CPUINFO_ARCH_WASM: u32 = 0; -pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; -pub const CPUINFO_ARCH_RISCV32: u32 = 0; -pub const CPUINFO_ARCH_RISCV64: u32 = 0; -pub const CPUINFO_CACHE_UNIFIED: u32 = 1; -pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; -pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; -pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; -pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; -pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; -pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; -pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; -pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; -pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; -pub type int_least64_t = i64; -pub type uint_least64_t = u64; -pub type int_fast64_t = i64; -pub type uint_fast64_t = u64; -pub type int_least32_t = i32; -pub type uint_least32_t = u32; -pub type int_fast32_t = i32; -pub type uint_fast32_t = u32; -pub type int_least16_t = i16; -pub type uint_least16_t = u16; -pub type int_fast16_t = i16; -pub type uint_fast16_t = u16; -pub type int_least8_t = i8; -pub type uint_least8_t = u8; -pub type int_fast8_t = i8; -pub type uint_fast8_t = u8; -pub type intmax_t = ::std::os::raw::c_long; -pub type uintmax_t = ::std::os::raw::c_ulong; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cache { - #[doc = " Cache size in bytes"] - pub size: u32, - #[doc = " Number of ways of associativity"] - pub associativity: u32, - #[doc = " Number of sets"] - pub sets: u32, - #[doc = " Number of partitions"] - pub partitions: u32, - #[doc = " Line size in bytes"] - pub line_size: u32, - #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] - pub flags: u32, - #[doc = " Index of the first logical processor that shares this cache"] - pub processor_start: u32, - #[doc = " Number of logical processors that share this cache"] - pub processor_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_trace_cache { - pub uops: u32, - pub associativity: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_tlb { - pub entries: u32, - pub associativity: u32, - pub pages: u64, -} -#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] -pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; -#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] -pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; -#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; -#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; -#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; -#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; -#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; -#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; -#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; -#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; -#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; -#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] -pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; -#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; -#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; -#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; -#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] -pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; -#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] -pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; -#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; -#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; -#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; -#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; -#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; -#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; -#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] -pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; -#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] -pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; -#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] -pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; -#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] -pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; -#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] -pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; -#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] -pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; -#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] -pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; -#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] -pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; -#[doc = " Vendor of processor core design"] -pub type cpuinfo_vendor = ::std::os::raw::c_uint; -#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] -pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; -#[doc = " Pentium and Pentium MMX microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; -#[doc = " Intel Quark microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; -#[doc = " Pentium Pro, Pentium II, and Pentium III."] -pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; -#[doc = " Pentium M."] -pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; -#[doc = " Intel Core microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; -#[doc = " Intel Core 2 microarchitecture on 65 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; -#[doc = " Intel Core 2 microarchitecture on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; -#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; -#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; -#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; -#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; -#[doc = " Intel Broadwell microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; -#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; -#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] -pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; -#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; -#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; -#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; -#[doc = " Pentium 4 with Prescott and later cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; -#[doc = " Intel Atom on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; -#[doc = " Intel Atom on 32 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; -#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; -#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; -#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; -#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; -#[doc = " Intel Knights Ferry HPC boards."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; -#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; -#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; -#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; -#[doc = " Intel Knights Mill Xeon Phi."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; -#[doc = " Intel/Marvell XScale series."] -pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; -#[doc = " AMD K5."] -pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; -#[doc = " AMD K6 and alike."] -pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; -#[doc = " AMD Athlon and Duron."] -pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; -#[doc = " AMD Athlon 64, Opteron 64."] -pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; -#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] -pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; -#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; -#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; -#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; -#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; -#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; -#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; -#[doc = " AMD Zen 3 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; -#[doc = " AMD Zen 4 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; -#[doc = " NSC Geode and AMD Geode GX and LX."] -pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; -#[doc = " AMD Bobcat mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; -#[doc = " AMD Jaguar mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; -#[doc = " AMD Puma mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; -#[doc = " ARM7 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; -#[doc = " ARM9 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; -#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; -#[doc = " ARM Cortex-A5."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; -#[doc = " ARM Cortex-A7."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; -#[doc = " ARM Cortex-A8."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; -#[doc = " ARM Cortex-A9."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; -#[doc = " ARM Cortex-A12."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; -#[doc = " ARM Cortex-A15."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; -#[doc = " ARM Cortex-A17."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; -#[doc = " ARM Cortex-A32."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; -#[doc = " ARM Cortex-A35."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; -#[doc = " ARM Cortex-A53."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; -#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; -#[doc = " ARM Cortex-A55."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; -#[doc = " ARM Cortex-A57."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; -#[doc = " ARM Cortex-A65."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; -#[doc = " ARM Cortex-A72."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; -#[doc = " ARM Cortex-A73."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; -#[doc = " ARM Cortex-A75."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; -#[doc = " ARM Cortex-A76."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; -#[doc = " ARM Cortex-A77."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; -#[doc = " ARM Cortex-A78."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; -#[doc = " ARM Neoverse N1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; -#[doc = " ARM Neoverse E1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; -#[doc = " ARM Neoverse V1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; -#[doc = " ARM Neoverse N2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; -#[doc = " ARM Neoverse V2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; -#[doc = " ARM Cortex-X1."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; -#[doc = " ARM Cortex-X2."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; -#[doc = " ARM Cortex-X3."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; -#[doc = " ARM Cortex-A510."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; -#[doc = " ARM Cortex-A710."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; -#[doc = " ARM Cortex-A715."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; -#[doc = " Qualcomm Scorpion."] -pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; -#[doc = " Qualcomm Krait."] -pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; -#[doc = " Qualcomm Kryo."] -pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; -#[doc = " Qualcomm Falkor."] -pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; -#[doc = " Qualcomm Saphira."] -pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; -#[doc = " Nvidia Denver."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; -#[doc = " Nvidia Denver 2."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; -#[doc = " Nvidia Carmel."] -pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; -#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; -#[doc = " Apple A6 and A6X processors."] -pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; -#[doc = " Apple A7 processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; -#[doc = " Apple A8 and A8X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; -#[doc = " Apple A9 and A9X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; -#[doc = " Apple A10 and A10X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; -#[doc = " Apple A11 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; -#[doc = " Apple A11 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; -#[doc = " Apple A12 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; -#[doc = " Apple A12 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; -#[doc = " Apple A13 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; -#[doc = " Apple A13 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; -#[doc = " Apple A14 / M1 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; -#[doc = " Apple A14 / M1 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; -#[doc = " Apple A15 / M2 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; -#[doc = " Apple A15 / M2 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; -#[doc = " Cavium ThunderX."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; -#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; -#[doc = " Marvell PJ4."] -pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; -#[doc = " Broadcom Brahma B15."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; -#[doc = " Broadcom Brahma B53."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; -#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] -pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; -#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] -pub type cpuinfo_uarch = ::std::os::raw::c_uint; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor { - #[doc = " SMT (hyperthread) ID within a core"] - pub smt_id: u32, - #[doc = " Core containing this logical processor"] - pub core: *const cpuinfo_core, - #[doc = " Cluster of cores containing this logical processor"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this logical processor"] - pub package: *const cpuinfo_package, - #[doc = " APIC ID (unique x86-specific ID of the logical processor)"] - pub apic_id: u32, - pub cache: cpuinfo_processor__bindgen_ty_1, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor__bindgen_ty_1 { - #[doc = " Level 1 instruction cache"] - pub l1i: *const cpuinfo_cache, - #[doc = " Level 1 data cache"] - pub l1d: *const cpuinfo_cache, - #[doc = " Level 2 unified or data cache"] - pub l2: *const cpuinfo_cache, - #[doc = " Level 3 unified or data cache"] - pub l3: *const cpuinfo_cache, - #[doc = " Level 4 unified or data cache"] - pub l4: *const cpuinfo_cache, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_core { - #[doc = " Index of the first logical processor on this core."] - pub processor_start: u32, - #[doc = " Number of logical processors on this core"] - pub processor_count: u32, - #[doc = " Core ID within a package"] - pub core_id: u32, - #[doc = " Cluster containing this core"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this core."] - pub package: *const cpuinfo_package, - #[doc = " Vendor of the CPU microarchitecture for this core"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture for this core"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register for this core"] - pub cpuid: u32, - #[doc = " Clock rate (non-Turbo) of the core, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cluster { - #[doc = " Index of the first logical processor in the cluster"] - pub processor_start: u32, - #[doc = " Number of logical processors in the cluster"] - pub processor_count: u32, - #[doc = " Index of the first core in the cluster"] - pub core_start: u32, - #[doc = " Number of cores on the cluster"] - pub core_count: u32, - #[doc = " Cluster ID within a package"] - pub cluster_id: u32, - #[doc = " Physical package containing the cluster"] - pub package: *const cpuinfo_package, - #[doc = " CPU microarchitecture vendor of the cores in the cluster"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture of the cores in the cluster"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register of the cores in the cluster"] - pub cpuid: u32, - #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_package { - #[doc = " SoC or processor chip model name"] - pub name: [::std::os::raw::c_char; 48usize], - #[doc = " Index of the first logical processor on this physical package"] - pub processor_start: u32, - #[doc = " Number of logical processors on this physical package"] - pub processor_count: u32, - #[doc = " Index of the first core on this physical package"] - pub core_start: u32, - #[doc = " Number of cores on this physical package"] - pub core_count: u32, - #[doc = " Index of the first cluster of cores on this physical package"] - pub cluster_start: u32, - #[doc = " Number of clusters of cores on this physical package"] - pub cluster_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_uarch_info { - #[doc = " Type of CPU microarchitecture"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture"] - pub cpuid: u32, - #[doc = " Number of logical processors with the microarchitecture"] - pub processor_count: u32, - #[doc = " Number of cores with the microarchitecture"] - pub core_count: u32, -} -extern "C" { - pub fn cpuinfo_initialize() -> bool; -} -extern "C" { - pub fn cpuinfo_deinitialize(); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_x86_isa { - pub rdtscp: bool, - pub rdpid: bool, - pub sysenter: bool, - pub msr: bool, - pub clzero: bool, - pub clflush: bool, - pub clflushopt: bool, - pub mwait: bool, - pub mwaitx: bool, - pub fxsave: bool, - pub xsave: bool, - pub three_d_now: bool, - pub three_d_now_plus: bool, - pub prefetch: bool, - pub prefetchw: bool, - pub prefetchwt1: bool, - pub sse3: bool, - pub ssse3: bool, - pub sse4_1: bool, - pub sse4_2: bool, - pub sse4a: bool, - pub misaligned_sse: bool, - pub avx: bool, - pub avxvnni: bool, - pub fma3: bool, - pub fma4: bool, - pub xop: bool, - pub f16c: bool, - pub avx2: bool, - pub avx512f: bool, - pub avx512pf: bool, - pub avx512er: bool, - pub avx512cd: bool, - pub avx512dq: bool, - pub avx512bw: bool, - pub avx512vl: bool, - pub avx512ifma: bool, - pub avx512vbmi: bool, - pub avx512vbmi2: bool, - pub avx512bitalg: bool, - pub avx512vpopcntdq: bool, - pub avx512vnni: bool, - pub avx512bf16: bool, - pub avx512fp16: bool, - pub avx512vp2intersect: bool, - pub avx512_4vnniw: bool, - pub avx512_4fmaps: bool, - pub amx_bf16: bool, - pub amx_tile: bool, - pub amx_int8: bool, - pub amx_fp16: bool, - pub avx_vnni_int8: bool, - pub avx_vnni_int16: bool, - pub avx_ne_convert: bool, - pub hle: bool, - pub rtm: bool, - pub xtest: bool, - pub mpx: bool, - pub cmpxchg16b: bool, - pub clwb: bool, - pub movbe: bool, - pub lahf_sahf: bool, - pub fs_gs_base: bool, - pub lzcnt: bool, - pub popcnt: bool, - pub tbm: bool, - pub bmi: bool, - pub bmi2: bool, - pub adx: bool, - pub aes: bool, - pub vaes: bool, - pub pclmulqdq: bool, - pub vpclmulqdq: bool, - pub gfni: bool, - pub rdrand: bool, - pub rdseed: bool, - pub sha: bool, - pub rng: bool, - pub ace: bool, - pub ace2: bool, - pub phe: bool, - pub pmm: bool, - pub lwp: bool, -} -extern "C" { - pub static mut cpuinfo_isa: cpuinfo_x86_isa; -} -extern "C" { - pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_cores() -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_packages() -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processors_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_cores_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_clusters_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_packages_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_uarchs_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l2_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l3_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l4_caches_count() -> u32; -} -extern "C" { - #[doc = " Returns upper bound on cache size."] - pub fn cpuinfo_get_max_cache_size() -> u32; -} -extern "C" { - #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] - pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; -} -extern "C" { - #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] - pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index() -> u32; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; -} diff --git a/src/bindings_x86_64_unknown_linux_gnu.rs b/src/bindings_x86_64_unknown_linux_gnu.rs deleted file mode 100644 index 3160d12..0000000 --- a/src/bindings_x86_64_unknown_linux_gnu.rs +++ /dev/null @@ -1,701 +0,0 @@ -/* automatically generated by rust-bindgen 0.69.4 */ - -#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] -#![allow(dead_code)] - -pub const CPUINFO_ARCH_X86_64: u32 = 1; -pub const CPUINFO_ARCH_X86: u32 = 0; -pub const CPUINFO_ARCH_ARM: u32 = 0; -pub const CPUINFO_ARCH_ARM64: u32 = 0; -pub const CPUINFO_ARCH_PPC64: u32 = 0; -pub const CPUINFO_ARCH_ASMJS: u32 = 0; -pub const CPUINFO_ARCH_WASM: u32 = 0; -pub const CPUINFO_ARCH_WASMSIMD: u32 = 0; -pub const CPUINFO_ARCH_RISCV32: u32 = 0; -pub const CPUINFO_ARCH_RISCV64: u32 = 0; -pub const CPUINFO_CACHE_UNIFIED: u32 = 1; -pub const CPUINFO_CACHE_INCLUSIVE: u32 = 2; -pub const CPUINFO_CACHE_COMPLEX_INDEXING: u32 = 4; -pub const CPUINFO_PAGE_SIZE_4KB: u32 = 4096; -pub const CPUINFO_PAGE_SIZE_1MB: u32 = 1048576; -pub const CPUINFO_PAGE_SIZE_2MB: u32 = 2097152; -pub const CPUINFO_PAGE_SIZE_4MB: u32 = 4194304; -pub const CPUINFO_PAGE_SIZE_16MB: u32 = 16777216; -pub const CPUINFO_PAGE_SIZE_1GB: u32 = 1073741824; -pub const CPUINFO_PACKAGE_NAME_MAX: u32 = 48; -pub type int_least64_t = i64; -pub type uint_least64_t = u64; -pub type int_fast64_t = i64; -pub type uint_fast64_t = u64; -pub type int_least32_t = i32; -pub type uint_least32_t = u32; -pub type int_fast32_t = i32; -pub type uint_fast32_t = u32; -pub type int_least16_t = i16; -pub type uint_least16_t = u16; -pub type int_fast16_t = i16; -pub type uint_fast16_t = u16; -pub type int_least8_t = i8; -pub type uint_least8_t = u8; -pub type int_fast8_t = i8; -pub type uint_fast8_t = u8; -pub type intmax_t = ::std::os::raw::c_long; -pub type uintmax_t = ::std::os::raw::c_ulong; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cache { - #[doc = " Cache size in bytes"] - pub size: u32, - #[doc = " Number of ways of associativity"] - pub associativity: u32, - #[doc = " Number of sets"] - pub sets: u32, - #[doc = " Number of partitions"] - pub partitions: u32, - #[doc = " Line size in bytes"] - pub line_size: u32, - #[doc = " Binary characteristics of the cache (unified cache, inclusive cache,\n cache with complex indexing).\n\n @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE,\n CPUINFO_CACHE_COMPLEX_INDEXING"] - pub flags: u32, - #[doc = " Index of the first logical processor that shares this cache"] - pub processor_start: u32, - #[doc = " Number of logical processors that share this cache"] - pub processor_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_trace_cache { - pub uops: u32, - pub associativity: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_tlb { - pub entries: u32, - pub associativity: u32, - pub pages: u64, -} -#[doc = " Processor vendor is not known to the library, or the library failed\nto get vendor information from the OS."] -pub const cpuinfo_vendor_cpuinfo_vendor_unknown: cpuinfo_vendor = 0; -#[doc = " Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor\n microarchitectures.\n\n Sold its ARM design subsidiary in 2006. The last ARM processor design\n was released in 2004."] -pub const cpuinfo_vendor_cpuinfo_vendor_intel: cpuinfo_vendor = 1; -#[doc = " Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_amd: cpuinfo_vendor = 2; -#[doc = " ARM Holdings plc. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_arm: cpuinfo_vendor = 3; -#[doc = " Qualcomm Incorporated. Vendor of ARM and ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_qualcomm: cpuinfo_vendor = 4; -#[doc = " Apple Inc. Vendor of ARM and ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apple: cpuinfo_vendor = 5; -#[doc = " Samsung Electronics Co., Ltd. Vendir if ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_samsung: cpuinfo_vendor = 6; -#[doc = " Nvidia Corporation. Vendor of ARM64-compatible processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_nvidia: cpuinfo_vendor = 7; -#[doc = " MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_mips: cpuinfo_vendor = 8; -#[doc = " International Business Machines Corporation. Vendor of PowerPC\nprocessor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ibm: cpuinfo_vendor = 9; -#[doc = " Ingenic Semiconductor. Vendor of MIPS processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_ingenic: cpuinfo_vendor = 10; -#[doc = " VIA Technologies, Inc. Vendor of x86 and x86-64 processor\n microarchitectures.\n\n Processors are designed by Centaur Technology, a subsidiary of VIA\n Technologies."] -pub const cpuinfo_vendor_cpuinfo_vendor_via: cpuinfo_vendor = 11; -#[doc = " Cavium, Inc. Vendor of ARM64 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_cavium: cpuinfo_vendor = 12; -#[doc = " Broadcom, Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_broadcom: cpuinfo_vendor = 13; -#[doc = " Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_apm: cpuinfo_vendor = 14; -#[doc = " Huawei Technologies Co., Ltd. Vendor of ARM64 processor\n microarchitectures.\n\n Processors are designed by HiSilicon, a subsidiary of Huawei."] -pub const cpuinfo_vendor_cpuinfo_vendor_huawei: cpuinfo_vendor = 15; -#[doc = " Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor\n of x86-64 processor microarchitectures.\n\n Processors are variants of AMD cores."] -pub const cpuinfo_vendor_cpuinfo_vendor_hygon: cpuinfo_vendor = 16; -#[doc = " SiFive, Inc. Vendor of RISC-V processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_sifive: cpuinfo_vendor = 17; -#[doc = " Texas Instruments Inc. Vendor of ARM processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_texas_instruments: cpuinfo_vendor = 30; -#[doc = " Marvell Technology Group Ltd. Vendor of ARM processor\n microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_marvell: cpuinfo_vendor = 31; -#[doc = " RDC Semiconductor Co., Ltd. Vendor of x86 processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_rdc: cpuinfo_vendor = 32; -#[doc = " DM&P Electronics Inc. Vendor of x86 processor microarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_dmp: cpuinfo_vendor = 33; -#[doc = " Motorola, Inc. Vendor of PowerPC and ARM processor\nmicroarchitectures."] -pub const cpuinfo_vendor_cpuinfo_vendor_motorola: cpuinfo_vendor = 34; -#[doc = " Transmeta Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 2004.\n Transmeta processors implemented VLIW ISA and used binary translation\n to execute x86 code."] -pub const cpuinfo_vendor_cpuinfo_vendor_transmeta: cpuinfo_vendor = 50; -#[doc = " Cyrix Corporation. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1996."] -pub const cpuinfo_vendor_cpuinfo_vendor_cyrix: cpuinfo_vendor = 51; -#[doc = " Rise Technology. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1999."] -pub const cpuinfo_vendor_cpuinfo_vendor_rise: cpuinfo_vendor = 52; -#[doc = " National Semiconductor. Vendor of x86 processor microarchitectures.\n\n Sold its x86 design subsidiary in 1999. The last processor design was\n released in 1998."] -pub const cpuinfo_vendor_cpuinfo_vendor_nsc: cpuinfo_vendor = 53; -#[doc = " Silicon Integrated Systems. Vendor of x86 processor\n microarchitectures.\n\n Sold its x86 design subsidiary in 2001. The last processor design was\n released in 2001."] -pub const cpuinfo_vendor_cpuinfo_vendor_sis: cpuinfo_vendor = 54; -#[doc = " NexGen. Vendor of x86 processor microarchitectures.\n\n Now defunct. The last processor design was released in 1994.\n NexGen designed the first x86 microarchitecture which decomposed x86\n instructions into simple microoperations."] -pub const cpuinfo_vendor_cpuinfo_vendor_nexgen: cpuinfo_vendor = 55; -#[doc = " United Microelectronics Corporation. Vendor of x86 processor\n microarchitectures.\n\n Ceased x86 in the early 1990s. The last processor design was released\n in 1991. Designed U5C and U5D processors. Both are 486 level."] -pub const cpuinfo_vendor_cpuinfo_vendor_umc: cpuinfo_vendor = 56; -#[doc = " Digital Equipment Corporation. Vendor of ARM processor\n microarchitecture.\n\n Sold its ARM designs in 1997. The last processor design was released\n in 1997."] -pub const cpuinfo_vendor_cpuinfo_vendor_dec: cpuinfo_vendor = 57; -#[doc = " Vendor of processor core design"] -pub type cpuinfo_vendor = ::std::os::raw::c_uint; -#[doc = " Microarchitecture is unknown, or the library failed to get\ninformation about the microarchitecture from OS"] -pub const cpuinfo_uarch_cpuinfo_uarch_unknown: cpuinfo_uarch = 0; -#[doc = " Pentium and Pentium MMX microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_p5: cpuinfo_uarch = 1048832; -#[doc = " Intel Quark microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_quark: cpuinfo_uarch = 1048833; -#[doc = " Pentium Pro, Pentium II, and Pentium III."] -pub const cpuinfo_uarch_cpuinfo_uarch_p6: cpuinfo_uarch = 1049088; -#[doc = " Pentium M."] -pub const cpuinfo_uarch_cpuinfo_uarch_dothan: cpuinfo_uarch = 1049089; -#[doc = " Intel Core microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_yonah: cpuinfo_uarch = 1049090; -#[doc = " Intel Core 2 microarchitecture on 65 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_conroe: cpuinfo_uarch = 1049091; -#[doc = " Intel Core 2 microarchitecture on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_penryn: cpuinfo_uarch = 1049092; -#[doc = " Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st\ngen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_nehalem: cpuinfo_uarch = 1049093; -#[doc = " Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sandy_bridge: cpuinfo_uarch = 1049094; -#[doc = " Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_ivy_bridge: cpuinfo_uarch = 1049095; -#[doc = " Intel Haswell microarchitecture (Core i3/i5/i7 4th gen)."] -pub const cpuinfo_uarch_cpuinfo_uarch_haswell: cpuinfo_uarch = 1049096; -#[doc = " Intel Broadwell microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_broadwell: cpuinfo_uarch = 1049097; -#[doc = " Intel Sky Lake microarchitecture (14 nm, including\nKaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sky_lake: cpuinfo_uarch = 1049098; -#[doc = " DEPRECATED (Intel Kaby Lake microarchitecture)."] -pub const cpuinfo_uarch_cpuinfo_uarch_kaby_lake: cpuinfo_uarch = 1049098; -#[doc = " Intel Palm Cove microarchitecture (10 nm, Cannon Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_palm_cove: cpuinfo_uarch = 1049099; -#[doc = " Intel Sunny Cove microarchitecture (10 nm, Ice Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_sunny_cove: cpuinfo_uarch = 1049100; -#[doc = " Pentium 4 with Willamette, Northwood, or Foster cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_willamette: cpuinfo_uarch = 1049344; -#[doc = " Pentium 4 with Prescott and later cores."] -pub const cpuinfo_uarch_cpuinfo_uarch_prescott: cpuinfo_uarch = 1049345; -#[doc = " Intel Atom on 45 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_bonnell: cpuinfo_uarch = 1049600; -#[doc = " Intel Atom on 32 nm process."] -pub const cpuinfo_uarch_cpuinfo_uarch_saltwell: cpuinfo_uarch = 1049601; -#[doc = " Intel Silvermont microarchitecture (22 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_silvermont: cpuinfo_uarch = 1049602; -#[doc = " Intel Airmont microarchitecture (14 nm out-of-order Atom)."] -pub const cpuinfo_uarch_cpuinfo_uarch_airmont: cpuinfo_uarch = 1049603; -#[doc = " Intel Goldmont microarchitecture (Denverton, Apollo Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont: cpuinfo_uarch = 1049604; -#[doc = " Intel Goldmont Plus microarchitecture (Gemini Lake)."] -pub const cpuinfo_uarch_cpuinfo_uarch_goldmont_plus: cpuinfo_uarch = 1049605; -#[doc = " Intel Knights Ferry HPC boards."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_ferry: cpuinfo_uarch = 1049856; -#[doc = " Intel Knights Corner HPC boards (aka Xeon Phi)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_corner: cpuinfo_uarch = 1049857; -#[doc = " Intel Knights Landing microarchitecture (second-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_landing: cpuinfo_uarch = 1049858; -#[doc = " Intel Knights Hill microarchitecture (third-gen MIC)."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_hill: cpuinfo_uarch = 1049859; -#[doc = " Intel Knights Mill Xeon Phi."] -pub const cpuinfo_uarch_cpuinfo_uarch_knights_mill: cpuinfo_uarch = 1049860; -#[doc = " Intel/Marvell XScale series."] -pub const cpuinfo_uarch_cpuinfo_uarch_xscale: cpuinfo_uarch = 1050112; -#[doc = " AMD K5."] -pub const cpuinfo_uarch_cpuinfo_uarch_k5: cpuinfo_uarch = 2097408; -#[doc = " AMD K6 and alike."] -pub const cpuinfo_uarch_cpuinfo_uarch_k6: cpuinfo_uarch = 2097409; -#[doc = " AMD Athlon and Duron."] -pub const cpuinfo_uarch_cpuinfo_uarch_k7: cpuinfo_uarch = 2097410; -#[doc = " AMD Athlon 64, Opteron 64."] -pub const cpuinfo_uarch_cpuinfo_uarch_k8: cpuinfo_uarch = 2097411; -#[doc = " AMD Family 10h (Barcelona, Istambul, Magny-Cours)."] -pub const cpuinfo_uarch_cpuinfo_uarch_k10: cpuinfo_uarch = 2097412; -#[doc = " AMD Bulldozer microarchitecture\n Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_bulldozer: cpuinfo_uarch = 2097413; -#[doc = " AMD Piledriver microarchitecture\n Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu\n Dhabi Opteron CPUs."] -pub const cpuinfo_uarch_cpuinfo_uarch_piledriver: cpuinfo_uarch = 2097414; -#[doc = " AMD Steamroller microarchitecture (Kaveri APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_steamroller: cpuinfo_uarch = 2097415; -#[doc = " AMD Excavator microarchitecture (Carizzo APUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_excavator: cpuinfo_uarch = 2097416; -#[doc = " AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen: cpuinfo_uarch = 2097417; -#[doc = " AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs)."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen2: cpuinfo_uarch = 2097418; -#[doc = " AMD Zen 3 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen3: cpuinfo_uarch = 2097419; -#[doc = " AMD Zen 4 microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_zen4: cpuinfo_uarch = 2097420; -#[doc = " NSC Geode and AMD Geode GX and LX."] -pub const cpuinfo_uarch_cpuinfo_uarch_geode: cpuinfo_uarch = 2097664; -#[doc = " AMD Bobcat mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_bobcat: cpuinfo_uarch = 2097665; -#[doc = " AMD Jaguar mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_jaguar: cpuinfo_uarch = 2097666; -#[doc = " AMD Puma mobile microarchitecture."] -pub const cpuinfo_uarch_cpuinfo_uarch_puma: cpuinfo_uarch = 2097667; -#[doc = " ARM7 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm7: cpuinfo_uarch = 3145984; -#[doc = " ARM9 series."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm9: cpuinfo_uarch = 3145985; -#[doc = " ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore."] -pub const cpuinfo_uarch_cpuinfo_uarch_arm11: cpuinfo_uarch = 3145986; -#[doc = " ARM Cortex-A5."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a5: cpuinfo_uarch = 3146245; -#[doc = " ARM Cortex-A7."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a7: cpuinfo_uarch = 3146247; -#[doc = " ARM Cortex-A8."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a8: cpuinfo_uarch = 3146248; -#[doc = " ARM Cortex-A9."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a9: cpuinfo_uarch = 3146249; -#[doc = " ARM Cortex-A12."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a12: cpuinfo_uarch = 3146258; -#[doc = " ARM Cortex-A15."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a15: cpuinfo_uarch = 3146261; -#[doc = " ARM Cortex-A17."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a17: cpuinfo_uarch = 3146263; -#[doc = " ARM Cortex-A32."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a32: cpuinfo_uarch = 3146546; -#[doc = " ARM Cortex-A35."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a35: cpuinfo_uarch = 3146549; -#[doc = " ARM Cortex-A53."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a53: cpuinfo_uarch = 3146579; -#[doc = " ARM Cortex-A55 revision 0 (restricted dual-issue capabilities\ncompared to revision 1+)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55r0: cpuinfo_uarch = 3146580; -#[doc = " ARM Cortex-A55."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a55: cpuinfo_uarch = 3146581; -#[doc = " ARM Cortex-A57."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a57: cpuinfo_uarch = 3146583; -#[doc = " ARM Cortex-A65."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a65: cpuinfo_uarch = 3146597; -#[doc = " ARM Cortex-A72."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a72: cpuinfo_uarch = 3146610; -#[doc = " ARM Cortex-A73."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a73: cpuinfo_uarch = 3146611; -#[doc = " ARM Cortex-A75."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a75: cpuinfo_uarch = 3146613; -#[doc = " ARM Cortex-A76."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76: cpuinfo_uarch = 3146614; -#[doc = " ARM Cortex-A77."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a77: cpuinfo_uarch = 3146615; -#[doc = " ARM Cortex-A78."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a78: cpuinfo_uarch = 3146616; -#[doc = " ARM Neoverse N1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n1: cpuinfo_uarch = 3146752; -#[doc = " ARM Neoverse E1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_e1: cpuinfo_uarch = 3146753; -#[doc = " ARM Neoverse V1."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v1: cpuinfo_uarch = 3146754; -#[doc = " ARM Neoverse N2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_n2: cpuinfo_uarch = 3146755; -#[doc = " ARM Neoverse V2."] -pub const cpuinfo_uarch_cpuinfo_uarch_neoverse_v2: cpuinfo_uarch = 3146756; -#[doc = " ARM Cortex-X1."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x1: cpuinfo_uarch = 3147009; -#[doc = " ARM Cortex-X2."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x2: cpuinfo_uarch = 3147010; -#[doc = " ARM Cortex-X3."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_x3: cpuinfo_uarch = 3147011; -#[doc = " ARM Cortex-A510."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a510: cpuinfo_uarch = 3147089; -#[doc = " ARM Cortex-A710."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a710: cpuinfo_uarch = 3147121; -#[doc = " ARM Cortex-A715."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a715: cpuinfo_uarch = 3147122; -#[doc = " Qualcomm Scorpion."] -pub const cpuinfo_uarch_cpuinfo_uarch_scorpion: cpuinfo_uarch = 4194560; -#[doc = " Qualcomm Krait."] -pub const cpuinfo_uarch_cpuinfo_uarch_krait: cpuinfo_uarch = 4194561; -#[doc = " Qualcomm Kryo."] -pub const cpuinfo_uarch_cpuinfo_uarch_kryo: cpuinfo_uarch = 4194562; -#[doc = " Qualcomm Falkor."] -pub const cpuinfo_uarch_cpuinfo_uarch_falkor: cpuinfo_uarch = 4194563; -#[doc = " Qualcomm Saphira."] -pub const cpuinfo_uarch_cpuinfo_uarch_saphira: cpuinfo_uarch = 4194564; -#[doc = " Nvidia Denver."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver: cpuinfo_uarch = 5243136; -#[doc = " Nvidia Denver 2."] -pub const cpuinfo_uarch_cpuinfo_uarch_denver2: cpuinfo_uarch = 5243137; -#[doc = " Nvidia Carmel."] -pub const cpuinfo_uarch_cpuinfo_uarch_carmel: cpuinfo_uarch = 5243138; -#[doc = " Samsung Exynos M1 (Exynos 8890 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M2 (Exynos 8895 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M3 (Exynos 9810 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M4 (Exynos 9820 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m4: cpuinfo_uarch = 6291715; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_exynos_m5: cpuinfo_uarch = 6291716; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_cortex_a76ae: cpuinfo_uarch = 3146614; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m1: cpuinfo_uarch = 6291712; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mongoose_m2: cpuinfo_uarch = 6291713; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m3: cpuinfo_uarch = 6291714; -#[doc = " Samsung Exynos M5 (Exynos 9830 big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_meerkat_m4: cpuinfo_uarch = 6291715; -#[doc = " Apple A6 and A6X processors."] -pub const cpuinfo_uarch_cpuinfo_uarch_swift: cpuinfo_uarch = 7340288; -#[doc = " Apple A7 processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_cyclone: cpuinfo_uarch = 7340289; -#[doc = " Apple A8 and A8X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_typhoon: cpuinfo_uarch = 7340290; -#[doc = " Apple A9 and A9X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_twister: cpuinfo_uarch = 7340291; -#[doc = " Apple A10 and A10X processor."] -pub const cpuinfo_uarch_cpuinfo_uarch_hurricane: cpuinfo_uarch = 7340292; -#[doc = " Apple A11 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_monsoon: cpuinfo_uarch = 7340293; -#[doc = " Apple A11 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_mistral: cpuinfo_uarch = 7340294; -#[doc = " Apple A12 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_vortex: cpuinfo_uarch = 7340295; -#[doc = " Apple A12 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_tempest: cpuinfo_uarch = 7340296; -#[doc = " Apple A13 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_lightning: cpuinfo_uarch = 7340297; -#[doc = " Apple A13 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunder: cpuinfo_uarch = 7340298; -#[doc = " Apple A14 / M1 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_firestorm: cpuinfo_uarch = 7340299; -#[doc = " Apple A14 / M1 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_icestorm: cpuinfo_uarch = 7340300; -#[doc = " Apple A15 / M2 processor (big cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_avalanche: cpuinfo_uarch = 7340301; -#[doc = " Apple A15 / M2 processor (little cores)."] -pub const cpuinfo_uarch_cpuinfo_uarch_blizzard: cpuinfo_uarch = 7340302; -#[doc = " Cavium ThunderX."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx: cpuinfo_uarch = 8388864; -#[doc = " Cavium ThunderX2 (originally Broadcom Vulkan)."] -pub const cpuinfo_uarch_cpuinfo_uarch_thunderx2: cpuinfo_uarch = 8389120; -#[doc = " Marvell PJ4."] -pub const cpuinfo_uarch_cpuinfo_uarch_pj4: cpuinfo_uarch = 9437440; -#[doc = " Broadcom Brahma B15."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b15: cpuinfo_uarch = 10486016; -#[doc = " Broadcom Brahma B53."] -pub const cpuinfo_uarch_cpuinfo_uarch_brahma_b53: cpuinfo_uarch = 10486017; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_xgene: cpuinfo_uarch = 11534592; -#[doc = " Applied Micro X-Gene."] -pub const cpuinfo_uarch_cpuinfo_uarch_dhyana: cpuinfo_uarch = 16777472; -#[doc = " HiSilicon TaiShan v110 (Huawei Kunpeng 920 series processors)."] -pub const cpuinfo_uarch_cpuinfo_uarch_taishan_v110: cpuinfo_uarch = 12583168; -#[doc = " Processor microarchitecture\n\n Processors with different microarchitectures often have different instruction\n performance characteristics, and may have dramatically different pipeline\n organization."] -pub type cpuinfo_uarch = ::std::os::raw::c_uint; -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor { - #[doc = " SMT (hyperthread) ID within a core"] - pub smt_id: u32, - #[doc = " Core containing this logical processor"] - pub core: *const cpuinfo_core, - #[doc = " Cluster of cores containing this logical processor"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this logical processor"] - pub package: *const cpuinfo_package, - #[doc = " Linux-specific ID for the logical processor:\n - Linux kernel exposes information about this logical processor in\n /sys/devices/system/cpu/cpu/\n - Bit in the cpu_set_t identifies this logical processor"] - pub linux_id: ::std::os::raw::c_int, - #[doc = " APIC ID (unique x86-specific ID of the logical processor)"] - pub apic_id: u32, - pub cache: cpuinfo_processor__bindgen_ty_1, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_processor__bindgen_ty_1 { - #[doc = " Level 1 instruction cache"] - pub l1i: *const cpuinfo_cache, - #[doc = " Level 1 data cache"] - pub l1d: *const cpuinfo_cache, - #[doc = " Level 2 unified or data cache"] - pub l2: *const cpuinfo_cache, - #[doc = " Level 3 unified or data cache"] - pub l3: *const cpuinfo_cache, - #[doc = " Level 4 unified or data cache"] - pub l4: *const cpuinfo_cache, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_core { - #[doc = " Index of the first logical processor on this core."] - pub processor_start: u32, - #[doc = " Number of logical processors on this core"] - pub processor_count: u32, - #[doc = " Core ID within a package"] - pub core_id: u32, - #[doc = " Cluster containing this core"] - pub cluster: *const cpuinfo_cluster, - #[doc = " Physical package containing this core."] - pub package: *const cpuinfo_package, - #[doc = " Vendor of the CPU microarchitecture for this core"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture for this core"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register for this core"] - pub cpuid: u32, - #[doc = " Clock rate (non-Turbo) of the core, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_cluster { - #[doc = " Index of the first logical processor in the cluster"] - pub processor_start: u32, - #[doc = " Number of logical processors in the cluster"] - pub processor_count: u32, - #[doc = " Index of the first core in the cluster"] - pub core_start: u32, - #[doc = " Number of cores on the cluster"] - pub core_count: u32, - #[doc = " Cluster ID within a package"] - pub cluster_id: u32, - #[doc = " Physical package containing the cluster"] - pub package: *const cpuinfo_package, - #[doc = " CPU microarchitecture vendor of the cores in the cluster"] - pub vendor: cpuinfo_vendor, - #[doc = " CPU microarchitecture of the cores in the cluster"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register of the cores in the cluster"] - pub cpuid: u32, - #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] - pub frequency: u64, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_package { - #[doc = " SoC or processor chip model name"] - pub name: [::std::os::raw::c_char; 48usize], - #[doc = " Index of the first logical processor on this physical package"] - pub processor_start: u32, - #[doc = " Number of logical processors on this physical package"] - pub processor_count: u32, - #[doc = " Index of the first core on this physical package"] - pub core_start: u32, - #[doc = " Number of cores on this physical package"] - pub core_count: u32, - #[doc = " Index of the first cluster of cores on this physical package"] - pub cluster_start: u32, - #[doc = " Number of clusters of cores on this physical package"] - pub cluster_count: u32, -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_uarch_info { - #[doc = " Type of CPU microarchitecture"] - pub uarch: cpuinfo_uarch, - #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture"] - pub cpuid: u32, - #[doc = " Number of logical processors with the microarchitecture"] - pub processor_count: u32, - #[doc = " Number of cores with the microarchitecture"] - pub core_count: u32, -} -extern "C" { - pub fn cpuinfo_initialize() -> bool; -} -extern "C" { - pub fn cpuinfo_deinitialize(); -} -#[repr(C)] -#[derive(Debug, Copy, Clone)] -pub struct cpuinfo_x86_isa { - pub rdtscp: bool, - pub rdpid: bool, - pub sysenter: bool, - pub msr: bool, - pub clzero: bool, - pub clflush: bool, - pub clflushopt: bool, - pub mwait: bool, - pub mwaitx: bool, - pub fxsave: bool, - pub xsave: bool, - pub three_d_now: bool, - pub three_d_now_plus: bool, - pub prefetch: bool, - pub prefetchw: bool, - pub prefetchwt1: bool, - pub sse3: bool, - pub ssse3: bool, - pub sse4_1: bool, - pub sse4_2: bool, - pub sse4a: bool, - pub misaligned_sse: bool, - pub avx: bool, - pub avxvnni: bool, - pub fma3: bool, - pub fma4: bool, - pub xop: bool, - pub f16c: bool, - pub avx2: bool, - pub avx512f: bool, - pub avx512pf: bool, - pub avx512er: bool, - pub avx512cd: bool, - pub avx512dq: bool, - pub avx512bw: bool, - pub avx512vl: bool, - pub avx512ifma: bool, - pub avx512vbmi: bool, - pub avx512vbmi2: bool, - pub avx512bitalg: bool, - pub avx512vpopcntdq: bool, - pub avx512vnni: bool, - pub avx512bf16: bool, - pub avx512fp16: bool, - pub avx512vp2intersect: bool, - pub avx512_4vnniw: bool, - pub avx512_4fmaps: bool, - pub amx_bf16: bool, - pub amx_tile: bool, - pub amx_int8: bool, - pub amx_fp16: bool, - pub avx_vnni_int8: bool, - pub avx_vnni_int16: bool, - pub avx_ne_convert: bool, - pub hle: bool, - pub rtm: bool, - pub xtest: bool, - pub mpx: bool, - pub cmpxchg16b: bool, - pub clwb: bool, - pub movbe: bool, - pub lahf_sahf: bool, - pub fs_gs_base: bool, - pub lzcnt: bool, - pub popcnt: bool, - pub tbm: bool, - pub bmi: bool, - pub bmi2: bool, - pub adx: bool, - pub aes: bool, - pub vaes: bool, - pub pclmulqdq: bool, - pub vpclmulqdq: bool, - pub gfni: bool, - pub rdrand: bool, - pub rdseed: bool, - pub sha: bool, - pub rng: bool, - pub ace: bool, - pub ace2: bool, - pub phe: bool, - pub pmm: bool, - pub lwp: bool, -} -extern "C" { - pub static mut cpuinfo_isa: cpuinfo_x86_isa; -} -extern "C" { - pub fn cpuinfo_get_processors() -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_cores() -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_clusters() -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_packages() -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarchs() -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_caches() -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processor(index: u32) -> *const cpuinfo_processor; -} -extern "C" { - pub fn cpuinfo_get_core(index: u32) -> *const cpuinfo_core; -} -extern "C" { - pub fn cpuinfo_get_cluster(index: u32) -> *const cpuinfo_cluster; -} -extern "C" { - pub fn cpuinfo_get_package(index: u32) -> *const cpuinfo_package; -} -extern "C" { - pub fn cpuinfo_get_uarch(index: u32) -> *const cpuinfo_uarch_info; -} -extern "C" { - pub fn cpuinfo_get_l1i_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l1d_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l2_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l3_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_l4_cache(index: u32) -> *const cpuinfo_cache; -} -extern "C" { - pub fn cpuinfo_get_processors_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_cores_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_clusters_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_packages_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_uarchs_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1i_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l1d_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l2_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l3_caches_count() -> u32; -} -extern "C" { - pub fn cpuinfo_get_l4_caches_count() -> u32; -} -extern "C" { - #[doc = " Returns upper bound on cache size."] - pub fn cpuinfo_get_max_cache_size() -> u32; -} -extern "C" { - #[doc = " Identify the logical processor that executes the current thread.\n\n There is no guarantee that the thread will stay on the same logical processor\n for any time. Callers should treat the result as only a hint, and be prepared\n to handle NULL return value."] - pub fn cpuinfo_get_current_processor() -> *const cpuinfo_processor; -} -extern "C" { - #[doc = " Identify the core that executes the current thread.\n\n There is no guarantee that the thread will stay on the same core for any\n time. Callers should treat the result as only a hint, and be prepared to\n handle NULL return value."] - pub fn cpuinfo_get_current_core() -> *const cpuinfo_core; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns 0.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index() -> u32; -} -extern "C" { - #[doc = " Identify the microarchitecture index of the core that executes the current\n thread. If the system does not support such identification, the function\n returns the user-specified default value.\n\n There is no guarantee that the thread will stay on the same type of core for\n any time. Callers should treat the result as only a hint."] - pub fn cpuinfo_get_current_uarch_index_with_default(default_uarch_index: u32) -> u32; -} diff --git a/src/lib.rs b/src/lib.rs index 50b8118..8ee2ade 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,44 +1,7 @@ #![doc = include_str!("../README.md")] -#[cfg(all(target_arch = "aarch64", target_os = "android"))] -mod bindings_aarch64_linux_android; -#[cfg(all(target_arch = "aarch64", target_os = "android"))] -use bindings_aarch64_linux_android::*; - -#[cfg(all(target_arch = "aarch64", target_os = "macos"))] -mod bindings_aarch64_apple_darwin; -#[cfg(all(target_arch = "aarch64", target_os = "macos"))] -use bindings_aarch64_apple_darwin::*; - -#[cfg(all(target_arch = "aarch64", target_os = "windows", target_env = "msvc"))] -mod bindings_aarch64_pc_windows_msvc; -#[cfg(all(target_arch = "aarch64", target_os = "windows", target_env = "msvc"))] -use bindings_aarch64_pc_windows_msvc::*; - -#[cfg(all(target_arch = "aarch64", target_os = "linux", target_env = "gnu"))] -mod bindings_aarch64_unknown_linux_gnu; -#[cfg(all(target_arch = "aarch64", target_os = "linux", target_env = "gnu"))] -use bindings_aarch64_unknown_linux_gnu::*; - -#[cfg(all(target_arch = "x86_64", target_os = "windows", target_env = "msvc"))] -mod bindings_x86_64_pc_windows_msvc; -#[cfg(all(target_arch = "x86_64", target_os = "windows", target_env = "msvc"))] -use bindings_x86_64_pc_windows_msvc::*; - -#[cfg(all(target_arch = "x86_64", target_os = "linux", target_env = "gnu"))] -mod bindings_x86_64_unknown_linux_gnu; -#[cfg(all(target_arch = "x86_64", target_os = "linux", target_env = "gnu"))] -use bindings_x86_64_unknown_linux_gnu::*; - -#[cfg(all(target_arch = "x86_64", target_os = "macos"))] -mod bindings_x86_64_apple_darwin; -#[cfg(all(target_arch = "x86_64", target_os = "macos"))] -use bindings_x86_64_apple_darwin::*; - -#[cfg(all(target_arch = "arm", target_os = "linux", target_env = "gnu"))] -mod bindings_armv7_unknown_linux_gnueabihf; -#[cfg(all(target_arch = "arm", target_os = "linux", target_env = "gnu"))] -use bindings_armv7_unknown_linux_gnueabihf::*; +mod bindings; +use bindings::*; use std::borrow::Cow; use std::sync::{Arc, Once}; From 4ce62bc8fd8cbdbcebe87fd15a23112721a89b65 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 15:35:09 +0200 Subject: [PATCH 17/30] fix bindings generation --- build.rs | 11 ++++++----- src/lib.rs | 7 ++++++- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/build.rs b/build.rs index a1fd88c..753b051 100644 --- a/build.rs +++ b/build.rs @@ -146,20 +146,21 @@ fn main() { build.compile("cpuinfo"); - generate_bindings("src/bindings.rs"); + generate_bindings(); } -fn generate_bindings(output_file: &str) { +fn generate_bindings() { + let dest = std::env::var("OUT_DIR").unwrap(); + let dest = std::path::Path::new(&dest).join("bindings.rs"); + let bindings = bindgen::Builder::default() .header("vendor/cpuinfo/include/cpuinfo.h") - .raw_line("#![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)]") - .raw_line("#![allow(dead_code)]") .clang_args(&["-xc++", "-std=c++11"]) .layout_tests(false) .generate() .expect("Unable to generate bindings!"); bindings - .write_to_file(std::path::Path::new(output_file)) + .write_to_file(dest) .expect("Unable to write bindings!"); } diff --git a/src/lib.rs b/src/lib.rs index 8ee2ade..f585c92 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -1,6 +1,11 @@ #![doc = include_str!("../README.md")] -mod bindings; +mod bindings { + #![allow(non_upper_case_globals, non_snake_case, non_camel_case_types)] + #![allow(dead_code)] + + include!(concat!(env!("OUT_DIR"), "/bindings.rs")); +} use bindings::*; use std::borrow::Cow; From dea60a56014a1e02753d307a286f7071389eae3e Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 15:47:27 +0200 Subject: [PATCH 18/30] cleanup --- .gitignore | 4 +-- build.rs | 12 --------- src/lib.rs | 71 ++++++++++++++++++++++++++++++------------------------ 3 files changed, 41 insertions(+), 46 deletions(-) diff --git a/.gitignore b/.gitignore index 9d543b7..acbfeed 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,3 @@ /target /Cargo.lock -/src/bindings.rs -info.txt - +info.txt \ No newline at end of file diff --git a/build.rs b/build.rs index 753b051..913ff33 100644 --- a/build.rs +++ b/build.rs @@ -77,18 +77,6 @@ const MACH_ARM_SRCS: &[&str] = &["src/arm/mach/init.c"]; const FREEBSD_X86_SRCS: &[&str] = &["src/x86/freebsd/init.c"]; -/// Targets for which bindings will be generated. -const BINDGEN_SUPPORTED_TARGETS: &[&str] = &[ - "x86_64-unknown-linux-gnu", - "x86_64-apple-darwin", - "x86_64-pc-windows-msvc", - "aarch64-linux-android", - "aarch64-unknown-linux-gnu", - "aarch64-pc-windows-msvc", - "aarch64-apple-darwin", - "armv7-unknown-linux-gnueabihf", -]; - fn main() { let mut build = cc::Build::new(); diff --git a/src/lib.rs b/src/lib.rs index f585c92..d4055db 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -88,17 +88,17 @@ impl CpuInfo { } fn cluster(cluster: *const cpuinfo_cluster, package: Arc) -> Arc { - Arc::new(unsafe { - #[cfg(target_arch = "x86_64")] - let cpuid = Some((*cluster).cpuid); - #[cfg(not(target_arch = "x86_64"))] - let cpuid = None; + #[cfg(target_arch = "x86_64")] + let cpuid = Some(unsafe { (*cluster).cpuid }); + #[cfg(not(target_arch = "x86_64"))] + let cpuid = None; - #[cfg(target_arch = "aarch64")] - let midr = Some((*cluster).midr); - #[cfg(not(target_arch = "aarch64"))] - let midr = None; + #[cfg(target_arch = "aarch64")] + let midr = Some(unsafe { (*cluster).midr }); + #[cfg(not(target_arch = "aarch64"))] + let midr = None; + Arc::new(unsafe { Cluster { processor_start: (*cluster).processor_start, processor_count: (*cluster).processor_count, @@ -123,11 +123,18 @@ impl CpuInfo { } fn core(core: *const cpuinfo_core, cluster: Arc, package: Arc) -> Arc { + #[cfg(target_arch = "x86_64")] + let cpuid = Some(unsafe { (*core).cpuid }); + #[cfg(not(target_arch = "x86_64"))] + let cpuid = None; + + #[cfg(target_arch = "aarch64")] + let midr = Some(unsafe { (*core).midr }); + #[cfg(not(target_arch = "aarch64"))] + let midr = None; + Arc::new(unsafe { Core { - cpuid: cluster.cpuid, - midr: cluster.midr, - processor_start: (*core).processor_start, processor_count: (*core).processor_count, core_id: (*core).core_id, @@ -135,6 +142,8 @@ impl CpuInfo { package, vendor: Self::vendor((*core).vendor), uarch: Self::uarch((*core).uarch), + cpuid, + midr, frequency: (*core).frequency, } }) @@ -198,27 +207,27 @@ impl CpuInfo { package.clone(), ); - processors.push(unsafe { - #[cfg(target_os = "linux")] - let linux_id = Some((*processor).linux_id); - #[cfg(not(target_os = "linux"))] - let linux_id = None; - - #[cfg(target_os = "windows")] - let (windows_group_id, windows_processor_id) = { - ( - Some((*processor).windows_group_id), - Some((*processor).windows_processor_id), - ) - }; - #[cfg(not(target_os = "windows"))] - let (windows_group_id, windows_processor_id) = (None, None); + #[cfg(target_os = "linux")] + let linux_id = Some(unsafe { (*processor).linux_id }); + #[cfg(not(target_os = "linux"))] + let linux_id = None; + + #[cfg(target_os = "windows")] + let (windows_group_id, windows_processor_id) = { + ( + Some(unsafe { (*processor).windows_group_id }), + Some(unsafe { (*processor).windows_processor_id }), + ) + }; + #[cfg(not(target_os = "windows"))] + let (windows_group_id, windows_processor_id) = (None, None); - #[cfg(target_arch = "x86_64")] - let apic_id = Some((*processor).apic_id); - #[cfg(not(target_arch = "x86_64"))] - let apic_id = None; + #[cfg(target_arch = "x86_64")] + let apic_id = Some(unsafe { (*processor).apic_id }); + #[cfg(not(target_arch = "x86_64"))] + let apic_id = None; + processors.push(unsafe { Processor { smt_id: (*processor).smt_id, core, From ba6c7c7c6d71c4d73a764f860bd1797a4e8420d4 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 15:51:40 +0200 Subject: [PATCH 19/30] on push only --- .github/workflows/ci.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 248ce84..4d77add 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -2,7 +2,6 @@ name: CI on: push: - pull_request: jobs: rust: From 803705eac17b6bbce91a772ad9d7f12941d6bc36 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 16:43:30 +0200 Subject: [PATCH 20/30] remove armv7 test --- .github/workflows/ci.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 486b8bb..cd8bf49 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -79,11 +79,11 @@ jobs: # test: true # cargo_args: --features "openwrt" - - target: armv7-unknown-linux-gnueabihf - os: ubuntu-latest - name: Linux ARMv7 - cross: true - test: true + # - target: armv7-unknown-linux-gnueabihf + # os: ubuntu-latest + # name: Linux ARMv7 + # cross: true + # test: true steps: - name: Checkout From 7cfdd7c761cd721bdb4a3227c5a5be5420c2db86 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 16:59:45 +0200 Subject: [PATCH 21/30] update bindgen and force rust target --- Cargo.lock | 88 +++--------------------------------------------------- Cargo.toml | 2 +- build.rs | 5 ++++ 3 files changed, 10 insertions(+), 85 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index aeeb832..582bffb 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -13,16 +13,14 @@ dependencies = [ [[package]] name = "bindgen" -version = "0.69.4" +version = "0.71.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "a00dc851838a2120612785d195287475a3ac45514741da670b735818822129a0" +checksum = "5f58bf3d7db68cfbac37cfc485a8d711e87e064c3d0fe0435b92f7a407f9d6b3" dependencies = [ "bitflags", "cexpr", "clang-sys", "itertools", - "lazy_static", - "lazycell", "log", "prettyplease", "proc-macro2", @@ -31,7 +29,6 @@ dependencies = [ "rustc-hash", "shlex", "syn", - "which", ] [[package]] @@ -95,31 +92,12 @@ version = "1.13.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "60b1af1c220855b6ceac025d3f6ecdd2b7c4894bfe9cd9bda4fbb4bc7c0d4cf0" -[[package]] -name = "errno" -version = "0.3.9" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "534c5cf6194dfab3db3242765c03bbe257cf92f22b38f6bc0c58d59108a820ba" -dependencies = [ - "libc", - "windows-sys", -] - [[package]] name = "glob" version = "0.3.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "d2fabcfbdc87f4758337ca535fb41a6d701b65693ce38287d856d1674551ec9b" -[[package]] -name = "home" -version = "0.5.9" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "e3d1354bf6b7235cb4a0576c2619fd4ed18183f689b12b006a0ee7329eeff9a5" -dependencies = [ - "windows-sys", -] - [[package]] name = "itertools" version = "0.12.1" @@ -135,18 +113,6 @@ version = "1.0.11" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "49f1f14873335454500d59611f1cf4a4b0f786f9ac11f4312a78e4cf2566695b" -[[package]] -name = "lazy_static" -version = "1.5.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "bbd2bcb4c963f2ddae06a2efc7e9f3591312473c50c6685e1f298068316e66fe" - -[[package]] -name = "lazycell" -version = "1.3.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "830d08ce1d1d941e6b30645f1a0eb5643013d835ce3779a5fc208261dbe10f55" - [[package]] name = "libc" version = "0.2.155" @@ -163,12 +129,6 @@ dependencies = [ "windows-targets", ] -[[package]] -name = "linux-raw-sys" -version = "0.4.14" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "78b3ae25bc7c8c38cec158d1f2757ee79e9b3740fbc7ccf0e59e4b08d793fa89" - [[package]] name = "log" version = "0.4.22" @@ -197,12 +157,6 @@ dependencies = [ "minimal-lexical", ] -[[package]] -name = "once_cell" -version = "1.19.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "3fdb12b2476b595f9358c5161aa467c2438859caa136dec86c26fdd2efe17b92" - [[package]] name = "prettyplease" version = "0.2.20" @@ -262,22 +216,9 @@ checksum = "7a66a03ae7c801facd77a29370b4faec201768915ac14a721ba36f20bc9c209b" [[package]] name = "rustc-hash" -version = "1.1.0" +version = "2.1.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "08d43f7aa6b08d49f382cde6a7982047c3426db949b1424bc4b7ec9ae12c6ce2" - -[[package]] -name = "rustix" -version = "0.38.34" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "70dc5ec042f7a43c4a73241207cecc9873a06d45debb38b329f8541d85c2730f" -dependencies = [ - "bitflags", - "errno", - "libc", - "linux-raw-sys", - "windows-sys", -] +checksum = "357703d41365b4b27c590e3ed91eabb1b663f07c4c084095e60cbed4362dff0d" [[package]] name = "ryu" @@ -339,27 +280,6 @@ version = "1.0.12" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b" -[[package]] -name = "which" -version = "4.4.2" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "87ba24419a2078cd2b0f2ede2691b6c66d8e47836da3b6db8265ebad47afbfc7" -dependencies = [ - "either", - "home", - "once_cell", - "rustix", -] - -[[package]] -name = "windows-sys" -version = "0.52.0" -source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "282be5f36a8ce781fad8c8ae18fa3f9beff57ec1b52cb3de0789201425d9a33d" -dependencies = [ - "windows-targets", -] - [[package]] name = "windows-targets" version = "0.52.6" diff --git a/Cargo.toml b/Cargo.toml index 829d095..6a52b42 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -20,5 +20,5 @@ serde = { version = "1", features = ["derive", "rc"] } serde_json = "1" [build-dependencies] -bindgen = { version = "0.69" } +bindgen = { version = "0.71" } cc = "1.1" diff --git a/build.rs b/build.rs index 913ff33..798e5e5 100644 --- a/build.rs +++ b/build.rs @@ -141,10 +141,15 @@ fn generate_bindings() { let dest = std::env::var("OUT_DIR").unwrap(); let dest = std::path::Path::new(&dest).join("bindings.rs"); + let Ok(version) = bindgen::RustTarget::stable(74, 0) else { + panic!("Invalid rust target version"); + }; + let bindings = bindgen::Builder::default() .header("vendor/cpuinfo/include/cpuinfo.h") .clang_args(&["-xc++", "-std=c++11"]) .layout_tests(false) + .rust_target(version) .generate() .expect("Unable to generate bindings!"); From 7f93635cfdd650d6b38ba22bab36ee29c7cb248f Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 17:01:29 +0200 Subject: [PATCH 22/30] remove rust target --- build.rs | 5 ----- 1 file changed, 5 deletions(-) diff --git a/build.rs b/build.rs index 798e5e5..913ff33 100644 --- a/build.rs +++ b/build.rs @@ -141,15 +141,10 @@ fn generate_bindings() { let dest = std::env::var("OUT_DIR").unwrap(); let dest = std::path::Path::new(&dest).join("bindings.rs"); - let Ok(version) = bindgen::RustTarget::stable(74, 0) else { - panic!("Invalid rust target version"); - }; - let bindings = bindgen::Builder::default() .header("vendor/cpuinfo/include/cpuinfo.h") .clang_args(&["-xc++", "-std=c++11"]) .layout_tests(false) - .rust_target(version) .generate() .expect("Unable to generate bindings!"); From 5504041737de3cdf8a51aee7b4e3ea37b18c4d02 Mon Sep 17 00:00:00 2001 From: Max de Danschutter <43446207+maxded@users.noreply.github.com> Date: Thu, 24 Apr 2025 17:03:12 +0200 Subject: [PATCH 23/30] Update src/lib.rs Co-authored-by: Marijn Suijten --- src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib.rs b/src/lib.rs index d4055db..bea1881 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -390,7 +390,7 @@ pub struct Uarch { pub struct UarchInfo { #[doc = " Type of CPU microarchitecture"] pub uarch: Uarch, - #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture"] + #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture (x86-specific ID)"] pub cpuid: Option, #[doc = " Value of Main ID Register (MIDR) for this core (arm-specific ID)"] pub midr: Option, From c6409504ac17a2d78a60075e64bc85a33545a132 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 17:05:26 +0200 Subject: [PATCH 24/30] remvoe info.text --- .gitignore | 2 +- info.txt | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) delete mode 100644 info.txt diff --git a/.gitignore b/.gitignore index acbfeed..c664348 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,3 @@ /target /Cargo.lock -info.txt \ No newline at end of file +/info.txt \ No newline at end of file diff --git a/info.txt b/info.txt deleted file mode 100644 index 66e966a..0000000 --- a/info.txt +++ /dev/null @@ -1 +0,0 @@ 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\ No newline at end of file From 524acd1c6d7ea1be087544f09a23aae83777e421 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 17:09:01 +0200 Subject: [PATCH 25/30] update docs --- src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib.rs b/src/lib.rs index bea1881..4b9d11f 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -327,7 +327,7 @@ pub struct Core { pub uarch: Uarch, #[doc = " Value of CPUID leaf 1 EAX register for this core (x86-specific ID)"] pub cpuid: Option, - #[doc = " Value of Main ID Register (MIDR) for this core (arm-specific ID)"] + #[doc = " Value of Main ID Register (MIDR) for this core (arm/aarch64-specific ID)"] pub midr: Option, #[doc = " Clock rate (non-Turbo) of the core, in Hz"] pub frequency: u64, From 813c9a81a7478229c8e7e2a6439ad60edfc26250 Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 18:22:09 +0200 Subject: [PATCH 26/30] include 32bit targets --- src/lib.rs | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/lib.rs b/src/lib.rs index 4b9d11f..3199eb4 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -44,14 +44,14 @@ impl CpuInfo { for i in 0..count { let uarch_info = unsafe { cpuinfo_get_uarch(i) }; infos.push(unsafe { - #[cfg(target_arch = "x86_64")] + #[cfg(any(target_arch = "x86_64", target_arch = "x86"))] let cpuid = Some((*uarch_info).cpuid); - #[cfg(not(target_arch = "x86_64"))] + #[cfg(all(not(target_arch = "x86_64"), not(target_arch = "x86")))] let cpuid = None; - #[cfg(target_arch = "aarch64")] + #[cfg(any(target_arch = "aarch64", target_arch = "arm"))] let midr = Some((*uarch_info).midr); - #[cfg(not(target_arch = "aarch64"))] + #[cfg(all(not(target_arch = "aarch64"), not(target_arch = "arm")))] let midr = None; UarchInfo { @@ -88,14 +88,14 @@ impl CpuInfo { } fn cluster(cluster: *const cpuinfo_cluster, package: Arc) -> Arc { - #[cfg(target_arch = "x86_64")] + #[cfg(any(target_arch = "x86_64", target_arch = "x86"))] let cpuid = Some(unsafe { (*cluster).cpuid }); - #[cfg(not(target_arch = "x86_64"))] + #[cfg(all(not(target_arch = "x86_64"), not(target_arch = "x86")))] let cpuid = None; - #[cfg(target_arch = "aarch64")] + #[cfg(any(target_arch = "aarch64", target_arch = "arm"))] let midr = Some(unsafe { (*cluster).midr }); - #[cfg(not(target_arch = "aarch64"))] + #[cfg(all(not(target_arch = "aarch64"), not(target_arch = "arm")))] let midr = None; Arc::new(unsafe { @@ -123,14 +123,14 @@ impl CpuInfo { } fn core(core: *const cpuinfo_core, cluster: Arc, package: Arc) -> Arc { - #[cfg(target_arch = "x86_64")] + #[cfg(any(target_arch = "x86_64", target_arch = "x86"))] let cpuid = Some(unsafe { (*core).cpuid }); - #[cfg(not(target_arch = "x86_64"))] + #[cfg(all(not(target_arch = "x86_64"), not(target_arch = "x86")))] let cpuid = None; - #[cfg(target_arch = "aarch64")] + #[cfg(any(target_arch = "aarch64", target_arch = "arm"))] let midr = Some(unsafe { (*core).midr }); - #[cfg(not(target_arch = "aarch64"))] + #[cfg(all(not(target_arch = "aarch64"), not(target_arch = "arm")))] let midr = None; Arc::new(unsafe { @@ -222,9 +222,9 @@ impl CpuInfo { #[cfg(not(target_os = "windows"))] let (windows_group_id, windows_processor_id) = (None, None); - #[cfg(target_arch = "x86_64")] + #[cfg(any(target_arch = "x86_64", target_arch = "x86"))] let apic_id = Some(unsafe { (*processor).apic_id }); - #[cfg(not(target_arch = "x86_64"))] + #[cfg(all(not(target_arch = "x86_64"), not(target_arch = "x86")))] let apic_id = None; processors.push(unsafe { From ebabab495b5cf8d161813d661f19662068816bcf Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 19:39:40 +0200 Subject: [PATCH 27/30] add rust target to bindgen --- build.rs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/build.rs b/build.rs index 913ff33..798e5e5 100644 --- a/build.rs +++ b/build.rs @@ -141,10 +141,15 @@ fn generate_bindings() { let dest = std::env::var("OUT_DIR").unwrap(); let dest = std::path::Path::new(&dest).join("bindings.rs"); + let Ok(version) = bindgen::RustTarget::stable(74, 0) else { + panic!("Invalid rust target version"); + }; + let bindings = bindgen::Builder::default() .header("vendor/cpuinfo/include/cpuinfo.h") .clang_args(&["-xc++", "-std=c++11"]) .layout_tests(false) + .rust_target(version) .generate() .expect("Unable to generate bindings!"); From c5d8cd8bcf7fbb9849121105abc9708e24a9f9ea Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Thu, 24 Apr 2025 19:40:05 +0200 Subject: [PATCH 28/30] update proc-macro2 in minimal-versin check --- .github/workflows/ci.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index cd8bf49..48babc1 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -29,6 +29,9 @@ jobs: - uses: dtolnay/rust-toolchain@nightly - name: Generate minimal-version dependencies run: cargo -Zminimal-versions generate-lockfile + # The latest bindgen release has an underspecified proc-macro2 dependency: https://github.com/rust-lang/rust-bindgen/issues/3149 + - name: Update proc-macro2 to 1.0.80 + run: cargo update -p proc-macro2 --precise 1.0.80 - uses: dtolnay/rust-toolchain@1.74.0 - name: Cargo check run: cargo check --workspace --all-targets From 147179a0323aa1b2a2c6e31691ec4cb7b24ef572 Mon Sep 17 00:00:00 2001 From: Max de Danschutter <43446207+maxded@users.noreply.github.com> Date: Fri, 25 Apr 2025 10:04:03 +0200 Subject: [PATCH 29/30] Update Cargo.toml Co-authored-by: Marijn Suijten --- Cargo.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Cargo.toml b/Cargo.toml index 6a52b42..0a9c292 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -20,5 +20,5 @@ serde = { version = "1", features = ["derive", "rc"] } serde_json = "1" [build-dependencies] -bindgen = { version = "0.71" } +bindgen = "0.71" cc = "1.1" From 4d17aaee34b52908d21c24e6ca93f2b62087b1df Mon Sep 17 00:00:00 2001 From: Max de Danschutter Date: Fri, 25 Apr 2025 10:07:04 +0200 Subject: [PATCH 30/30] feedback --- build.rs | 1 + src/lib.rs | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/build.rs b/build.rs index 798e5e5..4b8b7cf 100644 --- a/build.rs +++ b/build.rs @@ -141,6 +141,7 @@ fn generate_bindings() { let dest = std::env::var("OUT_DIR").unwrap(); let dest = std::path::Path::new(&dest).join("bindings.rs"); + // Use MSRV for target version. let Ok(version) = bindgen::RustTarget::stable(74, 0) else { panic!("Invalid rust target version"); }; diff --git a/src/lib.rs b/src/lib.rs index 3199eb4..4b17a24 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -325,7 +325,7 @@ pub struct Core { pub vendor: Vendor, #[doc = " CPU microarchitecture for this core"] pub uarch: Uarch, - #[doc = " Value of CPUID leaf 1 EAX register for this core (x86-specific ID)"] + #[doc = " Value of CPUID leaf 1 EAX register for this core (x86/x64-specific ID)"] pub cpuid: Option, #[doc = " Value of Main ID Register (MIDR) for this core (arm/aarch64-specific ID)"] pub midr: Option, @@ -351,9 +351,9 @@ pub struct Cluster { pub vendor: Vendor, #[doc = " CPU microarchitecture of the cores in the cluster"] pub uarch: Uarch, - #[doc = " Value of CPUID leaf 1 EAX register for this core (x86-specific ID)"] + #[doc = " Value of CPUID leaf 1 EAX register for this core (x86/x64-specific ID)"] pub cpuid: Option, - #[doc = " Value of Main ID Register (MIDR) for this core (arm-specific ID)"] + #[doc = " Value of Main ID Register (MIDR) for this core (arm/aarch64-specific ID)"] pub midr: Option, #[doc = " Clock rate (non-Turbo) of the cores in the cluster, in Hz"] pub frequency: u64, @@ -390,9 +390,9 @@ pub struct Uarch { pub struct UarchInfo { #[doc = " Type of CPU microarchitecture"] pub uarch: Uarch, - #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture (x86-specific ID)"] + #[doc = " Value of CPUID leaf 1 EAX register for the microarchitecture (x86/x64-specific ID)"] pub cpuid: Option, - #[doc = " Value of Main ID Register (MIDR) for this core (arm-specific ID)"] + #[doc = " Value of Main ID Register (MIDR) for this core (arm/aarch64-specific ID)"] pub midr: Option, #[doc = " Number of logical processors with the microarchitecture"] pub processor_count: u32,