Merge pull request #32 from nblei/master

Removed unneeded conditional

verilog-stdlib/stochastic/stoch_add.sv

@@ -30,9 +30,6 @@ always @(posedge CLK) begin
     else counter <= next_counter;
 end
 
-always @(c, y) begin
-    if (~|c & y) next_counter <= {COUNTER_SIZE{1'b0}};
-    else next_counter <= c - y;
-end
+assign next_counter = c - y;
 
 endmodule