diff --git a/ChangeLog b/ChangeLog index fb4c214bdc..ee4e3fb748 100644 --- a/ChangeLog +++ b/ChangeLog @@ -194,7 +194,7 @@ Improvements: - Fix eflags effects for adc/sbb (#1798) - Update x86 operand access information (#1801) - CI automatically build release tarball (#1802) -- Dont format sstreams when there's nothing to format (#1805) +- Don't format sstreams when there's nothing to format (#1805) - Fix warning about Unused variables (#1815) - Fix insn initialization when instruction have no operands or have a prefix (#1816) - Avoid abort() if x86 not supported (#1818) diff --git a/MCInst.h b/MCInst.h index 08a4f5891d..3c4bd34ad6 100644 --- a/MCInst.h +++ b/MCInst.h @@ -124,7 +124,7 @@ struct MCInst { // operand access index for list of registers sharing the same access right (for ARM) uint8_t ac_idx; uint8_t popcode_adjust; // Pseudo X86 instruction adjust - char assembly[8]; // for special instruction, so that we dont need printer + char assembly[8]; // for special instruction, so that we don't need printer unsigned char evm_data[32]; // for EVM PUSH operand cs_wasm_op wasm_data; // for WASM operand MCRegisterInfo *MRI; diff --git a/MCInstPrinter.h b/MCInstPrinter.h index d8c69fc462..0ccbb3f083 100644 --- a/MCInstPrinter.h +++ b/MCInstPrinter.h @@ -10,7 +10,7 @@ /// Returned by getMnemonic() of the AsmPrinters. typedef struct { - const char *first; // Menmonic + const char *first; // Mnemonic uint64_t second; // Bits } MnemonicBitsInfo; diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 2a208e3bda..6db42a21f5 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -181,7 +181,7 @@ void AArch64_add_vas(MCInst *MI, const SStream *OS) { } vl |= (num << 8); - // Determine op index by searching for trainling commata after op string + // Determine op index by searching for trailing commata after op string uint32_t op_idx = 0; const char *comma_ptr = strchr(OS->buffer, ',');; while (comma_ptr && comma_ptr < vl_ptr) { @@ -1084,7 +1084,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, const char *Dot = strstr(RegName, "."); AArch64Layout_VectorLayout vas = AArch64Layout_Invalid; if (!Dot) { - // The matrix dimensions are machine dependendent. + // The matrix dimensions are machine dependent. // Currently we do not support differentiation of machines. // So we just indicate the use of the complete matrix. vas = sme_reg_to_vas(MCInst_getOpVal(MI, OpNum)); @@ -1353,7 +1353,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, const char *Dot = strstr(RegName, "."); AArch64Layout_VectorLayout vas = AArch64Layout_Invalid; if (!Dot) { - // The matrix dimensions are machine dependendent. + // The matrix dimensions are machine dependent. // Currently we do not support differentiation of machines. // So we just indicate the use of the complete matrix. vas = sme_reg_to_vas(MCInst_getOpVal(MI, OpNum)); diff --git a/arch/TriCore/TriCoreInstPrinter.c b/arch/TriCore/TriCoreInstPrinter.c index c205adf924..342ee89563 100644 --- a/arch/TriCore/TriCoreInstPrinter.c +++ b/arch/TriCore/TriCoreInstPrinter.c @@ -460,7 +460,7 @@ static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) /// Returned by getMnemonic() of the AsmPrinters. typedef struct { - const char *first; // Menmonic + const char *first; // Mnemonic uint64_t second; // Bits } MnemonicBitsInfo; diff --git a/arch/XCore/XCoreDisassembler.c b/arch/XCore/XCoreDisassembler.c index c095240a5b..a2849c739c 100644 --- a/arch/XCore/XCoreDisassembler.c +++ b/arch/XCore/XCoreDisassembler.c @@ -238,7 +238,7 @@ static DecodeStatus Decode3OpInstruction(unsigned Insn, static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - // Try and decode as a 3R instruction. + // Try to decode as a 3R instruction. unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); switch (Opcode) { case 0x0: @@ -409,7 +409,7 @@ static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - // Try and decode as a L3R / L2RUS instruction. + // Try to decode as a L3R / L2RUS instruction. unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | fieldFromInstruction_4(Insn, 27, 5) << 4; switch (Opcode) { @@ -650,7 +650,7 @@ static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64 { unsigned Opcode; - // Try and decode as a L6R instruction. + // Try to decode as a L6R instruction. MCInst_clear(Inst); Opcode = fieldFromInstruction_4(Insn, 27, 5); switch (Opcode) { diff --git a/bindings/python/pyx/ccapstone.pyx b/bindings/python/pyx/ccapstone.pyx index efdc8561ac..d1a9aceb07 100644 --- a/bindings/python/pyx/ccapstone.pyx +++ b/bindings/python/pyx/ccapstone.pyx @@ -335,7 +335,7 @@ cdef class Cs(object): # unlike disasm(), disasm_lite() only return tuples of (address, size, mnemonic, op_str), # rather than CsInsn objects. def disasm_lite(self, code, addr, count=0): - # TODO: dont need detail, so we might turn off detail, then turn on again when done + # TODO: don't need detail, so we might turn off detail, then turn on again when done cdef cc.cs_insn *allinsn if _diet: diff --git a/bindings/vb6/CX86Inst.cls b/bindings/vb6/CX86Inst.cls index 70e62258d4..f3a2229ae3 100644 --- a/bindings/vb6/CX86Inst.cls +++ b/bindings/vb6/CX86Inst.cls @@ -183,7 +183,7 @@ Friend Sub LoadDetails(lpStruct As Long, parent As CDisassembler) m_prefix = cs.prefix m_opcode = cs.opcode - ptr = lpStruct + LenB(cs) 'we dont include the operands in our vb struct.. + ptr = lpStruct + LenB(cs) 'we don't include the operands in our vb struct.. For i = 1 To cs.op_count Set o = New CX86Operand o.LoadDetails ptr, hEngine diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h index b937f2f284..c46328fdec 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h @@ -981,7 +981,7 @@ class TargetInstrInfo : public MCInstrInfo { protected: /// Target-dependent implementation for IsCopyInstr. - /// If the specific machine instruction is a instruction that moves/copies + /// If the specific machine instruction is an instruction that moves/copies /// value from one register to another register return destination and source /// registers as machine operands. virtual Optional @@ -1001,7 +1001,7 @@ class TargetInstrInfo : public MCInstrInfo { } public: - /// If the specific machine instruction is a instruction that moves/copies + /// If the specific machine instruction is an instruction that moves/copies /// value from one register to another register return destination and source /// registers as machine operands. /// For COPY-instruction the method naturally returns destination and source diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h index db9ce345c4..959754bad4 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h @@ -129,7 +129,7 @@ // a. CFG Checksum (a.k.a. function hash): // !CFGChecksum: 12345 // b. CFG Checksum (see ContextAttributeMask): -// !Atribute: 1 +// !Attribute: 1 // // // Binary format diff --git a/xcode/README.md b/xcode/README.md index 7f21900eab..64b44d77b7 100644 --- a/xcode/README.md +++ b/xcode/README.md @@ -1,7 +1,7 @@ Xcode Project for Capstone ================================================================================ -The *Capstone.xcodeproj* project is an Xcode project that mimicks the Visual +The *Capstone.xcodeproj* project is an Xcode project that mimics the Visual Studio solution for Capstone. It embeds nicely into Xcode workspaces. It has 13 targets, two of which are the most likely to be of interest: